1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2022 Toradex
6 * Generated code from MX8M_DDR_tool
8 * Align with uboot version:
9 * imx_v2019.04_5.4.x and above version
10 * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
11 * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
14 #include <linux/kernel.h>
15 #include <asm/arch/ddr.h>
17 struct dram_cfg_param ddr_ddrc_cfg[] = {
18 /** Initialize DDRC registers **/
21 { 0x3d400000, 0xa3080020 },
22 { 0x3d400020, 0x1303 },
23 { 0x3d400024, 0x1e84800 },
24 { 0x3d400064, 0x7a0118 },
25 { 0x3d400070, 0x61027f10 },
26 { 0x3d400074, 0x7b0 },
27 { 0x3d4000d0, 0xc00307a3 },
28 { 0x3d4000d4, 0xc50000 },
29 { 0x3d4000dc, 0xf4003f },
30 { 0x3d4000e0, 0x330000 },
31 { 0x3d4000e8, 0x660048 },
32 { 0x3d4000ec, 0x160048 },
33 { 0x3d400100, 0x2028222a },
34 { 0x3d400104, 0x807bf },
35 { 0x3d40010c, 0xe0e000 },
36 { 0x3d400110, 0x12040a12 },
37 { 0x3d400114, 0x2050f0f },
38 { 0x3d400118, 0x1010009 },
39 { 0x3d40011c, 0x501 },
40 { 0x3d400130, 0x20800 },
41 { 0x3d400134, 0xe100002 },
42 { 0x3d400138, 0x120 },
43 { 0x3d400144, 0xc80064 },
44 { 0x3d400180, 0x3e8001e },
45 { 0x3d400184, 0x3207a12 },
47 { 0x3d400190, 0x49f820e },
48 { 0x3d400194, 0x80303 },
49 { 0x3d4001b4, 0x1f0e },
50 { 0x3d4001a0, 0xe0400018 },
51 { 0x3d4001a4, 0xdf00e4 },
52 { 0x3d4001a8, 0x80000000 },
56 { 0x3d4000f4, 0xc99 },
57 { 0x3d400108, 0x9121c1c },
60 { 0x3d400210, 0x1f1f },
61 { 0x3d400204, 0x80808 },
62 { 0x3d400214, 0x7070707 },
63 { 0x3d400218, 0x7070707 },
64 { 0x3d40021c, 0xf07 },
65 { 0x3d400250, 0x1705 },
67 { 0x3d40025c, 0x4000030 },
68 { 0x3d400264, 0x900093e7 },
69 { 0x3d40026c, 0x2005574 },
70 { 0x3d400400, 0x111 },
71 { 0x3d400404, 0x72ff },
72 { 0x3d400408, 0x72ff },
73 { 0x3d400494, 0x2100e07 },
74 { 0x3d400498, 0x620096 },
75 { 0x3d40049c, 0x1100e07 },
76 { 0x3d4004a0, 0xc8012c },
77 { 0x3d402020, 0x1001 },
78 { 0x3d402024, 0x30d400 },
79 { 0x3d402050, 0x20d000 },
80 { 0x3d402064, 0xc001c },
81 { 0x3d4020dc, 0x840000 },
82 { 0x3d4020e0, 0x330000 },
83 { 0x3d4020e8, 0x660048 },
84 { 0x3d4020ec, 0x160048 },
85 { 0x3d402100, 0xa040305 },
86 { 0x3d402104, 0x30407 },
87 { 0x3d402108, 0x203060b },
88 { 0x3d40210c, 0x505000 },
89 { 0x3d402110, 0x2040202 },
90 { 0x3d402114, 0x2030202 },
91 { 0x3d402118, 0x1010004 },
92 { 0x3d40211c, 0x301 },
93 { 0x3d402130, 0x20300 },
94 { 0x3d402134, 0xa100002 },
96 { 0x3d402144, 0x14000a },
97 { 0x3d402180, 0x640004 },
98 { 0x3d402190, 0x3818200 },
99 { 0x3d402194, 0x80303 },
100 { 0x3d4021b4, 0x100 },
101 { 0x3d4020f4, 0xc99 },
102 { 0x3d403020, 0x1001 },
103 { 0x3d403024, 0xc3500 },
104 { 0x3d403050, 0x20d000 },
105 { 0x3d403064, 0x30007 },
106 { 0x3d4030dc, 0x840000 },
107 { 0x3d4030e0, 0x330000 },
108 { 0x3d4030e8, 0x660048 },
109 { 0x3d4030ec, 0x160048 },
110 { 0x3d403100, 0xa010102 },
111 { 0x3d403104, 0x30404 },
112 { 0x3d403108, 0x203060b },
113 { 0x3d40310c, 0x505000 },
114 { 0x3d403110, 0x2040202 },
115 { 0x3d403114, 0x2030202 },
116 { 0x3d403118, 0x1010004 },
117 { 0x3d40311c, 0x301 },
118 { 0x3d403130, 0x20300 },
119 { 0x3d403134, 0xa100002 },
121 { 0x3d403144, 0x50003 },
122 { 0x3d403180, 0x190004 },
123 { 0x3d403190, 0x3818200 },
124 { 0x3d403194, 0x80303 },
125 { 0x3d4031b4, 0x100 },
126 { 0x3d4030f4, 0xc99 },
130 /* PHY Initialize Configuration */
131 struct dram_cfg_param ddr_ddrphy_cfg[] = {
339 /* ddr phy trained csr */
340 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
1062 /* P0 message block parameter for training firmware */
1063 struct dram_cfg_param ddr_fsp0_cfg[] = {
1067 { 0x54005, 0x2228 },
1069 { 0x54008, 0x131f },
1074 { 0x54019, 0x3ff4 },
1076 { 0x5401b, 0x4866 },
1077 { 0x5401c, 0x4800 },
1079 { 0x5401f, 0x3ff4 },
1081 { 0x54021, 0x4866 },
1082 { 0x54022, 0x4800 },
1084 { 0x5402b, 0x1000 },
1086 { 0x54032, 0xf400 },
1087 { 0x54033, 0x333f },
1088 { 0x54034, 0x6600 },
1091 { 0x54037, 0x1600 },
1092 { 0x54038, 0xf400 },
1093 { 0x54039, 0x333f },
1094 { 0x5403a, 0x6600 },
1097 { 0x5403d, 0x1600 },
1101 /* P1 message block parameter for training firmware */
1102 struct dram_cfg_param ddr_fsp1_cfg[] = {
1107 { 0x54005, 0x2228 },
1109 { 0x54008, 0x121f },
1116 { 0x5401b, 0x4866 },
1117 { 0x5401c, 0x4800 },
1121 { 0x54021, 0x4866 },
1122 { 0x54022, 0x4800 },
1124 { 0x5402b, 0x1000 },
1126 { 0x54032, 0x8400 },
1127 { 0x54033, 0x3300 },
1128 { 0x54034, 0x6600 },
1131 { 0x54037, 0x1600 },
1132 { 0x54038, 0x8400 },
1133 { 0x54039, 0x3300 },
1134 { 0x5403a, 0x6600 },
1137 { 0x5403d, 0x1600 },
1141 /* P2 message block parameter for training firmware */
1142 struct dram_cfg_param ddr_fsp2_cfg[] = {
1147 { 0x54005, 0x2228 },
1149 { 0x54008, 0x121f },
1156 { 0x5401b, 0x4866 },
1157 { 0x5401c, 0x4800 },
1161 { 0x54021, 0x4866 },
1162 { 0x54022, 0x4800 },
1164 { 0x5402b, 0x1000 },
1166 { 0x54032, 0x8400 },
1167 { 0x54033, 0x3300 },
1168 { 0x54034, 0x6600 },
1171 { 0x54037, 0x1600 },
1172 { 0x54038, 0x8400 },
1173 { 0x54039, 0x3300 },
1174 { 0x5403a, 0x6600 },
1177 { 0x5403d, 0x1600 },
1181 /* P0 2D message block parameter for training firmware */
1182 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1186 { 0x54005, 0x2228 },
1192 { 0x54010, 0x1f7f },
1194 { 0x54019, 0x3ff4 },
1196 { 0x5401b, 0x4866 },
1197 { 0x5401c, 0x4800 },
1199 { 0x5401f, 0x3ff4 },
1201 { 0x54021, 0x4866 },
1202 { 0x54022, 0x4800 },
1204 { 0x5402b, 0x1000 },
1206 { 0x54032, 0xf400 },
1207 { 0x54033, 0x333f },
1208 { 0x54034, 0x6600 },
1211 { 0x54037, 0x1600 },
1212 { 0x54038, 0xf400 },
1213 { 0x54039, 0x333f },
1214 { 0x5403a, 0x6600 },
1217 { 0x5403d, 0x1600 },
1221 /* DRAM PHY init engine image */
1222 struct dram_cfg_param ddr_phy_pie[] = {
1281 { 0x9005c, 0x40c0 },
1287 { 0x90062, 0x4040 },
1357 { 0x40001, 0x4008 },
1361 { 0x40002, 0x4040 },
1371 { 0x40044, 0x1740 },
1379 { 0x40046, 0x2001 },
1383 { 0x40047, 0x2800 },
1391 { 0x40049, 0x1400 },
1401 { 0x4000c, 0x4028 },
1413 { 0x4000f, 0x4040 },
1417 { 0x40010, 0x2604 },
1424 { 0x40071, 0x2002 },
1429 { 0x40013, 0x2604 },
1436 { 0x40074, 0x2002 },
1437 { 0x40015, 0x4040 },
1443 { 0x40056, 0x1200 },
1447 { 0x40057, 0x1300 },
1451 { 0x40058, 0x1200 },
1455 { 0x40059, 0x1300 },
1457 { 0x4001a, 0x4808 },
1498 { 0x900c9, 0x8568 },
1507 { 0x900d2, 0x8558 },
1512 { 0x900d7, 0x1ff8 },
1513 { 0x900d8, 0x85a8 },
1522 { 0x900e1, 0x8310 },
1525 { 0x900e4, 0xa310 },
1537 { 0x900f0, 0x8310 },
1540 { 0x900f3, 0xa310 },
1542 { 0x900f5, 0x1ff8 },
1543 { 0x900f6, 0x85a8 },
1555 { 0x90102, 0x8b10 },
1558 { 0x90105, 0xab10 },
1570 { 0x90111, 0x8b10 },
1573 { 0x90114, 0xab10 },
1588 { 0x90123, 0x8080 },
1603 { 0x90132, 0x8080 },
1609 { 0x90138, 0x8568 },
1618 { 0x90141, 0x8558 },
1630 { 0x9014d, 0x8558 },
1645 { 0x9015c, 0x8140 },
1648 { 0x9015f, 0x8138 },
1672 { 0x90177, 0x8140 },
1718 { 0x9000f, 0x6110 },
1719 { 0x90010, 0x2152 },
1720 { 0x90011, 0xdfbd },
1721 { 0x90012, 0x2060 },
1722 { 0x90013, 0x6152 },
1748 { 0x10002, 0x6209 },
1762 { 0x11002, 0x6209 },
1776 { 0x12002, 0x6209 },
1790 { 0x13002, 0x6209 },
1806 struct dram_fsp_msg ddr_dram_fsp_msg[] = {
1810 .fw_type = FW_1D_IMAGE,
1811 .fsp_cfg = ddr_fsp0_cfg,
1812 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
1817 .fw_type = FW_1D_IMAGE,
1818 .fsp_cfg = ddr_fsp1_cfg,
1819 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
1824 .fw_type = FW_1D_IMAGE,
1825 .fsp_cfg = ddr_fsp2_cfg,
1826 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
1831 .fw_type = FW_2D_IMAGE,
1832 .fsp_cfg = ddr_fsp0_2d_cfg,
1833 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
1837 struct dram_cfg_param ddr_ddrc_cfg2[] = {
1838 /** Initialize DDRC registers **/
1839 { 0x3d400304, 0x1 },
1840 { 0x3d400030, 0x1 },
1841 { 0x3d400000, 0xa1080020 },
1842 { 0x3d400020, 0x1303 },
1843 { 0x3d400024, 0x1e84800 },
1844 { 0x3d400064, 0x7a0118 },
1845 { 0x3d400070, 0x61027f10 },
1846 { 0x3d400074, 0x7b0 },
1847 { 0x3d4000d0, 0xc00307a3 },
1848 { 0x3d4000d4, 0xc50000 },
1849 { 0x3d4000dc, 0xf4003f },
1850 { 0x3d4000e0, 0x330000 },
1851 { 0x3d4000e8, 0x660048 },
1852 { 0x3d4000ec, 0x160048 },
1853 { 0x3d400100, 0x2028222a },
1854 { 0x3d400104, 0x807bf },
1855 { 0x3d40010c, 0xe0e000 },
1856 { 0x3d400110, 0x12040a12 },
1857 { 0x3d400114, 0x2050f0f },
1858 { 0x3d400118, 0x1010009 },
1859 { 0x3d40011c, 0x501 },
1860 { 0x3d400130, 0x20800 },
1861 { 0x3d400134, 0xe100002 },
1862 { 0x3d400138, 0x120 },
1863 { 0x3d400144, 0xc80064 },
1864 { 0x3d400180, 0x3e8001e },
1865 { 0x3d400184, 0x3207a12 },
1866 { 0x3d400188, 0x0 },
1867 { 0x3d400190, 0x49f820e },
1868 { 0x3d400194, 0x80303 },
1869 { 0x3d4001b4, 0x1f0e },
1870 { 0x3d4001a0, 0xe0400018 },
1871 { 0x3d4001a4, 0xdf00e4 },
1872 { 0x3d4001a8, 0x80000000 },
1873 { 0x3d4001b0, 0x11 },
1874 { 0x3d4001c0, 0x1 },
1875 { 0x3d4001c4, 0x1 },
1876 { 0x3d4000f4, 0xc99 },
1877 { 0x3d400108, 0x9121c1c },
1878 { 0x3d400200, 0x1f },
1879 { 0x3d40020c, 0x0 },
1880 { 0x3d400210, 0x1f1f },
1881 { 0x3d400204, 0x80808 },
1882 { 0x3d400214, 0x7070707 },
1883 { 0x3d400218, 0x7070707 },
1884 { 0x3d40021c, 0xf07 },
1885 { 0x3d400250, 0x1705 },
1886 { 0x3d400254, 0x2c },
1887 { 0x3d40025c, 0x4000030 },
1888 { 0x3d400264, 0x900093e7 },
1889 { 0x3d40026c, 0x2005574 },
1890 { 0x3d400400, 0x111 },
1891 { 0x3d400404, 0x72ff },
1892 { 0x3d400408, 0x72ff },
1893 { 0x3d400494, 0x2100e07 },
1894 { 0x3d400498, 0x620096 },
1895 { 0x3d40049c, 0x1100e07 },
1896 { 0x3d4004a0, 0xc8012c },
1897 { 0x3d402020, 0x1001 },
1898 { 0x3d402024, 0x30d400 },
1899 { 0x3d402050, 0x20d000 },
1900 { 0x3d402064, 0xc001c },
1901 { 0x3d4020dc, 0x840000 },
1902 { 0x3d4020e0, 0x330000 },
1903 { 0x3d4020e8, 0x660048 },
1904 { 0x3d4020ec, 0x160048 },
1905 { 0x3d402100, 0xa040305 },
1906 { 0x3d402104, 0x30407 },
1907 { 0x3d402108, 0x203060b },
1908 { 0x3d40210c, 0x505000 },
1909 { 0x3d402110, 0x2040202 },
1910 { 0x3d402114, 0x2030202 },
1911 { 0x3d402118, 0x1010004 },
1912 { 0x3d40211c, 0x301 },
1913 { 0x3d402130, 0x20300 },
1914 { 0x3d402134, 0xa100002 },
1915 { 0x3d402138, 0x1d },
1916 { 0x3d402144, 0x14000a },
1917 { 0x3d402180, 0x640004 },
1918 { 0x3d402190, 0x3818200 },
1919 { 0x3d402194, 0x80303 },
1920 { 0x3d4021b4, 0x100 },
1921 { 0x3d4020f4, 0xc99 },
1922 { 0x3d403020, 0x1001 },
1923 { 0x3d403024, 0xc3500 },
1924 { 0x3d403050, 0x20d000 },
1925 { 0x3d403064, 0x30007 },
1926 { 0x3d4030dc, 0x840000 },
1927 { 0x3d4030e0, 0x330000 },
1928 { 0x3d4030e8, 0x660048 },
1929 { 0x3d4030ec, 0x160048 },
1930 { 0x3d403100, 0xa010102 },
1931 { 0x3d403104, 0x30404 },
1932 { 0x3d403108, 0x203060b },
1933 { 0x3d40310c, 0x505000 },
1934 { 0x3d403110, 0x2040202 },
1935 { 0x3d403114, 0x2030202 },
1936 { 0x3d403118, 0x1010004 },
1937 { 0x3d40311c, 0x301 },
1938 { 0x3d403130, 0x20300 },
1939 { 0x3d403134, 0xa100002 },
1940 { 0x3d403138, 0x8 },
1941 { 0x3d403144, 0x50003 },
1942 { 0x3d403180, 0x190004 },
1943 { 0x3d403190, 0x3818200 },
1944 { 0x3d403194, 0x80303 },
1945 { 0x3d4031b4, 0x100 },
1946 { 0x3d4030f4, 0xc99 },
1947 { 0x3d400028, 0x0 },
1950 /* P0 message block parameter for training firmware */
1951 struct dram_cfg_param ddr_fsp0_cfg2[] = {
1955 { 0x54005, 0x2228 },
1957 { 0x54008, 0x131f },
1962 { 0x54019, 0x3ff4 },
1964 { 0x5401b, 0x4866 },
1965 { 0x5401c, 0x4800 },
1967 { 0x5401f, 0x3ff4 },
1969 { 0x54021, 0x4866 },
1970 { 0x54022, 0x4800 },
1972 { 0x5402b, 0x1000 },
1974 { 0x54032, 0xf400 },
1975 { 0x54033, 0x333f },
1976 { 0x54034, 0x6600 },
1979 { 0x54037, 0x1600 },
1980 { 0x54038, 0xf400 },
1981 { 0x54039, 0x333f },
1982 { 0x5403a, 0x6600 },
1985 { 0x5403d, 0x1600 },
1989 /* P1 message block parameter for training firmware */
1990 struct dram_cfg_param ddr_fsp1_cfg2[] = {
1995 { 0x54005, 0x2228 },
1997 { 0x54008, 0x121f },
2004 { 0x5401b, 0x4866 },
2005 { 0x5401c, 0x4800 },
2009 { 0x54021, 0x4866 },
2010 { 0x54022, 0x4800 },
2012 { 0x5402b, 0x1000 },
2014 { 0x54032, 0x8400 },
2015 { 0x54033, 0x3300 },
2016 { 0x54034, 0x6600 },
2019 { 0x54037, 0x1600 },
2020 { 0x54038, 0x8400 },
2021 { 0x54039, 0x3300 },
2022 { 0x5403a, 0x6600 },
2025 { 0x5403d, 0x1600 },
2029 /* P2 message block parameter for training firmware */
2030 struct dram_cfg_param ddr_fsp2_cfg2[] = {
2035 { 0x54005, 0x2228 },
2037 { 0x54008, 0x121f },
2044 { 0x5401b, 0x4866 },
2045 { 0x5401c, 0x4800 },
2049 { 0x54021, 0x4866 },
2050 { 0x54022, 0x4800 },
2052 { 0x5402b, 0x1000 },
2054 { 0x54032, 0x8400 },
2055 { 0x54033, 0x3300 },
2056 { 0x54034, 0x6600 },
2059 { 0x54037, 0x1600 },
2060 { 0x54038, 0x8400 },
2061 { 0x54039, 0x3300 },
2062 { 0x5403a, 0x6600 },
2065 { 0x5403d, 0x1600 },
2069 /* P0 2D message block parameter for training firmware */
2070 struct dram_cfg_param ddr_fsp0_2d_cfg2[] = {
2074 { 0x54005, 0x2228 },
2081 { 0x54010, 0x1f7f },
2083 { 0x54019, 0x3ff4 },
2085 { 0x5401b, 0x4866 },
2086 { 0x5401c, 0x4800 },
2088 { 0x5401f, 0x3ff4 },
2090 { 0x54021, 0x4866 },
2091 { 0x54022, 0x4800 },
2093 { 0x5402b, 0x1000 },
2095 { 0x54032, 0xf400 },
2096 { 0x54033, 0x333f },
2097 { 0x54034, 0x6600 },
2100 { 0x54037, 0x1600 },
2101 { 0x54038, 0xf400 },
2102 { 0x54039, 0x333f },
2103 { 0x5403a, 0x6600 },
2106 { 0x5403d, 0x1600 },
2110 struct dram_fsp_msg ddr_dram_fsp_msg2[] = {
2114 .fw_type = FW_1D_IMAGE,
2115 .fsp_cfg = ddr_fsp0_cfg2,
2116 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg2),
2121 .fw_type = FW_1D_IMAGE,
2122 .fsp_cfg = ddr_fsp1_cfg2,
2123 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg2),
2128 .fw_type = FW_1D_IMAGE,
2129 .fsp_cfg = ddr_fsp2_cfg2,
2130 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg2),
2135 .fw_type = FW_2D_IMAGE,
2136 .fsp_cfg = ddr_fsp0_2d_cfg2,
2137 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg2),
2141 /* quad die, dual rank aka 8 GB DDR timing config params */
2142 struct dram_timing_info dram_timing = {
2143 .ddrc_cfg = ddr_ddrc_cfg,
2144 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
2145 .ddrphy_cfg = ddr_ddrphy_cfg,
2146 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
2147 .fsp_msg = ddr_dram_fsp_msg,
2148 .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
2149 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
2150 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
2151 .ddrphy_pie = ddr_phy_pie,
2152 .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
2153 .fsp_table = { 4000, 400, 100, },
2156 /* dual die, single rank aka 1 GB (untested), 2 GB or 4 GB DDR timing config params */
2157 struct dram_timing_info dram_timing2 = {
2158 .ddrc_cfg = ddr_ddrc_cfg2,
2159 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg2),
2160 .ddrphy_cfg = ddr_ddrphy_cfg,
2161 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
2162 .fsp_msg = ddr_dram_fsp_msg2,
2163 .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg2),
2164 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
2165 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
2166 .ddrphy_pie = ddr_phy_pie,
2167 .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
2168 .fsp_table = { 4000, 400, 100, },