board/toradex/verdin-imx8mm/verdin-imx8mm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2020 Toradex
   4  */
   5
   6 #include <common.h>
   7 #include <init.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/sys_proto.h>
  10 #include <asm/io.h>
  11 #include <miiphy.h>
  12 #include <netdev.h>
  13 #include <micrel.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 int dram_init(void)
  18 {
  19         /* rom_pointer[1] contains the size of TEE occupies */
  20         if (rom_pointer[1])
  21                 gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
  22         else
  23                 gd->ram_size = PHYS_SDRAM_SIZE;
  24
  25         return 0;
  26 }
  27
  28 #if IS_ENABLED(CONFIG_FEC_MXC)
  29 static int setup_fec(void)
  30 {
  31         struct iomuxc_gpr_base_regs *gpr =
  32                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  33
  34         /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  35         clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
  36
  37         return 0;
  38 }
  39
  40 int board_phy_config(struct phy_device *phydev)
  41 {
  42         int tmp;
  43
  44         switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
  45         case PHY_ID_KSZ9031:
  46                 /*
  47                  * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by
  48                  * default. The MAC and the layout don't add a skew between
  49                  * clock and data.
  50                  * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for
  51                  * the TXC path to get the required clock skews.
  52                  */
  53                 /* control data pad skew - devaddr = 0x02, register = 0x04 */
  54                 ksz9031_phy_extended_write(phydev, 0x02,
  55                                            MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  56                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
  57                                            0x0070);
  58                 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  59                 ksz9031_phy_extended_write(phydev, 0x02,
  60                                            MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  61                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
  62                                            0x7777);
  63                 /* tx data pad skew - devaddr = 0x02, register = 0x06 */
  64                 ksz9031_phy_extended_write(phydev, 0x02,
  65                                            MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  66                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
  67                                            0x0000);
  68                 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
  69                 ksz9031_phy_extended_write(phydev, 0x02,
  70                                            MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  71                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
  72                                            0x03f4);
  73                 break;
  74         case PHY_ID_KSZ9131:
  75         default:
  76                 /* read rxc dll control - devaddr = 0x2, register = 0x4c */
  77                 tmp = ksz9031_phy_extended_read(phydev, 0x02,
  78                                         MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
  79                                         MII_KSZ9031_MOD_DATA_NO_POST_INC);
  80                 /* disable rxdll bypass (enable 2ns skew delay on RXC) */
  81                 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
  82                 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
  83                 tmp = ksz9031_phy_extended_write(phydev, 0x02,
  84                                         MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
  85                                         MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
  86                 /* read txc dll control - devaddr = 0x02, register = 0x4d */
  87                 tmp = ksz9031_phy_extended_read(phydev, 0x02,
  88                                         MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
  89                                         MII_KSZ9031_MOD_DATA_NO_POST_INC);
  90                 /* disable txdll bypass (enable 2ns skew delay on TXC) */
  91                 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
  92                 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
  93                 tmp = ksz9031_phy_extended_write(phydev, 0x02,
  94                                         MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
  95                                         MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
  96                 break;
  97         }
  98
  99         if (phydev->drv->config)
 100                 phydev->drv->config(phydev);
 101         return 0;
 102 }
 103 #endif
 104
 105 int board_init(void)
 106 {
 107         if (IS_ENABLED(CONFIG_FEC_MXC))
 108                 setup_fec();
 109
 110         return 0;
 111 }
 112
 113 int board_mmc_get_env_dev(int devno)
 114 {
 115         return devno;
 116 }
 117
 118 int board_late_init(void)
 119 {
 120         return 0;
 121 }
 122
 123 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 124 int ft_board_setup(void *blob, bd_t *bd)
 125 {
 126         return 0;
 127 }
 128 #endif