board/toradex/verdin-imx8mm/verdin-imx8mm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2020 Toradex
   4  */
   5
   6 #include <common.h>
   7 #include <init.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/sys_proto.h>
  10 #include <asm/io.h>
  11 #include <miiphy.h>
  12 #include <netdev.h>
  13 #include <micrel.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 #if IS_ENABLED(CONFIG_FEC_MXC)
  18 static int setup_fec(void)
  19 {
  20         struct iomuxc_gpr_base_regs *gpr =
  21                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  22
  23         /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  24         clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
  25
  26         return 0;
  27 }
  28
  29 int board_phy_config(struct phy_device *phydev)
  30 {
  31         int tmp;
  32
  33         switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
  34         case PHY_ID_KSZ9031:
  35                 /*
  36                  * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by
  37                  * default. The MAC and the layout don't add a skew between
  38                  * clock and data.
  39                  * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for
  40                  * the TXC path to get the required clock skews.
  41                  */
  42                 /* control data pad skew - devaddr = 0x02, register = 0x04 */
  43                 ksz9031_phy_extended_write(phydev, 0x02,
  44                                            MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  45                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
  46                                            0x0070);
  47                 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  48                 ksz9031_phy_extended_write(phydev, 0x02,
  49                                            MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  50                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
  51                                            0x7777);
  52                 /* tx data pad skew - devaddr = 0x02, register = 0x06 */
  53                 ksz9031_phy_extended_write(phydev, 0x02,
  54                                            MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  55                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
  56                                            0x0000);
  57                 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
  58                 ksz9031_phy_extended_write(phydev, 0x02,
  59                                            MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  60                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
  61                                            0x03f4);
  62                 break;
  63         case PHY_ID_KSZ9131:
  64         default:
  65                 /* read rxc dll control - devaddr = 0x2, register = 0x4c */
  66                 tmp = ksz9031_phy_extended_read(phydev, 0x02,
  67                                         MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
  68                                         MII_KSZ9031_MOD_DATA_NO_POST_INC);
  69                 /* disable rxdll bypass (enable 2ns skew delay on RXC) */
  70                 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
  71                 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
  72                 tmp = ksz9031_phy_extended_write(phydev, 0x02,
  73                                         MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
  74                                         MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
  75                 /* read txc dll control - devaddr = 0x02, register = 0x4d */
  76                 tmp = ksz9031_phy_extended_read(phydev, 0x02,
  77                                         MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
  78                                         MII_KSZ9031_MOD_DATA_NO_POST_INC);
  79                 /* disable txdll bypass (enable 2ns skew delay on TXC) */
  80                 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
  81                 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
  82                 tmp = ksz9031_phy_extended_write(phydev, 0x02,
  83                                         MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
  84                                         MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
  85                 break;
  86         }
  87
  88         if (phydev->drv->config)
  89                 phydev->drv->config(phydev);
  90         return 0;
  91 }
  92 #endif
  93
  94 int board_init(void)
  95 {
  96         if (IS_ENABLED(CONFIG_FEC_MXC))
  97                 setup_fec();
  98
  99         return 0;
 100 }
 101
 102 int board_mmc_get_env_dev(int devno)
 103 {
 104         return devno;
 105 }
 106
 107 int board_late_init(void)
 108 {
 109         return 0;
 110 }
 111
 112 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 113 int ft_board_setup(void *blob, struct bd_info *bd)
 114 {
 115         return 0;
 116 }
 117 #endif