board/toradex/verdin-imx8mm/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2020 Toradex
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <image.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/ddr.h>
  13 #include <asm/arch/imx8mm_pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/io.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <cpu_func.h>
  19 #include <dm/device.h>
  20 #include <dm/device-internal.h>
  21 #include <dm/uclass.h>
  22 #include <dm/uclass-internal.h>
  23 #include <hang.h>
  24 #include <i2c.h>
  25 #include <power/bd71837.h>
  26 #include <power/pca9450.h>
  27 #include <power/pmic.h>
  28 #include <spl.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define I2C_PMIC_BUS_ID        1
  33
  34 int spl_board_boot_device(enum boot_device boot_dev_spl)
  35 {
  36         switch (boot_dev_spl) {
  37         case MMC1_BOOT:
  38                 return BOOT_DEVICE_MMC1;
  39         case SD2_BOOT:
  40         case MMC2_BOOT:
  41                 return BOOT_DEVICE_MMC2;
  42         case SD3_BOOT:
  43         case MMC3_BOOT:
  44                 return BOOT_DEVICE_MMC1;
  45         case USB_BOOT:
  46                 return BOOT_DEVICE_BOARD;
  47         default:
  48                 return BOOT_DEVICE_NONE;
  49         }
  50 }
  51
  52 void spl_dram_init(void)
  53 {
  54         ddr_init(&dram_timing);
  55 }
  56
  57 void spl_board_init(void)
  58 {
  59         /* Serial download mode */
  60         if (is_usb_boot()) {
  61                 puts("Back to ROM, SDP\n");
  62                 restore_boot_params();
  63         }
  64         puts("Normal Boot\n");
  65 }
  66
  67 #ifdef CONFIG_SPL_LOAD_FIT
  68 int board_fit_config_name_match(const char *name)
  69 {
  70         /* Just empty function now - can't decide what to choose */
  71         debug("%s: %s\n", __func__, name);
  72
  73         return 0;
  74 }
  75 #endif
  76
  77 #define UART_PAD_CTRL   (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
  78 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  79
  80 /* Verdin UART_3, Console/Debug UART */
  81 static iomux_v3_cfg_t const uart_pads[] = {
  82         IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  83         IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  84 };
  85
  86 static iomux_v3_cfg_t const wdog_pads[] = {
  87         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  88 };
  89
  90 int board_early_init_f(void)
  91 {
  92         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  93
  94         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  95
  96         set_wdog_reset(wdog);
  97
  98         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  99
 100         return 0;
 101 }
 102
 103 int power_init_board(void)
 104 {
 105         struct udevice *dev;
 106         int ret;
 107
 108         if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) {
 109                 ret = pmic_get("pmic", &dev);
 110                 if (ret == -ENODEV) {
 111                         puts("No pmic found\n");
 112                         return ret;
 113                 }
 114
 115                 if (ret != 0)
 116                         return ret;
 117
 118                 /* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
 119                 pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
 120
 121                 /* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */
 122                 pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
 123
 124                 /* set WDOG_B_CFG to cold reset */
 125                 pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
 126
 127                 pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
 128
 129                 return 0;
 130         }
 131
 132         return 0;
 133 }
 134
 135 void board_init_f(ulong dummy)
 136 {
 137         struct udevice *dev;
 138         int ret;
 139
 140         arch_cpu_init();
 141
 142         init_uart_clk(0);
 143
 144         board_early_init_f();
 145
 146         timer_init();
 147
 148         preloader_console_init();
 149
 150         /* Clear the BSS. */
 151         memset(__bss_start, 0, __bss_end - __bss_start);
 152
 153         ret = spl_early_init();
 154         if (ret) {
 155                 debug("spl_early_init() failed: %d\n", ret);
 156                 hang();
 157         }
 158
 159         ret = uclass_get_device_by_name(UCLASS_CLK,
 160                                         "clock-controller@30380000",
 161                                         &dev);
 162         if (ret < 0) {
 163                 printf("Failed to find clock node. Check device tree\n");
 164                 hang();
 165         }
 166
 167         enable_tzc380();
 168
 169         power_init_board();
 170
 171         /* DDR initialization */
 172         spl_dram_init();
 173
 174         board_init_r(NULL, 0);
 175 }