1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016-2018 Toradex AG
6 #include <asm/arch/clock.h>
7 #include <asm/arch/crm_regs.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/mx7-pins.h>
10 #include <asm/arch/sys_proto.h>
12 #include <asm/mach-imx/iomux-v3.h>
16 #include <dm/platform_data/serial_mxc.h>
17 #include <fdt_support.h>
18 #include <fsl_esdhc.h>
19 #include <jffs2/load_kernel.h>
20 #include <linux/sizes.h>
25 #include <power/pmic.h>
26 #include <power/rn5t567_pmic.h>
28 #include <usb/ehci-ci.h>
29 #include "../common/tdx-common.h"
31 DECLARE_GLOBAL_DATA_PTR;
33 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
34 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
36 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
37 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
39 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
41 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
42 PAD_CTL_DSE_3P3V_49OHM)
44 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
46 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
48 #define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
52 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
57 static iomux_v3_cfg_t const uart1_pads[] = {
58 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
59 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
60 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
61 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
64 #ifdef CONFIG_USB_EHCI_MX7
65 static iomux_v3_cfg_t const usb_cdet_pads[] = {
66 MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
70 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
71 static iomux_v3_cfg_t const gpmi_pads[] = {
72 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
73 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
74 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
75 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
76 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
77 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
78 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
79 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
80 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
81 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
82 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
83 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
84 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
85 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
86 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
89 static void setup_gpmi_nand(void)
91 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
93 /* NAND_USDHC_BUS_CLK is set in rom */
98 #ifdef CONFIG_VIDEO_MXS
99 static iomux_v3_cfg_t const lcd_pads[] = {
100 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
101 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
102 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
103 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
104 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
105 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
106 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
107 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
108 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
109 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
110 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
111 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
112 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
113 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
114 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
115 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
116 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
117 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
118 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
119 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
120 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
121 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
124 static iomux_v3_cfg_t const backlight_pads[] = {
126 MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
127 /* Backlight PWM<A> (multiplexed pin) */
128 MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
129 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
132 #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
133 #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
135 static int setup_lcd(void)
137 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
139 imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
142 gpio_request(GPIO_BL_ON, "BL_ON");
143 gpio_direction_output(GPIO_BL_ON, 1);
145 /* Set PWM<A> to full brightness (assuming inversed polarity) */
146 gpio_request(GPIO_PWM_A, "PWM<A>");
147 gpio_direction_output(GPIO_PWM_A, 0);
153 #ifdef CONFIG_FEC_MXC
154 static iomux_v3_cfg_t const fec1_pads[] = {
155 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
156 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
158 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
160 MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
161 MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
162 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
163 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
164 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
165 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
166 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
167 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
168 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
171 static void setup_iomux_fec(void)
173 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
177 static void setup_iomux_uart(void)
179 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
182 #ifdef CONFIG_FEC_MXC
183 int board_eth_init(bd_t *bis)
189 ret = fecmxc_initialize_multi(bis, 0,
190 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
192 printf("FEC1 MXC: %s:failed\n", __func__);
197 static int setup_fec(void)
199 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
200 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
202 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
204 * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
205 * and output it on the pin
207 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
208 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
209 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
211 /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
212 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
213 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
214 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
217 return set_clk_enet(ENET_50MHZ);
220 int board_phy_config(struct phy_device *phydev)
222 if (phydev->drv->config)
223 phydev->drv->config(phydev);
228 int board_early_init_f(void)
237 /* address of boot parameters */
238 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
240 #ifdef CONFIG_FEC_MXC
244 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
248 #ifdef CONFIG_VIDEO_MXS
252 #ifdef CONFIG_USB_EHCI_MX7
253 imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
254 gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
260 #ifdef CONFIG_DM_PMIC
261 int power_init_board(void)
268 ret = pmic_get("rn5t567", &dev);
271 ver = pmic_reg_read(dev, RN5T567_LSIVER);
272 reg = pmic_reg_read(dev, RN5T567_OTPVER);
274 printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
276 /* set judge and press timer of N_OE to minimal values */
277 pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
279 /* configure sleep slot for 3.3V Ethernet */
280 reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
281 reg = (reg & 0xf0) | reg >> 4;
282 pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
284 /* disable DCDC2 discharge to avoid backfeeding through VFB2 */
285 pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
287 /* configure sleep slot for ARM rail */
288 reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
289 reg = (reg & 0xf0) | reg >> 4;
290 pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
292 /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
293 pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
298 void reset_cpu(ulong addr)
302 pmic_get("rn5t567", &dev);
304 /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
305 pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
306 pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
309 * Re-power factor detection on PMIC side is not instant. 1ms
310 * proved to be enough time until reset takes effect.
318 printf("Model: Toradex Colibri iMX7%c\n",
319 is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
324 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
325 int ft_board_setup(void *blob, bd_t *bd)
327 #if defined(CONFIG_FDT_FIXUP_PARTITIONS)
328 static const struct node_info nodes[] = {
329 { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
330 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
333 /* Update partition nodes using info from mtdparts env var */
334 puts(" Updating MTD partitions...\n");
335 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
338 return ft_common_board_setup(blob, bd);
342 #ifdef CONFIG_USB_EHCI_MX7
343 static iomux_v3_cfg_t const usb_otg2_pads[] = {
344 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
347 int board_ehci_hcd_init(int port)
353 if (is_cpu_type(MXC_CPU_MX7S))
356 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
357 ARRAY_SIZE(usb_otg2_pads));
365 int board_usb_phy_mode(int port)
369 if (gpio_get_value(USB_CDET_GPIO))
370 return USB_INIT_DEVICE;
372 return USB_INIT_HOST;
375 return USB_INIT_HOST;