board/toradex/colibri-imx6ull/colibri-imx6ull.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Toradex AG
   4  */
   5 #include <common.h>
   6 #include <asm/arch/clock.h>
   7 #include <asm/arch/crm_regs.h>
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch-mx6/clock.h>
  10 #include <asm/arch-mx6/imx-regs.h>
  11 #include <asm/arch-mx6/mx6ull_pins.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/gpio.h>
  14 #include <asm/mach-imx/boot_mode.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/io.h>
  17 #include <common.h>
  18 #include <dm.h>
  19 #include <dm/platform_data/serial_mxc.h>
  20 #include <fdt_support.h>
  21 #include <fsl_esdhc.h>
  22 #include <imx_thermal.h>
  23 #include <jffs2/load_kernel.h>
  24 #include <linux/sizes.h>
  25 #include <mmc.h>
  26 #include <miiphy.h>
  27 #include <mtd_node.h>
  28 #include <netdev.h>
  29 #include <usb.h>
  30 #include <usb/ehci-ci.h>
  31 #include "../common/tdx-common.h"
  32 #include "../common/tdx-cfg-block.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  37         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  38         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  41         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  46 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_40ohm)
  47
  48 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm)
  49
  50 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
  51                 PAD_CTL_DSE_48ohm)
  52
  53 #define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  54
  55 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
  56
  57 #define USB_CDET_GPIO   IMX_GPIO_NR(7, 14)
  58
  59 int dram_init(void)
  60 {
  61         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  62
  63         return 0;
  64 }
  65
  66 static iomux_v3_cfg_t const uart1_pads[] = {
  67         MX6_PAD_UART1_TX_DATA__UART1_DTE_RX     | MUX_PAD_CTRL(UART_PAD_CTRL),
  68         MX6_PAD_UART1_RX_DATA__UART1_DTE_TX     | MUX_PAD_CTRL(UART_PAD_CTRL),
  69         MX6_PAD_UART1_RTS_B__UART1_DTE_CTS      | MUX_PAD_CTRL(UART_PAD_CTRL),
  70         MX6_PAD_UART1_CTS_B__UART1_DTE_RTS      | MUX_PAD_CTRL(UART_PAD_CTRL),
  71 };
  72
  73 #ifdef CONFIG_FSL_ESDHC
  74 static iomux_v3_cfg_t const usdhc1_pads[] = {
  75         MX6_PAD_SD1_CLK__USDHC1_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76         MX6_PAD_SD1_CMD__USDHC1_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81
  82         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  83 };
  84 #endif
  85
  86 static iomux_v3_cfg_t const usb_cdet_pads[] = {
  87         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  88 };
  89
  90 #ifdef CONFIG_NAND_MXS
  91 static iomux_v3_cfg_t const gpmi_pads[] = {
  92         MX6_PAD_NAND_DATA00__RAWNAND_DATA00     | MUX_PAD_CTRL(NAND_PAD_CTRL),
  93         MX6_PAD_NAND_DATA01__RAWNAND_DATA01     | MUX_PAD_CTRL(NAND_PAD_CTRL),
  94         MX6_PAD_NAND_DATA02__RAWNAND_DATA02     | MUX_PAD_CTRL(NAND_PAD_CTRL),
  95         MX6_PAD_NAND_DATA03__RAWNAND_DATA03     | MUX_PAD_CTRL(NAND_PAD_CTRL),
  96         MX6_PAD_NAND_DATA04__RAWNAND_DATA04     | MUX_PAD_CTRL(NAND_PAD_CTRL),
  97         MX6_PAD_NAND_DATA05__RAWNAND_DATA05     | MUX_PAD_CTRL(NAND_PAD_CTRL),
  98         MX6_PAD_NAND_DATA06__RAWNAND_DATA06     | MUX_PAD_CTRL(NAND_PAD_CTRL),
  99         MX6_PAD_NAND_DATA07__RAWNAND_DATA07     | MUX_PAD_CTRL(NAND_PAD_CTRL),
 100         MX6_PAD_NAND_CLE__RAWNAND_CLE           | MUX_PAD_CTRL(NAND_PAD_CTRL),
 101         MX6_PAD_NAND_ALE__RAWNAND_ALE           | MUX_PAD_CTRL(NAND_PAD_CTRL),
 102         MX6_PAD_NAND_RE_B__RAWNAND_RE_B         | MUX_PAD_CTRL(NAND_PAD_CTRL),
 103         MX6_PAD_NAND_WE_B__RAWNAND_WE_B         | MUX_PAD_CTRL(NAND_PAD_CTRL),
 104         MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
 105         MX6_PAD_NAND_READY_B__RAWNAND_READY_B   | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
 106 };
 107
 108 static void setup_gpmi_nand(void)
 109 {
 110         imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
 111
 112         setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
 113                           (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
 114 }
 115 #endif
 116
 117 #ifdef CONFIG_VIDEO_MXS
 118 static iomux_v3_cfg_t const lcd_pads[] = {
 119         MX6_PAD_LCD_CLK__LCDIF_CLK              | MUX_PAD_CTRL(LCD_PAD_CTRL),
 120         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 121         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC          | MUX_PAD_CTRL(LCD_PAD_CTRL),
 122         MX6_PAD_LCD_CLK__LCDIF_CLK              | MUX_PAD_CTRL(LCD_PAD_CTRL),
 123         MX6_PAD_LCD_DATA00__LCDIF_DATA00        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 124         MX6_PAD_LCD_DATA01__LCDIF_DATA01        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 125         MX6_PAD_LCD_DATA02__LCDIF_DATA02        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 126         MX6_PAD_LCD_DATA03__LCDIF_DATA03        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 127         MX6_PAD_LCD_DATA04__LCDIF_DATA04        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 128         MX6_PAD_LCD_DATA05__LCDIF_DATA05        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 129         MX6_PAD_LCD_DATA06__LCDIF_DATA06        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 130         MX6_PAD_LCD_DATA07__LCDIF_DATA07        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 131         MX6_PAD_LCD_DATA08__LCDIF_DATA08        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 132         MX6_PAD_LCD_DATA09__LCDIF_DATA09        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 133         MX6_PAD_LCD_DATA10__LCDIF_DATA10        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 134         MX6_PAD_LCD_DATA11__LCDIF_DATA11        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 135         MX6_PAD_LCD_DATA12__LCDIF_DATA12        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 136         MX6_PAD_LCD_DATA13__LCDIF_DATA13        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 137         MX6_PAD_LCD_DATA14__LCDIF_DATA14        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 138         MX6_PAD_LCD_DATA15__LCDIF_DATA15        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 139         MX6_PAD_LCD_DATA16__LCDIF_DATA16        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 140         MX6_PAD_LCD_DATA17__LCDIF_DATA17        | MUX_PAD_CTRL(LCD_PAD_CTRL),
 141 };
 142
 143 static iomux_v3_cfg_t const backlight_pads[] = {
 144         /* Backlight On */
 145         MX6_PAD_JTAG_TMS__GPIO1_IO11            | MUX_PAD_CTRL(NO_PAD_CTRL),
 146         /* Backlight PWM<A> (multiplexed pin) */
 147         MX6_PAD_NAND_WP_B__GPIO4_IO11           | MUX_PAD_CTRL(NO_PAD_CTRL),
 148 };
 149
 150 #define GPIO_BL_ON IMX_GPIO_NR(1, 11)
 151 #define GPIO_PWM_A IMX_GPIO_NR(4, 11)
 152
 153 static int setup_lcd(void)
 154 {
 155         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 156
 157         imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
 158
 159         /* Set BL_ON */
 160         gpio_request(GPIO_BL_ON, "BL_ON");
 161         gpio_direction_output(GPIO_BL_ON, 1);
 162
 163         /* Set PWM<A> to full brightness (assuming inversed polarity) */
 164         gpio_request(GPIO_PWM_A, "PWM<A>");
 165         gpio_direction_output(GPIO_PWM_A, 0);
 166
 167         return 0;
 168 }
 169 #endif
 170
 171 #ifdef CONFIG_FEC_MXC
 172 static iomux_v3_cfg_t const fec2_pads[] = {
 173         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2            | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
 174         MX6_PAD_GPIO1_IO06__ENET2_MDIO                  | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 175         MX6_PAD_GPIO1_IO07__ENET2_MDC                   | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 176         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00           | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 177         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01           | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 178         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER                | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 179         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN                | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 180         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00           | MUX_PAD_CTRL(ENET_PAD_CTRL),
 181         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01           | MUX_PAD_CTRL(ENET_PAD_CTRL),
 182         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN                | MUX_PAD_CTRL(ENET_PAD_CTRL),
 183 };
 184
 185 static void setup_iomux_fec(void)
 186 {
 187         imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
 188 }
 189 #endif
 190
 191 static void setup_iomux_uart(void)
 192 {
 193         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 194 }
 195
 196 #ifdef CONFIG_FSL_ESDHC
 197
 198 #define USDHC1_CD_GPIO  IMX_GPIO_NR(5, 0)
 199
 200 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 201         {USDHC1_BASE_ADDR, 0, 4},
 202 };
 203
 204 int board_mmc_getcd(struct mmc *mmc)
 205 {
 206         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 207         int ret = 0;
 208
 209         switch (cfg->esdhc_base) {
 210         case USDHC1_BASE_ADDR:
 211                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 212                 break;
 213         }
 214
 215         return ret;
 216 }
 217
 218 int board_mmc_init(bd_t *bis)
 219 {
 220         int i, ret;
 221
 222         /* USDHC1 is mmc0 */
 223         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 224                 switch (i) {
 225                 case 0:
 226                         imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
 227                                                          ARRAY_SIZE(usdhc1_pads));
 228                         gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
 229                         gpio_direction_input(USDHC1_CD_GPIO);
 230                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 231                         break;
 232                 default:
 233                         printf("Warning: you configured more USDHC controllers"
 234                                 "(%d) than supported by the board\n", i + 1);
 235                         return -EINVAL;
 236                 }
 237
 238                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 239                 if (ret)
 240                         return ret;
 241         }
 242
 243         return 0;
 244 }
 245 #endif
 246
 247 #ifdef CONFIG_FEC_MXC
 248
 249 static int setup_fec(void)
 250 {
 251         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 252         int ret;
 253
 254         setup_iomux_fec();
 255
 256         /* provide the PHY clock from the i.MX 6 */
 257         ret = enable_fec_anatop_clock(1, ENET_50MHZ);
 258         if (ret)
 259                 return ret;
 260
 261         /* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */
 262         clrsetbits_le32(&iomuxc_regs->gpr[1],
 263                         IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
 264                         IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 265
 266         /* give new Ethernet PHY power save mode circuitry time to settle */
 267         mdelay(300);
 268
 269         return 0;
 270 }
 271
 272 int board_phy_config(struct phy_device *phydev)
 273 {
 274         if (phydev->drv->config)
 275                 phydev->drv->config(phydev);
 276         return 0;
 277 }
 278 #endif
 279
 280 int board_early_init_f(void)
 281 {
 282         setup_iomux_uart();
 283
 284         return 0;
 285 }
 286
 287 int board_init(void)
 288 {
 289         /* address of boot parameters */
 290         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 291
 292 #ifdef CONFIG_FEC_MXC
 293         setup_fec();
 294 #endif
 295
 296 #ifdef CONFIG_NAND_MXS
 297         setup_gpmi_nand();
 298 #endif
 299
 300 #ifdef CONFIG_VIDEO_MXS
 301         setup_lcd();
 302 #endif
 303
 304 #ifdef CONFIG_USB_EHCI_MX6
 305         imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
 306         gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
 307 #endif
 308
 309         return 0;
 310 }
 311
 312 #ifdef CONFIG_CMD_BMODE
 313 /* TODO */
 314 static const struct boot_mode board_boot_modes[] = {
 315         /* 4 bit bus width */
 316         {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
 317         {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
 318         {NULL, 0},
 319 };
 320 #endif
 321
 322 int board_late_init(void)
 323 {
 324 #ifdef CONFIG_TDX_CFG_BLOCK
 325         /*
 326          * If we have a valid config block and it says we are a module with
 327          * Wi-Fi/Bluetooth make sure we use the -wifi device tree.
 328          */
 329         if (tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT_IT ||
 330             tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT)
 331                 env_set("variant", "-wifi");
 332 #endif
 333
 334 #ifdef CONFIG_CMD_BMODE
 335         add_board_boot_modes(board_boot_modes);
 336 #endif
 337
 338 #ifdef CONFIG_CMD_USB_SDP
 339         if (is_boot_from_usb()) {
 340                 printf("Serial Downloader recovery mode, using sdp command\n");
 341                 env_set("bootdelay", "0");
 342                 env_set("bootcmd", "sdp 0");
 343         }
 344 #endif /* CONFIG_CMD_USB_SDP */
 345
 346         return 0;
 347 }
 348
 349 int checkboard(void)
 350 {
 351         printf("Model: Toradex Colibri iMX6ULL\n");
 352
 353         return 0;
 354 }
 355
 356 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 357 int ft_board_setup(void *blob, bd_t *bd)
 358 {
 359 #if defined(CONFIG_FDT_FIXUP_PARTITIONS)
 360         static struct node_info nodes[] = {
 361                 { "fsl,imx6ull-gpmi-nand", MTD_DEV_TYPE_NAND, },
 362                 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
 363         };
 364
 365         /* Update partition nodes using info from mtdparts env var */
 366         puts("   Updating MTD partitions...\n");
 367         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 368 #endif
 369
 370         return ft_common_board_setup(blob, bd);
 371 }
 372 #endif
 373
 374 #ifdef CONFIG_USB_EHCI_MX6
 375 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 376                 MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 377 };
 378
 379 int board_ehci_hcd_init(int port)
 380 {
 381         switch (port) {
 382         case 0:
 383                 break;
 384         case 1:
 385                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 386                                                  ARRAY_SIZE(usb_otg2_pads));
 387                 break;
 388         default:
 389                 return -EINVAL;
 390         }
 391         return 0;
 392 }
 393
 394 int board_usb_phy_mode(int port)
 395 {
 396         switch (port) {
 397         case 0:
 398                 if (gpio_get_value(USB_CDET_GPIO))
 399                         return USB_INIT_DEVICE;
 400                 else
 401                         return USB_INIT_HOST;
 402         case 1:
 403         default:
 404                 return USB_INIT_HOST;
 405         }
 406 }
 407 #endif
 408
 409 static struct mxc_serial_platdata mxc_serial_plat = {
 410         .reg = (struct mxc_uart *)UART1_BASE,
 411         .use_dte = 1,
 412 };
 413
 414 U_BOOT_DEVICE(mxc_serial) = {
 415         .name = "serial_mxc",
 416         .platdata = &mxc_serial_plat,
 417 };