board/toradex/apalis_t30/apalis_t30-spl.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  (C) Copyright 2010-2013
   4  *  NVIDIA Corporation <www.nvidia.com>
   5  *
   6  *  (C) Copyright 2021
   7  *  Svyatoslav Ryhel <clamor95@gmail.com>
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch-tegra/tegra_i2c.h>
  12 #include <linux/delay.h>
  13
  14 /* I2C addr is in 8 bit */
  15 #define TPS65911_I2C_ADDR               0x5A
  16 #define TPS65911_VDDCTRL_OP_REG         0x28
  17 #define TPS65911_VDDCTRL_SR_REG         0x27
  18 #define TPS65911_VDDCTRL_OP_DATA        (0x2400 | TPS65911_VDDCTRL_OP_REG)
  19 #define TPS65911_VDDCTRL_SR_DATA        (0x0100 | TPS65911_VDDCTRL_SR_REG)
  20
  21 void pmic_enable_cpu_vdd(void)
  22 {
  23         /*
  24          * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
  25          * First set VDD to 1.0125V, then enable the VDD regulator.
  26          */
  27         udelay(1000);
  28         tegra_i2c_ll_write(TPS65911_I2C_ADDR,
  29                            TPS65911_VDDCTRL_OP_DATA);
  30         udelay(1000);
  31         tegra_i2c_ll_write(TPS65911_I2C_ADDR,
  32                            TPS65911_VDDCTRL_SR_DATA);
  33         udelay(10 * 1000);
  34 }