1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
5 * Copyright (C) 2014-2019, Toradex AG
6 * copied from nitrogen6x
15 #include <asm/global_data.h>
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/crm_regs.h>
22 #include <asm/arch/imx-regs.h>
23 #include <asm/arch/mx6-ddr.h>
24 #include <asm/arch/mx6-pins.h>
25 #include <asm/arch/mxc_hdmi.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/bootm.h>
29 #include <asm/mach-imx/boot_mode.h>
30 #include <asm/mach-imx/iomux-v3.h>
31 #include <asm/mach-imx/sata.h>
32 #include <asm/mach-imx/video.h>
33 #include <dm/device-internal.h>
34 #include <dm/platform_data/serial_mxc.h>
35 #include <dwc_ahsata.h>
37 #include <fsl_esdhc_imx.h>
38 #include <imx_thermal.h>
43 #include "../common/tdx-cfg-block.h"
44 #ifdef CONFIG_TDX_CMD_IMX_MFGR
48 DECLARE_GLOBAL_DATA_PTR;
50 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
52 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
54 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
55 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
56 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
58 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
59 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
60 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
62 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
63 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
65 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
66 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
69 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
70 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
71 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
73 #define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
75 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
77 #define APALIS_IMX6_SATA_INIT_RETRIES 10
81 /* use the DDR controllers configured size */
82 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
83 (ulong)imx_ddr_size());
89 iomux_v3_cfg_t const uart1_pads_dce[] = {
90 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
91 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
93 iomux_v3_cfg_t const uart1_pads_dte[] = {
94 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
95 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
98 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
100 iomux_v3_cfg_t const usdhc1_pads[] = {
101 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
111 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
112 # define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
116 iomux_v3_cfg_t const usdhc2_pads[] = {
117 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
124 # define GPIO_SD_CD IMX_GPIO_NR(6, 14)
128 iomux_v3_cfg_t const usdhc3_pads[] = {
129 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
130 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
131 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
132 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
133 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
134 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
135 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
136 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
137 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
138 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
139 MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
141 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
143 int mx6_rgmii_rework(struct phy_device *phydev)
147 switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
149 /* read rxc dll control - devaddr = 0x02, register = 0x4c */
150 tmp = ksz9031_phy_extended_read(phydev, 0x02,
151 MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
152 MII_KSZ9031_MOD_DATA_NO_POST_INC);
153 /* disable rxdll bypass (enable 2ns skew delay on RXC) */
154 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
155 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
156 ksz9031_phy_extended_write(phydev, 0x02,
157 MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
158 MII_KSZ9031_MOD_DATA_NO_POST_INC,
160 /* read txc dll control - devaddr = 0x02, register = 0x4d */
161 tmp = ksz9031_phy_extended_read(phydev, 0x02,
162 MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
163 MII_KSZ9031_MOD_DATA_NO_POST_INC);
164 /* disable rxdll bypass (enable 2ns skew delay on TXC) */
165 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
166 /* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
167 ksz9031_phy_extended_write(phydev, 0x02,
168 MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
169 MII_KSZ9031_MOD_DATA_NO_POST_INC,
172 /* control data pad skew - devaddr = 0x02, register = 0x04 */
173 ksz9031_phy_extended_write(phydev, 0x02,
174 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
175 MII_KSZ9031_MOD_DATA_NO_POST_INC,
177 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
178 ksz9031_phy_extended_write(phydev, 0x02,
179 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
180 MII_KSZ9031_MOD_DATA_NO_POST_INC,
182 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
183 ksz9031_phy_extended_write(phydev, 0x02,
184 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
185 MII_KSZ9031_MOD_DATA_NO_POST_INC,
187 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
188 ksz9031_phy_extended_write(phydev, 0x02,
189 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
190 MII_KSZ9031_MOD_DATA_NO_POST_INC,
195 /* control data pad skew - devaddr = 0x02, register = 0x04 */
196 ksz9031_phy_extended_write(phydev, 0x02,
197 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
198 MII_KSZ9031_MOD_DATA_NO_POST_INC,
200 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
201 ksz9031_phy_extended_write(phydev, 0x02,
202 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
203 MII_KSZ9031_MOD_DATA_NO_POST_INC,
205 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
206 ksz9031_phy_extended_write(phydev, 0x02,
207 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
208 MII_KSZ9031_MOD_DATA_NO_POST_INC,
210 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
211 ksz9031_phy_extended_write(phydev, 0x02,
212 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
213 MII_KSZ9031_MOD_DATA_NO_POST_INC,
221 iomux_v3_cfg_t const enet_pads[] = {
222 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
223 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
224 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
225 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
226 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
227 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
228 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
229 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
230 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
231 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
232 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
233 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
234 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
235 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
236 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
237 /* KSZ9031 PHY Reset */
238 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL) |
240 # define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
243 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
244 iomux_v3_cfg_t const gpio_pads[] = {
245 /* Apalis GPIO1 - GPIO8 */
246 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
248 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
250 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
252 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
254 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
256 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
258 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
260 MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
262 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
266 static void setup_iomux_gpio(void)
268 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
271 iomux_v3_cfg_t const usb_pads[] = {
273 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
274 # define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
276 MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
277 # define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
279 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
281 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
282 # define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
286 * UARTs are used in DTE mode, switch the mode on all UARTs before
287 * any pinmuxing connects a (DCE) output to a transceiver output.
289 #define UCR3 0x88 /* FIFO Control Register */
290 #define UCR3_RI BIT(8) /* RIDELT DTE mode */
291 #define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
292 #define UFCR 0x90 /* FIFO Control Register */
293 #define UFCR_DCEDTE BIT(6) /* DCE=0 */
295 static void setup_dtemode_uart(void)
297 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
298 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
299 setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
300 setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
302 clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
303 clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
304 clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
305 clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
308 static void setup_iomux_dte_uart(void)
310 setup_dtemode_uart();
311 imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
312 ARRAY_SIZE(uart1_pads_dte));
315 #ifdef CONFIG_USB_EHCI_MX6
316 int board_ehci_hcd_init(int port)
318 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
323 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
324 /* use the following sequence: eMMC, MMC1, SD1 */
325 struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
331 int board_mmc_getcd(struct mmc *mmc)
333 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
334 int ret = true; /* default: assume inserted */
336 switch (cfg->esdhc_base) {
337 case USDHC1_BASE_ADDR:
338 gpio_request(GPIO_MMC_CD, "MMC_CD");
339 gpio_direction_input(GPIO_MMC_CD);
340 ret = !gpio_get_value(GPIO_MMC_CD);
342 case USDHC2_BASE_ADDR:
343 gpio_request(GPIO_MMC_CD, "SD_CD");
344 gpio_direction_input(GPIO_SD_CD);
345 ret = !gpio_get_value(GPIO_SD_CD);
352 int board_mmc_init(struct bd_info *bis)
354 struct src *psrc = (struct src *)SRC_BASE_ADDR;
355 unsigned reg = readl(&psrc->sbmr1) >> 11;
357 * Upon reading BOOT_CFG register the following map is done:
358 * Bit 11 and 12 of BOOT_CFG register can determine the current
367 imx_iomux_v3_setup_multiple_pads(
368 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
369 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
370 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
371 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
374 imx_iomux_v3_setup_multiple_pads(
375 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
376 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
377 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
378 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
381 imx_iomux_v3_setup_multiple_pads(
382 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
383 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
384 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
385 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
388 puts("MMC boot device not available");
391 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
393 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
395 int board_phy_config(struct phy_device *phydev)
397 mx6_rgmii_rework(phydev);
398 if (phydev->drv->config)
399 phydev->drv->config(phydev);
404 static iomux_v3_cfg_t const pwr_intb_pads[] = {
406 * the bootrom sets the iomux to vselect, potentially connecting
407 * two outputs. Set this back to GPIO
409 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
412 #if defined(CONFIG_VIDEO_IPUV3)
414 static iomux_v3_cfg_t const backlight_pads[] = {
415 /* Backlight on RGB connector: J15 */
416 MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
418 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
419 /* additional CPU pin on BKL_PWM, keep in tristate */
420 MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
421 /* Backlight PWM, used as GPIO in U-Boot */
422 MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
424 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
425 /* buffer output enable 0: buffer enabled */
426 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
427 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
428 /* PSAVE# integrated VDAC */
429 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
431 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
434 static iomux_v3_cfg_t const rgb_pads[] = {
435 MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
436 MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
437 MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
438 MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
439 MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
440 MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
441 MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
442 MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
443 MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
444 MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
445 MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
446 MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
447 MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
448 MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
449 MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
450 MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
451 MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
452 MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
453 MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
454 MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
455 MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
456 MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
457 MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
458 MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
459 MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
460 MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
461 MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
462 MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
465 static void do_enable_hdmi(struct display_info_t const *dev)
467 imx_enable_hdmi_phy();
470 static void enable_lvds(struct display_info_t const *dev)
472 struct iomuxc *iomux = (struct iomuxc *)
474 u32 reg = readl(&iomux->gpr[2]);
475 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
476 writel(reg, &iomux->gpr[2]);
477 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
478 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
479 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
482 static void enable_rgb(struct display_info_t const *dev)
484 imx_iomux_v3_setup_multiple_pads(
486 ARRAY_SIZE(rgb_pads));
487 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
488 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
489 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
492 static int detect_default(struct display_info_t const *dev)
498 struct display_info_t const displays[] = {{
501 .pixfmt = IPU_PIX_FMT_RGB24,
502 .detect = detect_hdmi,
503 .enable = do_enable_hdmi,
517 .vmode = FB_VMODE_NONINTERLACED
522 .pixfmt = IPU_PIX_FMT_RGB24,
523 .detect = detect_default,
524 .enable = enable_rgb,
538 .vmode = FB_VMODE_NONINTERLACED
543 .pixfmt = IPU_PIX_FMT_RGB24,
544 .enable = enable_rgb,
558 .vmode = FB_VMODE_NONINTERLACED
562 .pixfmt = IPU_PIX_FMT_LVDS666,
563 .enable = enable_lvds,
565 .name = "wsvga-lvds",
577 .vmode = FB_VMODE_NONINTERLACED
579 size_t display_count = ARRAY_SIZE(displays);
581 static void setup_display(void)
583 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
584 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
589 /* Turn on LDB0,IPU,IPU DI0 clocks */
590 reg = __raw_readl(&mxc_ccm->CCGR3);
591 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
592 writel(reg, &mxc_ccm->CCGR3);
594 /* set LDB0, LDB1 clk select to 011/011 */
595 reg = readl(&mxc_ccm->cs2cdr);
596 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
597 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
598 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
599 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
600 writel(reg, &mxc_ccm->cs2cdr);
602 reg = readl(&mxc_ccm->cscmr2);
603 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
604 writel(reg, &mxc_ccm->cscmr2);
606 reg = readl(&mxc_ccm->chsccdr);
607 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
608 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
609 writel(reg, &mxc_ccm->chsccdr);
611 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
612 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
613 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
614 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
615 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
616 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
617 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
618 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
619 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
620 writel(reg, &iomux->gpr[2]);
622 reg = readl(&iomux->gpr[3]);
623 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
624 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
625 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
626 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
627 writel(reg, &iomux->gpr[3]);
629 /* backlight unconditionally on for now */
630 imx_iomux_v3_setup_multiple_pads(backlight_pads,
631 ARRAY_SIZE(backlight_pads));
632 /* use 0 for EDT 7", use 1 for LG fullHD panel */
633 gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
634 gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
635 gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
636 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
637 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
638 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
642 * Backlight off before OS handover
644 void board_preboot_os(void)
646 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
647 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
649 #endif /* defined(CONFIG_VIDEO_IPUV3) */
651 int board_early_init_f(void)
653 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
654 ARRAY_SIZE(pwr_intb_pads));
655 setup_iomux_dte_uart();
661 * Do not overwrite the console
662 * Use always serial for U-Boot console
664 int overwrite_console(void)
671 /* address of boot parameters */
672 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
674 #if defined(CONFIG_VIDEO_IPUV3)
678 #ifdef CONFIG_TDX_CMD_IMX_MFGR
691 #ifdef CONFIG_BOARD_LATE_INIT
692 int board_late_init(void)
694 #if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
698 rev = get_board_revision();
699 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
700 env_set("board_rev", env_str);
701 #endif /* CONFIG_BOARD_LATE_INIT */
703 #ifdef CONFIG_CMD_USB_SDP
704 if (is_boot_from_usb()) {
705 printf("Serial Downloader recovery mode, using sdp command\n");
706 env_set("bootdelay", "0");
707 env_set("bootcmd", "sdp 0");
709 #endif /* CONFIG_CMD_USB_SDP */
713 #endif /* CONFIG_BOARD_LATE_INIT */
720 switch (get_cpu_temp_grade(&minc, &maxc)) {
721 case TEMP_AUTOMOTIVE:
722 case TEMP_INDUSTRIAL:
724 case TEMP_EXTCOMMERCIAL:
728 printf("Model: Toradex Apalis iMX6 %s %s%s\n",
729 is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
730 (gd->ram_size == 0x80000000) ? "2GB" :
731 (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
735 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
736 int ft_board_setup(void *blob, struct bd_info *bd)
738 return ft_common_board_setup(blob, bd);
742 #ifdef CONFIG_CMD_BMODE
743 static const struct boot_mode board_boot_modes[] = {
744 /* 4-bit bus width */
745 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
746 {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
751 int misc_init_r(void)
753 #ifdef CONFIG_CMD_BMODE
754 add_board_boot_modes(board_boot_modes);
759 #ifdef CONFIG_LDO_BYPASS_CHECK
760 /* TODO, use external pmic, for now always ldo_enable */
761 void ldo_mode_set(int ldo_bypass)
767 #ifdef CONFIG_SPL_BUILD
769 #include <linux/libfdt.h>
770 #include "asm/arch/mx6q-ddr.h"
771 #include "asm/arch/iomux.h"
772 #include "asm/arch/crm_regs.h"
774 static void ccgr_init(void)
776 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
778 writel(0x00C03F3F, &ccm->CCGR0);
779 writel(0x0030FC03, &ccm->CCGR1);
780 writel(0x0FFFFFF3, &ccm->CCGR2);
781 writel(0x3FF0300F, &ccm->CCGR3);
782 writel(0x00FFF300, &ccm->CCGR4);
783 writel(0x0F0000F3, &ccm->CCGR5);
784 writel(0x000003FF, &ccm->CCGR6);
787 * Setup CCM_CCOSR register as follows:
789 * clko2_en = 1 --> CKO2 enabled
790 * clko2_div = 000 --> divide by 1
791 * clko2_sel = 01110 --> osc_clk (24MHz)
793 * clk_out_sel = 1 --> Output CKO2 to CKO1
795 * This sets both CLKO2/CLKO1 output to 24MHz,
796 * CLKO1 configuration not relevant because of clk_out_sel
797 * (CLKO1 set to default)
799 writel(0x010E0101, &ccm->ccosr);
803 #define PAD_CTL_INPUT_DDR BIT(17)
805 struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
806 /* Differential input, 40 ohm DSE */
807 .dram_sdclk_0 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
808 .dram_sdclk_1 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
809 .dram_cas = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
810 .dram_ras = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
811 .dram_reset = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
813 /* SDKE[0:1]: BIT(12) and BIT(13) are reserved and set at reset */
814 .dram_sdcke0 = 0x00003000,
815 .dram_sdcke1 = 0x00003000,
817 .dram_sdba2 = 0x00000000,
819 /* ODT[0:1]: 40 ohm DSE, BIT(12) and BIT(13) are reserved and set at reset */
820 .dram_sdodt0 = PAD_CTL_DSE_40ohm | 0x00003000,
821 .dram_sdodt1 = PAD_CTL_DSE_40ohm | 0x00003000,
823 /* SDQS[0:7]: 40 ohm DSE, Pull/Keeper Disabled, ODT Disabled */
824 .dram_sdqs0 = PAD_CTL_DSE_40ohm,
825 .dram_sdqs1 = PAD_CTL_DSE_40ohm,
826 .dram_sdqs2 = PAD_CTL_DSE_40ohm,
827 .dram_sdqs3 = PAD_CTL_DSE_40ohm,
828 .dram_sdqs4 = PAD_CTL_DSE_40ohm,
829 .dram_sdqs5 = PAD_CTL_DSE_40ohm,
830 .dram_sdqs6 = PAD_CTL_DSE_40ohm,
831 .dram_sdqs7 = PAD_CTL_DSE_40ohm,
833 /* DQM[0:7]: Differential input, 40 ohm DSE, Pull/Keeper Disabled, ODT Disabled */
834 .dram_dqm0 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
835 .dram_dqm1 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
836 .dram_dqm2 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
837 .dram_dqm3 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
838 .dram_dqm4 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
839 .dram_dqm5 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
840 .dram_dqm6 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
841 .dram_dqm7 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
844 struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
846 .grp_ddr_type = 0x000C0000,
848 /* SDQS[0:7]: Differential input */
849 .grp_ddrmode_ctl = PAD_CTL_INPUT_DDR,
851 /* DATA[0:63]: Pull/Keeper disabled */
854 /* ADDR[0:16], SDBA[0:1]: 40 ohm DSE */
855 .grp_addds = PAD_CTL_DSE_40ohm,
857 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm DSE */
858 .grp_ctlds = PAD_CTL_DSE_40ohm,
860 /* DATA[0:63]: Differential input */
861 .grp_ddrmode = PAD_CTL_INPUT_DDR,
863 /* DATA[0:63]: 40 ohm DSE */
864 .grp_b0ds = PAD_CTL_DSE_40ohm,
865 .grp_b1ds = PAD_CTL_DSE_40ohm,
866 .grp_b2ds = PAD_CTL_DSE_40ohm,
867 .grp_b3ds = PAD_CTL_DSE_40ohm,
868 .grp_b4ds = PAD_CTL_DSE_40ohm,
869 .grp_b5ds = PAD_CTL_DSE_40ohm,
870 .grp_b6ds = PAD_CTL_DSE_40ohm,
871 .grp_b7ds = PAD_CTL_DSE_40ohm,
874 struct mx6_ddr_sysinfo sysinfo = {
875 .dsize = 2, /* width of data bus: 2=64 */
876 .cs_density = 32, /* full range so that get_mem_size() works, 32Gb per CS */
879 .rtt_wr = 2, /* Dynamic ODT, RZQ/2 */
880 .rtt_nom = 0, /* Disabled */
881 .walat = 0, /* Write additional latency */
882 .ralat = 5, /* Read additional latency */
883 .mif3_mode = 3, /* Command prediction working mode */
884 .bi_on = 1, /* Bank interleaving enabled */
885 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
886 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
887 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
888 .ddr_type = DDR_TYPE_DDR3,
889 .refsel = 1, /* Refresh cycles at 32KHz */
890 .refr = 3, /* 4 refresh commands per refresh cycle */
893 static const struct mx6_mmdc_calibration mx6_mmdc_calib = {
894 .p0_mpwldectrl0 = 0x0009000E,
895 .p0_mpwldectrl1 = 0x0018000B,
896 .p1_mpwldectrl0 = 0x00060015,
897 .p1_mpwldectrl1 = 0x0006000E,
898 .p0_mpdgctrl0 = 0x432A0338,
899 .p0_mpdgctrl1 = 0x03260324,
900 .p1_mpdgctrl0 = 0x43340344,
901 .p1_mpdgctrl1 = 0x031E027C,
902 .p0_mprddlctl = 0x33272D2E,
903 .p1_mprddlctl = 0x2F312B37,
904 .p0_mpwrdlctl = 0x3A35433C,
905 .p1_mpwrdlctl = 0x4336453F,
908 static const struct mx6_ddr3_cfg ddr3_cfg = {
922 struct mx6_ddr_sysinfo sysinfo_it = {
923 .dsize = 2, /* width of data bus: 2=64 */
924 .cs_density = 32, /* full range so that get_mem_size() works, 32Gb per CS */
927 .rtt_wr = 1, /* Dynamic ODT, RZQ/4 */
928 .rtt_nom = 1, /* RZQ/4 */
929 .walat = 0, /* Write additional latency */
930 .ralat = 5, /* Read additional latency */
931 .mif3_mode = 3, /* Command prediction working mode */
932 .bi_on = 1, /* Bank interleaving enabled */
933 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
934 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
935 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
936 .ddr_type = DDR_TYPE_DDR3,
937 .refsel = 1, /* Refresh cycles at 32KHz */
938 .refr = 7, /* 8 refresh commands per refresh cycle */
941 static const struct mx6_mmdc_calibration mx6_mmdc_calib_it = {
942 .p0_mpwldectrl0 = 0x0009000E,
943 .p0_mpwldectrl1 = 0x0018000B,
944 .p1_mpwldectrl0 = 0x00060015,
945 .p1_mpwldectrl1 = 0x0006000E,
946 .p0_mpdgctrl0 = 0x03300338,
947 .p0_mpdgctrl1 = 0x03240324,
948 .p1_mpdgctrl0 = 0x03440350,
949 .p1_mpdgctrl1 = 0x032C0308,
950 .p0_mprddlctl = 0x40363C3E,
951 .p1_mprddlctl = 0x3C3E3C46,
952 .p0_mpwrdlctl = 0x403E463E,
953 .p1_mpwrdlctl = 0x4A384C46,
956 static const struct mx6_ddr3_cfg ddr3_cfg_it = {
971 /* Perform DDR DRAM calibration */
972 static void spl_dram_perform_cal(const struct mx6_ddr_sysinfo *ddr_sysinfo)
974 #ifdef CONFIG_MX6_DDRCAL
977 err = mmdc_do_write_level_calibration(ddr_sysinfo);
979 printf("error %d from write level calibration\n", err);
980 err = mmdc_do_dqs_calibration(ddr_sysinfo);
982 printf("error %d from dqs calibration\n", err);
986 static void spl_dram_init(void)
990 switch (get_cpu_temp_grade(NULL, NULL)) {
991 case TEMP_COMMERCIAL:
992 case TEMP_EXTCOMMERCIAL:
993 puts("Commercial temperature grade DDR3 timings.\n");
994 temp_grade_it = false;
996 case TEMP_INDUSTRIAL:
997 case TEMP_AUTOMOTIVE:
999 puts("Industrial temperature grade DDR3 timings.\n");
1000 temp_grade_it = true;
1004 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
1007 mx6_dram_cfg(&sysinfo_it, &mx6_mmdc_calib_it, &ddr3_cfg_it);
1009 mx6_dram_cfg(&sysinfo, &mx6_mmdc_calib, &ddr3_cfg);
1014 spl_dram_perform_cal(&sysinfo_it);
1016 spl_dram_perform_cal(&sysinfo);
1019 void board_init_f(ulong dummy)
1021 /* setup AIPS and disable watchdog */
1028 board_early_init_f();
1030 /* setup GP timer */
1033 /* UART clocks enabled and gd valid - init serial console */
1034 preloader_console_init();
1036 /* Make sure we use dte mode */
1037 setup_dtemode_uart();
1039 /* DDR initialization */
1042 /* Clear the BSS. */
1043 memset(__bss_start, 0, __bss_end - __bss_start);
1045 /* load/boot image from boot device */
1046 board_init_r(NULL, 0);
1049 #ifdef CONFIG_SPL_LOAD_FIT
1050 int board_fit_config_name_match(const char *name)
1052 if (!strcmp(name, "imx6-apalis"))
1059 void reset_cpu(void)
1063 #endif /* CONFIG_SPL_BUILD */
1065 static struct mxc_serial_plat mxc_serial_plat = {
1066 .reg = (struct mxc_uart *)UART1_BASE,
1070 U_BOOT_DRVINFO(mxc_serial) = {
1071 .name = "serial_mxc",
1072 .plat = &mxc_serial_plat,