board/toradex/apalis_imx6/apalis_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <init.h>
  13
  14 #include <ahci.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/imx-regs.h>
  18 #include <asm/arch/mx6-ddr.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/mxc_hdmi.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/bootm.h>
  23 #include <asm/gpio.h>
  24 #include <asm/mach-imx/boot_mode.h>
  25 #include <asm/mach-imx/iomux-v3.h>
  26 #include <asm/mach-imx/sata.h>
  27 #include <asm/mach-imx/video.h>
  28 #include <dm/device-internal.h>
  29 #include <dm/platform_data/serial_mxc.h>
  30 #include <dwc_ahsata.h>
  31 #include <env.h>
  32 #include <fsl_esdhc_imx.h>
  33 #include <imx_thermal.h>
  34 #include <micrel.h>
  35 #include <miiphy.h>
  36 #include <netdev.h>
  37
  38 #include "../common/tdx-cfg-block.h"
  39 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  40 #include "pf0100.h"
  41 #endif
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  47         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  48
  49 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  50         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  51         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  52
  53 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  54         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  55         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  56
  57 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  58         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  59
  60 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  61         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  62         PAD_CTL_SRE_SLOW)
  63
  64 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  65         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  66         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  67
  68 #define TRISTATE        (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  69
  70 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  71
  72 #define APALIS_IMX6_SATA_INIT_RETRIES   10
  73
  74 int dram_init(void)
  75 {
  76         /* use the DDR controllers configured size */
  77         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  78                                     (ulong)imx_ddr_size());
  79
  80         return 0;
  81 }
  82
  83 /* Apalis UART1 */
  84 iomux_v3_cfg_t const uart1_pads_dce[] = {
  85         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  87 };
  88 iomux_v3_cfg_t const uart1_pads_dte[] = {
  89         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  90         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  91 };
  92
  93 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  94 /* Apalis MMC1 */
  95 iomux_v3_cfg_t const usdhc1_pads[] = {
  96         MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 107 #       define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
 108 };
 109
 110 /* Apalis SD1 */
 111 iomux_v3_cfg_t const usdhc2_pads[] = {
 112         MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113         MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 119 #       define GPIO_SD_CD IMX_GPIO_NR(6, 14)
 120 };
 121
 122 /* eMMC */
 123 iomux_v3_cfg_t const usdhc3_pads[] = {
 124         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 125         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 128         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 132         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 133         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 134         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 135 };
 136 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 137
 138 int mx6_rgmii_rework(struct phy_device *phydev)
 139 {
 140         int tmp;
 141
 142         switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
 143         case PHY_ID_KSZ9131:
 144                 /* read rxc dll control - devaddr = 0x02, register = 0x4c */
 145                 tmp = ksz9031_phy_extended_read(phydev, 0x02,
 146                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
 147                                            MII_KSZ9031_MOD_DATA_NO_POST_INC);
 148                 /* disable rxdll bypass (enable 2ns skew delay on RXC) */
 149                 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
 150                 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
 151                 ksz9031_phy_extended_write(phydev, 0x02,
 152                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
 153                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 154                                            tmp);
 155                 /* read txc dll control - devaddr = 0x02, register = 0x4d */
 156                 tmp = ksz9031_phy_extended_read(phydev, 0x02,
 157                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
 158                                            MII_KSZ9031_MOD_DATA_NO_POST_INC);
 159                 /* disable rxdll bypass (enable 2ns skew delay on TXC) */
 160                 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
 161                 /* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
 162                 ksz9031_phy_extended_write(phydev, 0x02,
 163                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
 164                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 165                                            tmp);
 166
 167                 /* control data pad skew - devaddr = 0x02, register = 0x04 */
 168                 ksz9031_phy_extended_write(phydev, 0x02,
 169                                            MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 170                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 171                                            0x007d);
 172                 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 173                 ksz9031_phy_extended_write(phydev, 0x02,
 174                                            MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 175                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 176                                            0x7777);
 177                 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 178                 ksz9031_phy_extended_write(phydev, 0x02,
 179                                            MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 180                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 181                                            0xdddd);
 182                 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
 183                 ksz9031_phy_extended_write(phydev, 0x02,
 184                                            MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 185                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 186                                            0x0007);
 187                 break;
 188         case PHY_ID_KSZ9031:
 189         default:
 190                 /* control data pad skew - devaddr = 0x02, register = 0x04 */
 191                 ksz9031_phy_extended_write(phydev, 0x02,
 192                                            MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 193                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 194                                            0x0000);
 195                 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 196                 ksz9031_phy_extended_write(phydev, 0x02,
 197                                            MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 198                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 199                                            0x0000);
 200                 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 201                 ksz9031_phy_extended_write(phydev, 0x02,
 202                                            MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 203                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 204                                            0x0000);
 205                 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
 206                 ksz9031_phy_extended_write(phydev, 0x02,
 207                                            MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 208                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 209                                            0x03FF);
 210                 break;
 211         }
 212
 213         return 0;
 214 }
 215
 216 iomux_v3_cfg_t const enet_pads[] = {
 217         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 218         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 219         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 220         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 221         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 222         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 223         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 224         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 225         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 226         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 227         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 228         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 229         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 230         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 231         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 232         /* KSZ9031 PHY Reset */
 233         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL) |
 234                                                   MUX_MODE_SION,
 235 #       define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 236 };
 237
 238 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 239 iomux_v3_cfg_t const gpio_pads[] = {
 240         /* Apalis GPIO1 - GPIO8 */
 241         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 242                                           MUX_MODE_SION,
 243         MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(WEAK_PULLUP) |
 244                                           MUX_MODE_SION,
 245         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 246                                           MUX_MODE_SION,
 247         MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(WEAK_PULLUP) |
 248                                           MUX_MODE_SION,
 249         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 250                                           MUX_MODE_SION,
 251         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 252                                           MUX_MODE_SION,
 253         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 254                                           MUX_MODE_SION,
 255         MX6_PAD_GPIO_6__GPIO1_IO06      | MUX_PAD_CTRL(WEAK_PULLUP) |
 256                                           MUX_MODE_SION,
 257         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 258                                           MUX_MODE_SION,
 259 };
 260
 261 static void setup_iomux_gpio(void)
 262 {
 263         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 264 }
 265
 266 iomux_v3_cfg_t const usb_pads[] = {
 267         /* USBH_EN */
 268         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 269 #       define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 270         /* USB_VBUS_DET */
 271         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 272 #       define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
 273         /* USBO1_ID */
 274         MX6_PAD_ENET_RX_ER__USB_OTG_ID  | MUX_PAD_CTRL(WEAK_PULLUP),
 275         /* USBO1_EN */
 276         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 277 #       define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 278 };
 279
 280 /*
 281  * UARTs are used in DTE mode, switch the mode on all UARTs before
 282  * any pinmuxing connects a (DCE) output to a transceiver output.
 283  */
 284 #define UCR3            0x88    /* FIFO Control Register */
 285 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 286 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 287 #define UFCR            0x90    /* FIFO Control Register */
 288 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 289
 290 static void setup_dtemode_uart(void)
 291 {
 292         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 293         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 294         setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 295         setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 296
 297         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 298         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 299         clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
 300         clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
 301 }
 302 static void setup_dcemode_uart(void)
 303 {
 304         clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 305         clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 306         clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 307         clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 308 }
 309
 310 static void setup_iomux_dte_uart(void)
 311 {
 312         setup_dtemode_uart();
 313         imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 314                                          ARRAY_SIZE(uart1_pads_dte));
 315 }
 316 static void setup_iomux_dce_uart(void)
 317 {
 318         setup_dcemode_uart();
 319         imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
 320                                          ARRAY_SIZE(uart1_pads_dce));
 321 }
 322
 323 #ifdef CONFIG_USB_EHCI_MX6
 324 int board_ehci_hcd_init(int port)
 325 {
 326         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 327         return 0;
 328 }
 329 #endif
 330
 331 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
 332 /* use the following sequence: eMMC, MMC1, SD1 */
 333 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 334         {USDHC3_BASE_ADDR},
 335         {USDHC1_BASE_ADDR},
 336         {USDHC2_BASE_ADDR},
 337 };
 338
 339 int board_mmc_getcd(struct mmc *mmc)
 340 {
 341         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 342         int ret = true; /* default: assume inserted */
 343
 344         switch (cfg->esdhc_base) {
 345         case USDHC1_BASE_ADDR:
 346                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 347                 gpio_direction_input(GPIO_MMC_CD);
 348                 ret = !gpio_get_value(GPIO_MMC_CD);
 349                 break;
 350         case USDHC2_BASE_ADDR:
 351                 gpio_request(GPIO_MMC_CD, "SD_CD");
 352                 gpio_direction_input(GPIO_SD_CD);
 353                 ret = !gpio_get_value(GPIO_SD_CD);
 354                 break;
 355         }
 356
 357         return ret;
 358 }
 359
 360 int board_mmc_init(bd_t *bis)
 361 {
 362         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 363         unsigned reg = readl(&psrc->sbmr1) >> 11;
 364         /*
 365          * Upon reading BOOT_CFG register the following map is done:
 366          * Bit 11 and 12 of BOOT_CFG register can determine the current
 367          * mmc port
 368          * 0x1                  SD1
 369          * 0x2                  SD2
 370          * 0x3                  SD4
 371          */
 372
 373         switch (reg & 0x3) {
 374         case 0x0:
 375                 imx_iomux_v3_setup_multiple_pads(
 376                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 377                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 378                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 379                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 380                 break;
 381         case 0x1:
 382                 imx_iomux_v3_setup_multiple_pads(
 383                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 384                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 385                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 386                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 387                 break;
 388         case 0x2:
 389                 imx_iomux_v3_setup_multiple_pads(
 390                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 391                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 392                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 393                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 394                 break;
 395         default:
 396                 puts("MMC boot device not available");
 397         }
 398
 399         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 400 }
 401 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 402
 403 int board_phy_config(struct phy_device *phydev)
 404 {
 405         mx6_rgmii_rework(phydev);
 406         if (phydev->drv->config)
 407                 phydev->drv->config(phydev);
 408
 409         return 0;
 410 }
 411
 412 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 413         /*
 414          * the bootrom sets the iomux to vselect, potentially connecting
 415          * two outputs. Set this back to GPIO
 416          */
 417         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 418 };
 419
 420 #if defined(CONFIG_VIDEO_IPUV3)
 421
 422 static iomux_v3_cfg_t const backlight_pads[] = {
 423         /* Backlight on RGB connector: J15 */
 424         MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 425                                        MUX_MODE_SION,
 426 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 427         /* additional CPU pin on BKL_PWM, keep in tristate */
 428         MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 429         /* Backlight PWM, used as GPIO in U-Boot */
 430         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 431                                        MUX_MODE_SION,
 432 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 433         /* buffer output enable 0: buffer enabled */
 434         MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 435 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 436         /* PSAVE# integrated VDAC */
 437         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 438                                        MUX_MODE_SION,
 439 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 440 };
 441
 442 static iomux_v3_cfg_t const rgb_pads[] = {
 443         MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 444         MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 445         MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 446         MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 447         MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 448         MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 449         MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 450         MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 451         MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 452         MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 453         MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 454         MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 455         MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 456         MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 457         MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 458         MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 459         MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 460         MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 461         MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 462         MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 463         MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 464         MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 465         MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
 466         MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
 467         MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
 468         MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
 469         MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
 470         MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
 471 };
 472
 473 static void do_enable_hdmi(struct display_info_t const *dev)
 474 {
 475         imx_enable_hdmi_phy();
 476 }
 477
 478 static void enable_lvds(struct display_info_t const *dev)
 479 {
 480         struct iomuxc *iomux = (struct iomuxc *)
 481                                 IOMUXC_BASE_ADDR;
 482         u32 reg = readl(&iomux->gpr[2]);
 483         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 484         writel(reg, &iomux->gpr[2]);
 485         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 486         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 487         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 488 }
 489
 490 static void enable_rgb(struct display_info_t const *dev)
 491 {
 492         imx_iomux_v3_setup_multiple_pads(
 493                 rgb_pads,
 494                 ARRAY_SIZE(rgb_pads));
 495         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 496         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 497         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 498 }
 499
 500 static int detect_default(struct display_info_t const *dev)
 501 {
 502         (void) dev;
 503         return 1;
 504 }
 505
 506 struct display_info_t const displays[] = {{
 507         .bus    = -1,
 508         .addr   = 0,
 509         .pixfmt = IPU_PIX_FMT_RGB24,
 510         .detect = detect_hdmi,
 511         .enable = do_enable_hdmi,
 512         .mode   = {
 513                 .name           = "HDMI",
 514                 .refresh        = 60,
 515                 .xres           = 1024,
 516                 .yres           = 768,
 517                 .pixclock       = 15385,
 518                 .left_margin    = 220,
 519                 .right_margin   = 40,
 520                 .upper_margin   = 21,
 521                 .lower_margin   = 7,
 522                 .hsync_len      = 60,
 523                 .vsync_len      = 10,
 524                 .sync           = FB_SYNC_EXT,
 525                 .vmode          = FB_VMODE_NONINTERLACED
 526 } }, {
 527         .bus    = -1,
 528         .addr   = 0,
 529         .di     = 1,
 530         .pixfmt = IPU_PIX_FMT_RGB24,
 531         .detect = detect_default,
 532         .enable = enable_rgb,
 533         .mode   = {
 534                 .name           = "vga-rgb",
 535                 .refresh        = 60,
 536                 .xres           = 640,
 537                 .yres           = 480,
 538                 .pixclock       = 33000,
 539                 .left_margin    = 48,
 540                 .right_margin   = 16,
 541                 .upper_margin   = 31,
 542                 .lower_margin   = 11,
 543                 .hsync_len      = 96,
 544                 .vsync_len      = 2,
 545                 .sync           = 0,
 546                 .vmode          = FB_VMODE_NONINTERLACED
 547 } }, {
 548         .bus    = -1,
 549         .addr   = 0,
 550         .di     = 1,
 551         .pixfmt = IPU_PIX_FMT_RGB24,
 552         .enable = enable_rgb,
 553         .mode   = {
 554                 .name           = "wvga-rgb",
 555                 .refresh        = 60,
 556                 .xres           = 800,
 557                 .yres           = 480,
 558                 .pixclock       = 25000,
 559                 .left_margin    = 40,
 560                 .right_margin   = 88,
 561                 .upper_margin   = 33,
 562                 .lower_margin   = 10,
 563                 .hsync_len      = 128,
 564                 .vsync_len      = 2,
 565                 .sync           = 0,
 566                 .vmode          = FB_VMODE_NONINTERLACED
 567 } }, {
 568         .bus    = -1,
 569         .addr   = 0,
 570         .pixfmt = IPU_PIX_FMT_LVDS666,
 571         .enable = enable_lvds,
 572         .mode   = {
 573                 .name           = "wsvga-lvds",
 574                 .refresh        = 60,
 575                 .xres           = 1024,
 576                 .yres           = 600,
 577                 .pixclock       = 15385,
 578                 .left_margin    = 220,
 579                 .right_margin   = 40,
 580                 .upper_margin   = 21,
 581                 .lower_margin   = 7,
 582                 .hsync_len      = 60,
 583                 .vsync_len      = 10,
 584                 .sync           = FB_SYNC_EXT,
 585                 .vmode          = FB_VMODE_NONINTERLACED
 586 } } };
 587 size_t display_count = ARRAY_SIZE(displays);
 588
 589 static void setup_display(void)
 590 {
 591         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 592         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 593         int reg;
 594
 595         enable_ipu_clock();
 596         imx_setup_hdmi();
 597         /* Turn on LDB0,IPU,IPU DI0 clocks */
 598         reg = __raw_readl(&mxc_ccm->CCGR3);
 599         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 600         writel(reg, &mxc_ccm->CCGR3);
 601
 602         /* set LDB0, LDB1 clk select to 011/011 */
 603         reg = readl(&mxc_ccm->cs2cdr);
 604         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 605                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 606         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 607               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 608         writel(reg, &mxc_ccm->cs2cdr);
 609
 610         reg = readl(&mxc_ccm->cscmr2);
 611         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 612         writel(reg, &mxc_ccm->cscmr2);
 613
 614         reg = readl(&mxc_ccm->chsccdr);
 615         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 616                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 617         writel(reg, &mxc_ccm->chsccdr);
 618
 619         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 620              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 621              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 622              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 623              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 624              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 625              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 626              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 627              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 628         writel(reg, &iomux->gpr[2]);
 629
 630         reg = readl(&iomux->gpr[3]);
 631         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 632                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 633             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 634                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 635         writel(reg, &iomux->gpr[3]);
 636
 637         /* backlight unconditionally on for now */
 638         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 639                                          ARRAY_SIZE(backlight_pads));
 640         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 641         gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
 642         gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
 643         gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
 644         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 645         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 646         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 647 }
 648
 649 /*
 650  * Backlight off before OS handover
 651  */
 652 void board_preboot_os(void)
 653 {
 654         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 655         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 656 }
 657 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 658
 659 int board_early_init_f(void)
 660 {
 661         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 662                                          ARRAY_SIZE(pwr_intb_pads));
 663 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 664         setup_iomux_dte_uart();
 665 #else
 666         setup_iomux_dce_uart();
 667 #endif
 668         return 0;
 669 }
 670
 671 /*
 672  * Do not overwrite the console
 673  * Use always serial for U-Boot console
 674  */
 675 int overwrite_console(void)
 676 {
 677         return 1;
 678 }
 679
 680 int board_init(void)
 681 {
 682         /* address of boot parameters */
 683         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 684
 685 #if defined(CONFIG_VIDEO_IPUV3)
 686         setup_display();
 687 #endif
 688
 689 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 690         (void) pmic_init();
 691 #endif
 692
 693 #ifdef CONFIG_SATA
 694         setup_sata();
 695 #endif
 696
 697         setup_iomux_gpio();
 698
 699         return 0;
 700 }
 701
 702 #ifdef CONFIG_BOARD_LATE_INIT
 703 int board_late_init(void)
 704 {
 705 #if defined(CONFIG_REVISION_TAG) && \
 706     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 707         char env_str[256];
 708         u32 rev;
 709
 710         rev = get_board_rev();
 711         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 712         env_set("board_rev", env_str);
 713
 714 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 715         if ((rev & 0xfff0) == 0x0100) {
 716                 char *fdt_env;
 717
 718                 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
 719                 setup_iomux_dce_uart();
 720
 721                 /* if using the default device tree, use version for V1.0 HW */
 722                 fdt_env = env_get("fdt_file");
 723                 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
 724                         env_set("fdt_file", FDT_FILE_V1_0);
 725                         printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
 726 #ifndef CONFIG_ENV_IS_NOWHERE
 727                         env_save();
 728 #endif
 729                 }
 730         }
 731 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 732 #endif /* CONFIG_REVISION_TAG */
 733
 734 #ifdef CONFIG_CMD_USB_SDP
 735         if (is_boot_from_usb()) {
 736                 printf("Serial Downloader recovery mode, using sdp command\n");
 737                 env_set("bootdelay", "0");
 738                 env_set("bootcmd", "sdp 0");
 739         }
 740 #endif /* CONFIG_CMD_USB_SDP */
 741
 742         return 0;
 743 }
 744 #endif /* CONFIG_BOARD_LATE_INIT */
 745
 746 int checkboard(void)
 747 {
 748         char it[] = " IT";
 749         int minc, maxc;
 750
 751         switch (get_cpu_temp_grade(&minc, &maxc)) {
 752         case TEMP_AUTOMOTIVE:
 753         case TEMP_INDUSTRIAL:
 754                 break;
 755         case TEMP_EXTCOMMERCIAL:
 756         default:
 757                 it[0] = 0;
 758         };
 759         printf("Model: Toradex Apalis iMX6 %s %s%s\n",
 760                is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
 761                (gd->ram_size == 0x80000000) ? "2GB" :
 762                (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
 763         return 0;
 764 }
 765
 766 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 767 int ft_board_setup(void *blob, bd_t *bd)
 768 {
 769         return ft_common_board_setup(blob, bd);
 770 }
 771 #endif
 772
 773 #ifdef CONFIG_CMD_BMODE
 774 static const struct boot_mode board_boot_modes[] = {
 775         /* 4-bit bus width */
 776         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 777         {"sd",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 778         {NULL,  0},
 779 };
 780 #endif
 781
 782 int misc_init_r(void)
 783 {
 784 #ifdef CONFIG_CMD_BMODE
 785         add_board_boot_modes(board_boot_modes);
 786 #endif
 787         return 0;
 788 }
 789
 790 #ifdef CONFIG_LDO_BYPASS_CHECK
 791 /* TODO, use external pmic, for now always ldo_enable */
 792 void ldo_mode_set(int ldo_bypass)
 793 {
 794         return;
 795 }
 796 #endif
 797
 798 #ifdef CONFIG_SPL_BUILD
 799 #include <spl.h>
 800 #include <linux/libfdt.h>
 801 #include "asm/arch/mx6q-ddr.h"
 802 #include "asm/arch/iomux.h"
 803 #include "asm/arch/crm_regs.h"
 804
 805 static int mx6_com_dcd_table[] = {
 806 /* ddr-setup.cfg */
 807 MX6_IOM_DRAM_SDQS0, 0x00000030,
 808 MX6_IOM_DRAM_SDQS1, 0x00000030,
 809 MX6_IOM_DRAM_SDQS2, 0x00000030,
 810 MX6_IOM_DRAM_SDQS3, 0x00000030,
 811 MX6_IOM_DRAM_SDQS4, 0x00000030,
 812 MX6_IOM_DRAM_SDQS5, 0x00000030,
 813 MX6_IOM_DRAM_SDQS6, 0x00000030,
 814 MX6_IOM_DRAM_SDQS7, 0x00000030,
 815
 816 MX6_IOM_GRP_B0DS, 0x00000030,
 817 MX6_IOM_GRP_B1DS, 0x00000030,
 818 MX6_IOM_GRP_B2DS, 0x00000030,
 819 MX6_IOM_GRP_B3DS, 0x00000030,
 820 MX6_IOM_GRP_B4DS, 0x00000030,
 821 MX6_IOM_GRP_B5DS, 0x00000030,
 822 MX6_IOM_GRP_B6DS, 0x00000030,
 823 MX6_IOM_GRP_B7DS, 0x00000030,
 824 MX6_IOM_GRP_ADDDS, 0x00000030,
 825 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 826 MX6_IOM_GRP_CTLDS, 0x00000030,
 827
 828 MX6_IOM_DRAM_DQM0, 0x00020030,
 829 MX6_IOM_DRAM_DQM1, 0x00020030,
 830 MX6_IOM_DRAM_DQM2, 0x00020030,
 831 MX6_IOM_DRAM_DQM3, 0x00020030,
 832 MX6_IOM_DRAM_DQM4, 0x00020030,
 833 MX6_IOM_DRAM_DQM5, 0x00020030,
 834 MX6_IOM_DRAM_DQM6, 0x00020030,
 835 MX6_IOM_DRAM_DQM7, 0x00020030,
 836
 837 MX6_IOM_DRAM_CAS, 0x00020030,
 838 MX6_IOM_DRAM_RAS, 0x00020030,
 839 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 840 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 841
 842 MX6_IOM_DRAM_RESET, 0x00020030,
 843 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 844 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 845
 846 MX6_IOM_DRAM_SDODT0, 0x00003030,
 847 MX6_IOM_DRAM_SDODT1, 0x00003030,
 848
 849 /* (differential input) */
 850 MX6_IOM_DDRMODE_CTL, 0x00020000,
 851 /* (differential input) */
 852 MX6_IOM_GRP_DDRMODE, 0x00020000,
 853 /* disable ddr pullups */
 854 MX6_IOM_GRP_DDRPKE, 0x00000000,
 855 MX6_IOM_DRAM_SDBA2, 0x00000000,
 856 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 857 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 858
 859 /* Read data DQ Byte0-3 delay */
 860 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 861 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 862 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 863 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 864 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 865 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 866 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 867 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 868
 869 /*
 870  * MDMISC       mirroring       interleaved (row/bank/col)
 871  */
 872 MX6_MMDC_P0_MDMISC, 0x00081740,
 873
 874 /*
 875  * MDSCR        con_req
 876  */
 877 MX6_MMDC_P0_MDSCR, 0x00008000,
 878
 879 /* 1066mhz_4x128mx16.cfg */
 880
 881 MX6_MMDC_P0_MDPDC, 0x00020036,
 882 MX6_MMDC_P0_MDCFG0, 0x555A7954,
 883 MX6_MMDC_P0_MDCFG1, 0xDB328F64,
 884 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 885 MX6_MMDC_P0_MDRWD, 0x000026D2,
 886 MX6_MMDC_P0_MDOR, 0x005A1023,
 887 MX6_MMDC_P0_MDOTC, 0x09555050,
 888 MX6_MMDC_P0_MDPDC, 0x00025576,
 889 MX6_MMDC_P0_MDASP, 0x00000027,
 890 MX6_MMDC_P0_MDCTL, 0x831A0000,
 891 MX6_MMDC_P0_MDSCR, 0x04088032,
 892 MX6_MMDC_P0_MDSCR, 0x00008033,
 893 MX6_MMDC_P0_MDSCR, 0x00428031,
 894 MX6_MMDC_P0_MDSCR, 0x19308030,
 895 MX6_MMDC_P0_MDSCR, 0x04008040,
 896 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 897 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 898 MX6_MMDC_P0_MDREF, 0x00005800,
 899 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 900 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 901
 902 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
 903 MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
 904 MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
 905 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
 906
 907 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
 908 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
 909
 910 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
 911 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
 912
 913 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
 914 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
 915 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
 916 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
 917
 918 MX6_MMDC_P0_MPMUR0, 0x00000800,
 919 MX6_MMDC_P1_MPMUR0, 0x00000800,
 920 MX6_MMDC_P0_MDSCR, 0x00000000,
 921 MX6_MMDC_P0_MAPSR, 0x00011006,
 922 };
 923
 924 static int mx6_it_dcd_table[] = {
 925 /* ddr-setup.cfg */
 926 MX6_IOM_DRAM_SDQS0, 0x00000030,
 927 MX6_IOM_DRAM_SDQS1, 0x00000030,
 928 MX6_IOM_DRAM_SDQS2, 0x00000030,
 929 MX6_IOM_DRAM_SDQS3, 0x00000030,
 930 MX6_IOM_DRAM_SDQS4, 0x00000030,
 931 MX6_IOM_DRAM_SDQS5, 0x00000030,
 932 MX6_IOM_DRAM_SDQS6, 0x00000030,
 933 MX6_IOM_DRAM_SDQS7, 0x00000030,
 934
 935 MX6_IOM_GRP_B0DS, 0x00000030,
 936 MX6_IOM_GRP_B1DS, 0x00000030,
 937 MX6_IOM_GRP_B2DS, 0x00000030,
 938 MX6_IOM_GRP_B3DS, 0x00000030,
 939 MX6_IOM_GRP_B4DS, 0x00000030,
 940 MX6_IOM_GRP_B5DS, 0x00000030,
 941 MX6_IOM_GRP_B6DS, 0x00000030,
 942 MX6_IOM_GRP_B7DS, 0x00000030,
 943 MX6_IOM_GRP_ADDDS, 0x00000030,
 944 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 945 MX6_IOM_GRP_CTLDS, 0x00000030,
 946
 947 MX6_IOM_DRAM_DQM0, 0x00020030,
 948 MX6_IOM_DRAM_DQM1, 0x00020030,
 949 MX6_IOM_DRAM_DQM2, 0x00020030,
 950 MX6_IOM_DRAM_DQM3, 0x00020030,
 951 MX6_IOM_DRAM_DQM4, 0x00020030,
 952 MX6_IOM_DRAM_DQM5, 0x00020030,
 953 MX6_IOM_DRAM_DQM6, 0x00020030,
 954 MX6_IOM_DRAM_DQM7, 0x00020030,
 955
 956 MX6_IOM_DRAM_CAS, 0x00020030,
 957 MX6_IOM_DRAM_RAS, 0x00020030,
 958 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 959 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 960
 961 MX6_IOM_DRAM_RESET, 0x00020030,
 962 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 963 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 964
 965 MX6_IOM_DRAM_SDODT0, 0x00003030,
 966 MX6_IOM_DRAM_SDODT1, 0x00003030,
 967
 968 /* (differential input) */
 969 MX6_IOM_DDRMODE_CTL, 0x00020000,
 970 /* (differential input) */
 971 MX6_IOM_GRP_DDRMODE, 0x00020000,
 972 /* disable ddr pullups */
 973 MX6_IOM_GRP_DDRPKE, 0x00000000,
 974 MX6_IOM_DRAM_SDBA2, 0x00000000,
 975 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 976 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 977
 978 /* Read data DQ Byte0-3 delay */
 979 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 980 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 981 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 982 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 983 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 984 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 985 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 986 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 987
 988 /*
 989  * MDMISC       mirroring       interleaved (row/bank/col)
 990  */
 991 MX6_MMDC_P0_MDMISC, 0x00081740,
 992
 993 /*
 994  * MDSCR        con_req
 995  */
 996 MX6_MMDC_P0_MDSCR, 0x00008000,
 997
 998 /* 1066mhz_4x256mx16.cfg */
 999
1000 MX6_MMDC_P0_MDPDC, 0x00020036,
1001 MX6_MMDC_P0_MDCFG0, 0x898E78f5,
1002 MX6_MMDC_P0_MDCFG1, 0xff328f64,
1003 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
1004 MX6_MMDC_P0_MDRWD, 0x000026D2,
1005 MX6_MMDC_P0_MDOR, 0x008E1023,
1006 MX6_MMDC_P0_MDOTC, 0x09444040,
1007 MX6_MMDC_P0_MDPDC, 0x00025576,
1008 MX6_MMDC_P0_MDASP, 0x00000047,
1009 MX6_MMDC_P0_MDCTL, 0x841A0000,
1010 MX6_MMDC_P0_MDSCR, 0x02888032,
1011 MX6_MMDC_P0_MDSCR, 0x00008033,
1012 MX6_MMDC_P0_MDSCR, 0x00048031,
1013 MX6_MMDC_P0_MDSCR, 0x19408030,
1014 MX6_MMDC_P0_MDSCR, 0x04008040,
1015 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1016 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1017 MX6_MMDC_P0_MDREF, 0x00007800,
1018 MX6_MMDC_P0_MPODTCTRL, 0x00022227,
1019 MX6_MMDC_P1_MPODTCTRL, 0x00022227,
1020
1021 MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
1022 MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
1023 MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
1024 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
1025
1026 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
1027 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
1028
1029 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
1030 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
1031
1032 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1033 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1034 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1035 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1036
1037 MX6_MMDC_P0_MPMUR0, 0x00000800,
1038 MX6_MMDC_P1_MPMUR0, 0x00000800,
1039 MX6_MMDC_P0_MDSCR, 0x00000000,
1040 MX6_MMDC_P0_MAPSR, 0x00011006,
1041 };
1042
1043 static void ccgr_init(void)
1044 {
1045         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1046
1047         writel(0x00C03F3F, &ccm->CCGR0);
1048         writel(0x0030FC03, &ccm->CCGR1);
1049         writel(0x0FFFFFF3, &ccm->CCGR2);
1050         writel(0x3FF0300F, &ccm->CCGR3);
1051         writel(0x00FFF300, &ccm->CCGR4);
1052         writel(0x0F0000F3, &ccm->CCGR5);
1053         writel(0x000003FF, &ccm->CCGR6);
1054
1055 /*
1056  * Setup CCM_CCOSR register as follows:
1057  *
1058  * cko1_en  = 1    --> CKO1 enabled
1059  * cko1_div = 111  --> divide by 8
1060  * cko1_sel = 1011 --> ahb_clk_root
1061  *
1062  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1063  */
1064         writel(0x000000FB, &ccm->ccosr);
1065 }
1066
1067 static void ddr_init(int *table, int size)
1068 {
1069         int i;
1070
1071         for (i = 0; i < size / 2 ; i++)
1072                 writel(table[2 * i + 1], table[2 * i]);
1073 }
1074
1075 static void spl_dram_init(void)
1076 {
1077         int minc, maxc;
1078
1079         switch (get_cpu_temp_grade(&minc, &maxc)) {
1080         case TEMP_COMMERCIAL:
1081         case TEMP_EXTCOMMERCIAL:
1082                 puts("Commercial temperature grade DDR3 timings.\n");
1083                 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1084                 break;
1085         case TEMP_INDUSTRIAL:
1086         case TEMP_AUTOMOTIVE:
1087         default:
1088                 puts("Industrial temperature grade DDR3 timings.\n");
1089                 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1090                 break;
1091         };
1092         udelay(100);
1093 }
1094
1095 void board_init_f(ulong dummy)
1096 {
1097         /* setup AIPS and disable watchdog */
1098         arch_cpu_init();
1099
1100         ccgr_init();
1101         gpr_init();
1102
1103         /* iomux */
1104         board_early_init_f();
1105
1106         /* setup GP timer */
1107         timer_init();
1108
1109         /* UART clocks enabled and gd valid - init serial console */
1110         preloader_console_init();
1111
1112 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1113         /* Make sure we use dte mode */
1114         setup_dtemode_uart();
1115 #endif
1116
1117         /* DDR initialization */
1118         spl_dram_init();
1119
1120         /* Clear the BSS. */
1121         memset(__bss_start, 0, __bss_end - __bss_start);
1122
1123         /* load/boot image from boot device */
1124         board_init_r(NULL, 0);
1125 }
1126
1127 #ifdef CONFIG_SPL_LOAD_FIT
1128 int board_fit_config_name_match(const char *name)
1129 {
1130         if (!strcmp(name, "imx6-apalis"))
1131                 return 0;
1132
1133         return -1;
1134 }
1135 #endif
1136
1137 void reset_cpu(ulong addr)
1138 {
1139 }
1140
1141 #endif /* CONFIG_SPL_BUILD */
1142
1143 static struct mxc_serial_platdata mxc_serial_plat = {
1144         .reg = (struct mxc_uart *)UART1_BASE,
1145         .use_dte = true,
1146 };
1147
1148 U_BOOT_DEVICE(mxc_serial) = {
1149         .name = "serial_mxc",
1150         .platdata = &mxc_serial_plat,
1151 };