board/toradex/apalis_imx6/apalis_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <image.h>
  13 #include <init.h>
  14 #include <net.h>
  15 #include <linux/bitops.h>
  16 #include <linux/delay.h>
  17
  18 #include <ahci.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/crm_regs.h>
  21 #include <asm/arch/imx-regs.h>
  22 #include <asm/arch/mx6-ddr.h>
  23 #include <asm/arch/mx6-pins.h>
  24 #include <asm/arch/mxc_hdmi.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/bootm.h>
  27 #include <asm/gpio.h>
  28 #include <asm/mach-imx/boot_mode.h>
  29 #include <asm/mach-imx/iomux-v3.h>
  30 #include <asm/mach-imx/sata.h>
  31 #include <asm/mach-imx/video.h>
  32 #include <dm/device-internal.h>
  33 #include <dm/platform_data/serial_mxc.h>
  34 #include <dwc_ahsata.h>
  35 #include <env.h>
  36 #include <fsl_esdhc_imx.h>
  37 #include <imx_thermal.h>
  38 #include <micrel.h>
  39 #include <miiphy.h>
  40 #include <netdev.h>
  41
  42 #include "../common/tdx-cfg-block.h"
  43 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  44 #include "pf0100.h"
  45 #endif
  46
  47 DECLARE_GLOBAL_DATA_PTR;
  48
  49 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  51         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  52
  53 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  54         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  55         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  56
  57 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  58         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  59         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  60
  61 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  62         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  63
  64 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  65         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  66         PAD_CTL_SRE_SLOW)
  67
  68 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  69         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  70         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  71
  72 #define TRISTATE        (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  73
  74 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  75
  76 #define APALIS_IMX6_SATA_INIT_RETRIES   10
  77
  78 int dram_init(void)
  79 {
  80         /* use the DDR controllers configured size */
  81         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  82                                     (ulong)imx_ddr_size());
  83
  84         return 0;
  85 }
  86
  87 /* Apalis UART1 */
  88 iomux_v3_cfg_t const uart1_pads_dce[] = {
  89         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  90         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  91 };
  92 iomux_v3_cfg_t const uart1_pads_dte[] = {
  93         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  94         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  95 };
  96
  97 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  98 /* Apalis MMC1 */
  99 iomux_v3_cfg_t const usdhc1_pads[] = {
 100         MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 108         MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 109         MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 110         MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 111 #       define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
 112 };
 113
 114 /* Apalis SD1 */
 115 iomux_v3_cfg_t const usdhc2_pads[] = {
 116         MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 123 #       define GPIO_SD_CD IMX_GPIO_NR(6, 14)
 124 };
 125
 126 /* eMMC */
 127 iomux_v3_cfg_t const usdhc3_pads[] = {
 128         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 129         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 132         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 133         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 134         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 135         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 136         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 137         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 138         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 139 };
 140 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 141
 142 int mx6_rgmii_rework(struct phy_device *phydev)
 143 {
 144         int tmp;
 145
 146         switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
 147         case PHY_ID_KSZ9131:
 148                 /* read rxc dll control - devaddr = 0x02, register = 0x4c */
 149                 tmp = ksz9031_phy_extended_read(phydev, 0x02,
 150                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
 151                                            MII_KSZ9031_MOD_DATA_NO_POST_INC);
 152                 /* disable rxdll bypass (enable 2ns skew delay on RXC) */
 153                 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
 154                 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
 155                 ksz9031_phy_extended_write(phydev, 0x02,
 156                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
 157                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 158                                            tmp);
 159                 /* read txc dll control - devaddr = 0x02, register = 0x4d */
 160                 tmp = ksz9031_phy_extended_read(phydev, 0x02,
 161                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
 162                                            MII_KSZ9031_MOD_DATA_NO_POST_INC);
 163                 /* disable rxdll bypass (enable 2ns skew delay on TXC) */
 164                 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
 165                 /* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
 166                 ksz9031_phy_extended_write(phydev, 0x02,
 167                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
 168                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 169                                            tmp);
 170
 171                 /* control data pad skew - devaddr = 0x02, register = 0x04 */
 172                 ksz9031_phy_extended_write(phydev, 0x02,
 173                                            MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 174                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 175                                            0x007d);
 176                 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 177                 ksz9031_phy_extended_write(phydev, 0x02,
 178                                            MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 179                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 180                                            0x7777);
 181                 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 182                 ksz9031_phy_extended_write(phydev, 0x02,
 183                                            MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 184                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 185                                            0xdddd);
 186                 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
 187                 ksz9031_phy_extended_write(phydev, 0x02,
 188                                            MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 189                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 190                                            0x0007);
 191                 break;
 192         case PHY_ID_KSZ9031:
 193         default:
 194                 /* control data pad skew - devaddr = 0x02, register = 0x04 */
 195                 ksz9031_phy_extended_write(phydev, 0x02,
 196                                            MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 197                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 198                                            0x0000);
 199                 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 200                 ksz9031_phy_extended_write(phydev, 0x02,
 201                                            MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 202                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 203                                            0x0000);
 204                 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 205                 ksz9031_phy_extended_write(phydev, 0x02,
 206                                            MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 207                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 208                                            0x0000);
 209                 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
 210                 ksz9031_phy_extended_write(phydev, 0x02,
 211                                            MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 212                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 213                                            0x03FF);
 214                 break;
 215         }
 216
 217         return 0;
 218 }
 219
 220 iomux_v3_cfg_t const enet_pads[] = {
 221         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 222         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 223         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 224         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 225         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 226         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 227         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 228         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 229         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 230         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 231         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 232         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 233         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 234         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 235         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 236         /* KSZ9031 PHY Reset */
 237         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL) |
 238                                                   MUX_MODE_SION,
 239 #       define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 240 };
 241
 242 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 243 iomux_v3_cfg_t const gpio_pads[] = {
 244         /* Apalis GPIO1 - GPIO8 */
 245         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 246                                           MUX_MODE_SION,
 247         MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(WEAK_PULLUP) |
 248                                           MUX_MODE_SION,
 249         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 250                                           MUX_MODE_SION,
 251         MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(WEAK_PULLUP) |
 252                                           MUX_MODE_SION,
 253         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 254                                           MUX_MODE_SION,
 255         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 256                                           MUX_MODE_SION,
 257         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 258                                           MUX_MODE_SION,
 259         MX6_PAD_GPIO_6__GPIO1_IO06      | MUX_PAD_CTRL(WEAK_PULLUP) |
 260                                           MUX_MODE_SION,
 261         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 262                                           MUX_MODE_SION,
 263 };
 264
 265 static void setup_iomux_gpio(void)
 266 {
 267         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 268 }
 269
 270 iomux_v3_cfg_t const usb_pads[] = {
 271         /* USBH_EN */
 272         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 273 #       define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 274         /* USB_VBUS_DET */
 275         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 276 #       define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
 277         /* USBO1_ID */
 278         MX6_PAD_ENET_RX_ER__USB_OTG_ID  | MUX_PAD_CTRL(WEAK_PULLUP),
 279         /* USBO1_EN */
 280         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 281 #       define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 282 };
 283
 284 /*
 285  * UARTs are used in DTE mode, switch the mode on all UARTs before
 286  * any pinmuxing connects a (DCE) output to a transceiver output.
 287  */
 288 #define UCR3            0x88    /* FIFO Control Register */
 289 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 290 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 291 #define UFCR            0x90    /* FIFO Control Register */
 292 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 293
 294 static void setup_dtemode_uart(void)
 295 {
 296         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 297         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 298         setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 299         setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 300
 301         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 302         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 303         clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
 304         clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
 305 }
 306 static void setup_dcemode_uart(void)
 307 {
 308         clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 309         clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 310         clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 311         clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 312 }
 313
 314 static void setup_iomux_dte_uart(void)
 315 {
 316         setup_dtemode_uart();
 317         imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 318                                          ARRAY_SIZE(uart1_pads_dte));
 319 }
 320 static void setup_iomux_dce_uart(void)
 321 {
 322         setup_dcemode_uart();
 323         imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
 324                                          ARRAY_SIZE(uart1_pads_dce));
 325 }
 326
 327 #ifdef CONFIG_USB_EHCI_MX6
 328 int board_ehci_hcd_init(int port)
 329 {
 330         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 331         return 0;
 332 }
 333 #endif
 334
 335 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
 336 /* use the following sequence: eMMC, MMC1, SD1 */
 337 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 338         {USDHC3_BASE_ADDR},
 339         {USDHC1_BASE_ADDR},
 340         {USDHC2_BASE_ADDR},
 341 };
 342
 343 int board_mmc_getcd(struct mmc *mmc)
 344 {
 345         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 346         int ret = true; /* default: assume inserted */
 347
 348         switch (cfg->esdhc_base) {
 349         case USDHC1_BASE_ADDR:
 350                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 351                 gpio_direction_input(GPIO_MMC_CD);
 352                 ret = !gpio_get_value(GPIO_MMC_CD);
 353                 break;
 354         case USDHC2_BASE_ADDR:
 355                 gpio_request(GPIO_MMC_CD, "SD_CD");
 356                 gpio_direction_input(GPIO_SD_CD);
 357                 ret = !gpio_get_value(GPIO_SD_CD);
 358                 break;
 359         }
 360
 361         return ret;
 362 }
 363
 364 int board_mmc_init(struct bd_info *bis)
 365 {
 366         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 367         unsigned reg = readl(&psrc->sbmr1) >> 11;
 368         /*
 369          * Upon reading BOOT_CFG register the following map is done:
 370          * Bit 11 and 12 of BOOT_CFG register can determine the current
 371          * mmc port
 372          * 0x1                  SD1
 373          * 0x2                  SD2
 374          * 0x3                  SD4
 375          */
 376
 377         switch (reg & 0x3) {
 378         case 0x0:
 379                 imx_iomux_v3_setup_multiple_pads(
 380                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 381                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 382                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 383                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 384                 break;
 385         case 0x1:
 386                 imx_iomux_v3_setup_multiple_pads(
 387                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 388                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 389                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 390                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 391                 break;
 392         case 0x2:
 393                 imx_iomux_v3_setup_multiple_pads(
 394                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 395                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 396                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 397                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 398                 break;
 399         default:
 400                 puts("MMC boot device not available");
 401         }
 402
 403         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 404 }
 405 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 406
 407 int board_phy_config(struct phy_device *phydev)
 408 {
 409         mx6_rgmii_rework(phydev);
 410         if (phydev->drv->config)
 411                 phydev->drv->config(phydev);
 412
 413         return 0;
 414 }
 415
 416 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 417         /*
 418          * the bootrom sets the iomux to vselect, potentially connecting
 419          * two outputs. Set this back to GPIO
 420          */
 421         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 422 };
 423
 424 #if defined(CONFIG_VIDEO_IPUV3)
 425
 426 static iomux_v3_cfg_t const backlight_pads[] = {
 427         /* Backlight on RGB connector: J15 */
 428         MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 429                                        MUX_MODE_SION,
 430 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 431         /* additional CPU pin on BKL_PWM, keep in tristate */
 432         MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 433         /* Backlight PWM, used as GPIO in U-Boot */
 434         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 435                                        MUX_MODE_SION,
 436 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 437         /* buffer output enable 0: buffer enabled */
 438         MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 439 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 440         /* PSAVE# integrated VDAC */
 441         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 442                                        MUX_MODE_SION,
 443 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 444 };
 445
 446 static iomux_v3_cfg_t const rgb_pads[] = {
 447         MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 448         MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 449         MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 450         MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 451         MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 452         MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 453         MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 454         MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 455         MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 456         MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 457         MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 458         MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 459         MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 460         MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 461         MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 462         MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 463         MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 464         MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 465         MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 466         MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 467         MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 468         MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 469         MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
 470         MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
 471         MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
 472         MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
 473         MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
 474         MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
 475 };
 476
 477 static void do_enable_hdmi(struct display_info_t const *dev)
 478 {
 479         imx_enable_hdmi_phy();
 480 }
 481
 482 static void enable_lvds(struct display_info_t const *dev)
 483 {
 484         struct iomuxc *iomux = (struct iomuxc *)
 485                                 IOMUXC_BASE_ADDR;
 486         u32 reg = readl(&iomux->gpr[2]);
 487         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 488         writel(reg, &iomux->gpr[2]);
 489         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 490         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 491         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 492 }
 493
 494 static void enable_rgb(struct display_info_t const *dev)
 495 {
 496         imx_iomux_v3_setup_multiple_pads(
 497                 rgb_pads,
 498                 ARRAY_SIZE(rgb_pads));
 499         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 500         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 501         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 502 }
 503
 504 static int detect_default(struct display_info_t const *dev)
 505 {
 506         (void) dev;
 507         return 1;
 508 }
 509
 510 struct display_info_t const displays[] = {{
 511         .bus    = -1,
 512         .addr   = 0,
 513         .pixfmt = IPU_PIX_FMT_RGB24,
 514         .detect = detect_hdmi,
 515         .enable = do_enable_hdmi,
 516         .mode   = {
 517                 .name           = "HDMI",
 518                 .refresh        = 60,
 519                 .xres           = 1024,
 520                 .yres           = 768,
 521                 .pixclock       = 15385,
 522                 .left_margin    = 220,
 523                 .right_margin   = 40,
 524                 .upper_margin   = 21,
 525                 .lower_margin   = 7,
 526                 .hsync_len      = 60,
 527                 .vsync_len      = 10,
 528                 .sync           = FB_SYNC_EXT,
 529                 .vmode          = FB_VMODE_NONINTERLACED
 530 } }, {
 531         .bus    = -1,
 532         .addr   = 0,
 533         .di     = 1,
 534         .pixfmt = IPU_PIX_FMT_RGB24,
 535         .detect = detect_default,
 536         .enable = enable_rgb,
 537         .mode   = {
 538                 .name           = "vga-rgb",
 539                 .refresh        = 60,
 540                 .xres           = 640,
 541                 .yres           = 480,
 542                 .pixclock       = 33000,
 543                 .left_margin    = 48,
 544                 .right_margin   = 16,
 545                 .upper_margin   = 31,
 546                 .lower_margin   = 11,
 547                 .hsync_len      = 96,
 548                 .vsync_len      = 2,
 549                 .sync           = 0,
 550                 .vmode          = FB_VMODE_NONINTERLACED
 551 } }, {
 552         .bus    = -1,
 553         .addr   = 0,
 554         .di     = 1,
 555         .pixfmt = IPU_PIX_FMT_RGB24,
 556         .enable = enable_rgb,
 557         .mode   = {
 558                 .name           = "wvga-rgb",
 559                 .refresh        = 60,
 560                 .xres           = 800,
 561                 .yres           = 480,
 562                 .pixclock       = 25000,
 563                 .left_margin    = 40,
 564                 .right_margin   = 88,
 565                 .upper_margin   = 33,
 566                 .lower_margin   = 10,
 567                 .hsync_len      = 128,
 568                 .vsync_len      = 2,
 569                 .sync           = 0,
 570                 .vmode          = FB_VMODE_NONINTERLACED
 571 } }, {
 572         .bus    = -1,
 573         .addr   = 0,
 574         .pixfmt = IPU_PIX_FMT_LVDS666,
 575         .enable = enable_lvds,
 576         .mode   = {
 577                 .name           = "wsvga-lvds",
 578                 .refresh        = 60,
 579                 .xres           = 1024,
 580                 .yres           = 600,
 581                 .pixclock       = 15385,
 582                 .left_margin    = 220,
 583                 .right_margin   = 40,
 584                 .upper_margin   = 21,
 585                 .lower_margin   = 7,
 586                 .hsync_len      = 60,
 587                 .vsync_len      = 10,
 588                 .sync           = FB_SYNC_EXT,
 589                 .vmode          = FB_VMODE_NONINTERLACED
 590 } } };
 591 size_t display_count = ARRAY_SIZE(displays);
 592
 593 static void setup_display(void)
 594 {
 595         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 596         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 597         int reg;
 598
 599         enable_ipu_clock();
 600         imx_setup_hdmi();
 601         /* Turn on LDB0,IPU,IPU DI0 clocks */
 602         reg = __raw_readl(&mxc_ccm->CCGR3);
 603         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 604         writel(reg, &mxc_ccm->CCGR3);
 605
 606         /* set LDB0, LDB1 clk select to 011/011 */
 607         reg = readl(&mxc_ccm->cs2cdr);
 608         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 609                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 610         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 611               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 612         writel(reg, &mxc_ccm->cs2cdr);
 613
 614         reg = readl(&mxc_ccm->cscmr2);
 615         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 616         writel(reg, &mxc_ccm->cscmr2);
 617
 618         reg = readl(&mxc_ccm->chsccdr);
 619         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 620                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 621         writel(reg, &mxc_ccm->chsccdr);
 622
 623         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 624              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 625              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 626              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 627              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 628              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 629              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 630              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 631              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 632         writel(reg, &iomux->gpr[2]);
 633
 634         reg = readl(&iomux->gpr[3]);
 635         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 636                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 637             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 638                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 639         writel(reg, &iomux->gpr[3]);
 640
 641         /* backlight unconditionally on for now */
 642         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 643                                          ARRAY_SIZE(backlight_pads));
 644         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 645         gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
 646         gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
 647         gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
 648         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 649         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 650         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 651 }
 652
 653 /*
 654  * Backlight off before OS handover
 655  */
 656 void board_preboot_os(void)
 657 {
 658         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 659         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 660 }
 661 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 662
 663 int board_early_init_f(void)
 664 {
 665         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 666                                          ARRAY_SIZE(pwr_intb_pads));
 667 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 668         setup_iomux_dte_uart();
 669 #else
 670         setup_iomux_dce_uart();
 671 #endif
 672         return 0;
 673 }
 674
 675 /*
 676  * Do not overwrite the console
 677  * Use always serial for U-Boot console
 678  */
 679 int overwrite_console(void)
 680 {
 681         return 1;
 682 }
 683
 684 int board_init(void)
 685 {
 686         /* address of boot parameters */
 687         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 688
 689 #if defined(CONFIG_VIDEO_IPUV3)
 690         setup_display();
 691 #endif
 692
 693 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 694         (void) pmic_init();
 695 #endif
 696
 697 #ifdef CONFIG_SATA
 698         setup_sata();
 699 #endif
 700
 701         setup_iomux_gpio();
 702
 703         return 0;
 704 }
 705
 706 #ifdef CONFIG_BOARD_LATE_INIT
 707 int board_late_init(void)
 708 {
 709 #if defined(CONFIG_REVISION_TAG) && \
 710     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 711         char env_str[256];
 712         u32 rev;
 713
 714         rev = get_board_rev();
 715         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 716         env_set("board_rev", env_str);
 717
 718 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 719         if ((rev & 0xfff0) == 0x0100) {
 720                 char *fdt_env;
 721
 722                 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
 723                 setup_iomux_dce_uart();
 724
 725                 /* if using the default device tree, use version for V1.0 HW */
 726                 fdt_env = env_get("fdt_file");
 727                 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
 728                         env_set("fdt_file", FDT_FILE_V1_0);
 729                         printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
 730 #ifndef CONFIG_ENV_IS_NOWHERE
 731                         env_save();
 732 #endif
 733                 }
 734         }
 735 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 736 #endif /* CONFIG_REVISION_TAG */
 737
 738 #ifdef CONFIG_CMD_USB_SDP
 739         if (is_boot_from_usb()) {
 740                 printf("Serial Downloader recovery mode, using sdp command\n");
 741                 env_set("bootdelay", "0");
 742                 env_set("bootcmd", "sdp 0");
 743         }
 744 #endif /* CONFIG_CMD_USB_SDP */
 745
 746         return 0;
 747 }
 748 #endif /* CONFIG_BOARD_LATE_INIT */
 749
 750 int checkboard(void)
 751 {
 752         char it[] = " IT";
 753         int minc, maxc;
 754
 755         switch (get_cpu_temp_grade(&minc, &maxc)) {
 756         case TEMP_AUTOMOTIVE:
 757         case TEMP_INDUSTRIAL:
 758                 break;
 759         case TEMP_EXTCOMMERCIAL:
 760         default:
 761                 it[0] = 0;
 762         };
 763         printf("Model: Toradex Apalis iMX6 %s %s%s\n",
 764                is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
 765                (gd->ram_size == 0x80000000) ? "2GB" :
 766                (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
 767         return 0;
 768 }
 769
 770 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 771 int ft_board_setup(void *blob, struct bd_info *bd)
 772 {
 773         return ft_common_board_setup(blob, bd);
 774 }
 775 #endif
 776
 777 #ifdef CONFIG_CMD_BMODE
 778 static const struct boot_mode board_boot_modes[] = {
 779         /* 4-bit bus width */
 780         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 781         {"sd",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 782         {NULL,  0},
 783 };
 784 #endif
 785
 786 int misc_init_r(void)
 787 {
 788 #ifdef CONFIG_CMD_BMODE
 789         add_board_boot_modes(board_boot_modes);
 790 #endif
 791         return 0;
 792 }
 793
 794 #ifdef CONFIG_LDO_BYPASS_CHECK
 795 /* TODO, use external pmic, for now always ldo_enable */
 796 void ldo_mode_set(int ldo_bypass)
 797 {
 798         return;
 799 }
 800 #endif
 801
 802 #ifdef CONFIG_SPL_BUILD
 803 #include <spl.h>
 804 #include <linux/libfdt.h>
 805 #include "asm/arch/mx6q-ddr.h"
 806 #include "asm/arch/iomux.h"
 807 #include "asm/arch/crm_regs.h"
 808
 809 static int mx6_com_dcd_table[] = {
 810 /* ddr-setup.cfg */
 811 MX6_IOM_DRAM_SDQS0, 0x00000030,
 812 MX6_IOM_DRAM_SDQS1, 0x00000030,
 813 MX6_IOM_DRAM_SDQS2, 0x00000030,
 814 MX6_IOM_DRAM_SDQS3, 0x00000030,
 815 MX6_IOM_DRAM_SDQS4, 0x00000030,
 816 MX6_IOM_DRAM_SDQS5, 0x00000030,
 817 MX6_IOM_DRAM_SDQS6, 0x00000030,
 818 MX6_IOM_DRAM_SDQS7, 0x00000030,
 819
 820 MX6_IOM_GRP_B0DS, 0x00000030,
 821 MX6_IOM_GRP_B1DS, 0x00000030,
 822 MX6_IOM_GRP_B2DS, 0x00000030,
 823 MX6_IOM_GRP_B3DS, 0x00000030,
 824 MX6_IOM_GRP_B4DS, 0x00000030,
 825 MX6_IOM_GRP_B5DS, 0x00000030,
 826 MX6_IOM_GRP_B6DS, 0x00000030,
 827 MX6_IOM_GRP_B7DS, 0x00000030,
 828 MX6_IOM_GRP_ADDDS, 0x00000030,
 829 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 830 MX6_IOM_GRP_CTLDS, 0x00000030,
 831
 832 MX6_IOM_DRAM_DQM0, 0x00020030,
 833 MX6_IOM_DRAM_DQM1, 0x00020030,
 834 MX6_IOM_DRAM_DQM2, 0x00020030,
 835 MX6_IOM_DRAM_DQM3, 0x00020030,
 836 MX6_IOM_DRAM_DQM4, 0x00020030,
 837 MX6_IOM_DRAM_DQM5, 0x00020030,
 838 MX6_IOM_DRAM_DQM6, 0x00020030,
 839 MX6_IOM_DRAM_DQM7, 0x00020030,
 840
 841 MX6_IOM_DRAM_CAS, 0x00020030,
 842 MX6_IOM_DRAM_RAS, 0x00020030,
 843 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 844 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 845
 846 MX6_IOM_DRAM_RESET, 0x00020030,
 847 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 848 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 849
 850 MX6_IOM_DRAM_SDODT0, 0x00003030,
 851 MX6_IOM_DRAM_SDODT1, 0x00003030,
 852
 853 /* (differential input) */
 854 MX6_IOM_DDRMODE_CTL, 0x00020000,
 855 /* (differential input) */
 856 MX6_IOM_GRP_DDRMODE, 0x00020000,
 857 /* disable ddr pullups */
 858 MX6_IOM_GRP_DDRPKE, 0x00000000,
 859 MX6_IOM_DRAM_SDBA2, 0x00000000,
 860 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 861 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 862
 863 /* Read data DQ Byte0-3 delay */
 864 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 865 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 866 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 867 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 868 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 869 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 870 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 871 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 872
 873 /*
 874  * MDMISC       mirroring       interleaved (row/bank/col)
 875  */
 876 MX6_MMDC_P0_MDMISC, 0x00081740,
 877
 878 /*
 879  * MDSCR        con_req
 880  */
 881 MX6_MMDC_P0_MDSCR, 0x00008000,
 882
 883 /* 1066mhz_4x128mx16.cfg */
 884
 885 MX6_MMDC_P0_MDPDC, 0x00020036,
 886 MX6_MMDC_P0_MDCFG0, 0x555A7954,
 887 MX6_MMDC_P0_MDCFG1, 0xDB328F64,
 888 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 889 MX6_MMDC_P0_MDRWD, 0x000026D2,
 890 MX6_MMDC_P0_MDOR, 0x005A1023,
 891 MX6_MMDC_P0_MDOTC, 0x09555050,
 892 MX6_MMDC_P0_MDPDC, 0x00025576,
 893 MX6_MMDC_P0_MDASP, 0x00000027,
 894 MX6_MMDC_P0_MDCTL, 0x831A0000,
 895 MX6_MMDC_P0_MDSCR, 0x04088032,
 896 MX6_MMDC_P0_MDSCR, 0x00008033,
 897 MX6_MMDC_P0_MDSCR, 0x00428031,
 898 MX6_MMDC_P0_MDSCR, 0x19308030,
 899 MX6_MMDC_P0_MDSCR, 0x04008040,
 900 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 901 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 902 MX6_MMDC_P0_MDREF, 0x00005800,
 903 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 904 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 905
 906 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
 907 MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
 908 MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
 909 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
 910
 911 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
 912 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
 913
 914 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
 915 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
 916
 917 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
 918 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
 919 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
 920 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
 921
 922 MX6_MMDC_P0_MPMUR0, 0x00000800,
 923 MX6_MMDC_P1_MPMUR0, 0x00000800,
 924 MX6_MMDC_P0_MDSCR, 0x00000000,
 925 MX6_MMDC_P0_MAPSR, 0x00011006,
 926 };
 927
 928 static int mx6_it_dcd_table[] = {
 929 /* ddr-setup.cfg */
 930 MX6_IOM_DRAM_SDQS0, 0x00000030,
 931 MX6_IOM_DRAM_SDQS1, 0x00000030,
 932 MX6_IOM_DRAM_SDQS2, 0x00000030,
 933 MX6_IOM_DRAM_SDQS3, 0x00000030,
 934 MX6_IOM_DRAM_SDQS4, 0x00000030,
 935 MX6_IOM_DRAM_SDQS5, 0x00000030,
 936 MX6_IOM_DRAM_SDQS6, 0x00000030,
 937 MX6_IOM_DRAM_SDQS7, 0x00000030,
 938
 939 MX6_IOM_GRP_B0DS, 0x00000030,
 940 MX6_IOM_GRP_B1DS, 0x00000030,
 941 MX6_IOM_GRP_B2DS, 0x00000030,
 942 MX6_IOM_GRP_B3DS, 0x00000030,
 943 MX6_IOM_GRP_B4DS, 0x00000030,
 944 MX6_IOM_GRP_B5DS, 0x00000030,
 945 MX6_IOM_GRP_B6DS, 0x00000030,
 946 MX6_IOM_GRP_B7DS, 0x00000030,
 947 MX6_IOM_GRP_ADDDS, 0x00000030,
 948 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 949 MX6_IOM_GRP_CTLDS, 0x00000030,
 950
 951 MX6_IOM_DRAM_DQM0, 0x00020030,
 952 MX6_IOM_DRAM_DQM1, 0x00020030,
 953 MX6_IOM_DRAM_DQM2, 0x00020030,
 954 MX6_IOM_DRAM_DQM3, 0x00020030,
 955 MX6_IOM_DRAM_DQM4, 0x00020030,
 956 MX6_IOM_DRAM_DQM5, 0x00020030,
 957 MX6_IOM_DRAM_DQM6, 0x00020030,
 958 MX6_IOM_DRAM_DQM7, 0x00020030,
 959
 960 MX6_IOM_DRAM_CAS, 0x00020030,
 961 MX6_IOM_DRAM_RAS, 0x00020030,
 962 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 963 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 964
 965 MX6_IOM_DRAM_RESET, 0x00020030,
 966 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 967 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 968
 969 MX6_IOM_DRAM_SDODT0, 0x00003030,
 970 MX6_IOM_DRAM_SDODT1, 0x00003030,
 971
 972 /* (differential input) */
 973 MX6_IOM_DDRMODE_CTL, 0x00020000,
 974 /* (differential input) */
 975 MX6_IOM_GRP_DDRMODE, 0x00020000,
 976 /* disable ddr pullups */
 977 MX6_IOM_GRP_DDRPKE, 0x00000000,
 978 MX6_IOM_DRAM_SDBA2, 0x00000000,
 979 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 980 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 981
 982 /* Read data DQ Byte0-3 delay */
 983 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 984 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 985 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 986 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 987 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 988 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 989 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 990 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 991
 992 /*
 993  * MDMISC       mirroring       interleaved (row/bank/col)
 994  */
 995 MX6_MMDC_P0_MDMISC, 0x00081740,
 996
 997 /*
 998  * MDSCR        con_req
 999  */
1000 MX6_MMDC_P0_MDSCR, 0x00008000,
1001
1002 /* 1066mhz_4x256mx16.cfg */
1003
1004 MX6_MMDC_P0_MDPDC, 0x00020036,
1005 MX6_MMDC_P0_MDCFG0, 0x898E78f5,
1006 MX6_MMDC_P0_MDCFG1, 0xff328f64,
1007 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
1008 MX6_MMDC_P0_MDRWD, 0x000026D2,
1009 MX6_MMDC_P0_MDOR, 0x008E1023,
1010 MX6_MMDC_P0_MDOTC, 0x09444040,
1011 MX6_MMDC_P0_MDPDC, 0x00025576,
1012 MX6_MMDC_P0_MDASP, 0x00000047,
1013 MX6_MMDC_P0_MDCTL, 0x841A0000,
1014 MX6_MMDC_P0_MDSCR, 0x02888032,
1015 MX6_MMDC_P0_MDSCR, 0x00008033,
1016 MX6_MMDC_P0_MDSCR, 0x00048031,
1017 MX6_MMDC_P0_MDSCR, 0x19408030,
1018 MX6_MMDC_P0_MDSCR, 0x04008040,
1019 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1020 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1021 MX6_MMDC_P0_MDREF, 0x00007800,
1022 MX6_MMDC_P0_MPODTCTRL, 0x00022227,
1023 MX6_MMDC_P1_MPODTCTRL, 0x00022227,
1024
1025 MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
1026 MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
1027 MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
1028 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
1029
1030 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
1031 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
1032
1033 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
1034 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
1035
1036 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1037 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1038 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1039 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1040
1041 MX6_MMDC_P0_MPMUR0, 0x00000800,
1042 MX6_MMDC_P1_MPMUR0, 0x00000800,
1043 MX6_MMDC_P0_MDSCR, 0x00000000,
1044 MX6_MMDC_P0_MAPSR, 0x00011006,
1045 };
1046
1047 static void ccgr_init(void)
1048 {
1049         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1050
1051         writel(0x00C03F3F, &ccm->CCGR0);
1052         writel(0x0030FC03, &ccm->CCGR1);
1053         writel(0x0FFFFFF3, &ccm->CCGR2);
1054         writel(0x3FF0300F, &ccm->CCGR3);
1055         writel(0x00FFF300, &ccm->CCGR4);
1056         writel(0x0F0000F3, &ccm->CCGR5);
1057         writel(0x000003FF, &ccm->CCGR6);
1058
1059 /*
1060  * Setup CCM_CCOSR register as follows:
1061  *
1062  * cko1_en  = 1    --> CKO1 enabled
1063  * cko1_div = 111  --> divide by 8
1064  * cko1_sel = 1011 --> ahb_clk_root
1065  *
1066  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1067  */
1068         writel(0x000000FB, &ccm->ccosr);
1069 }
1070
1071 static void ddr_init(int *table, int size)
1072 {
1073         int i;
1074
1075         for (i = 0; i < size / 2 ; i++)
1076                 writel(table[2 * i + 1], table[2 * i]);
1077 }
1078
1079 static void spl_dram_init(void)
1080 {
1081         int minc, maxc;
1082
1083         switch (get_cpu_temp_grade(&minc, &maxc)) {
1084         case TEMP_COMMERCIAL:
1085         case TEMP_EXTCOMMERCIAL:
1086                 puts("Commercial temperature grade DDR3 timings.\n");
1087                 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1088                 break;
1089         case TEMP_INDUSTRIAL:
1090         case TEMP_AUTOMOTIVE:
1091         default:
1092                 puts("Industrial temperature grade DDR3 timings.\n");
1093                 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1094                 break;
1095         };
1096         udelay(100);
1097 }
1098
1099 void board_init_f(ulong dummy)
1100 {
1101         /* setup AIPS and disable watchdog */
1102         arch_cpu_init();
1103
1104         ccgr_init();
1105         gpr_init();
1106
1107         /* iomux */
1108         board_early_init_f();
1109
1110         /* setup GP timer */
1111         timer_init();
1112
1113         /* UART clocks enabled and gd valid - init serial console */
1114         preloader_console_init();
1115
1116 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1117         /* Make sure we use dte mode */
1118         setup_dtemode_uart();
1119 #endif
1120
1121         /* DDR initialization */
1122         spl_dram_init();
1123
1124         /* Clear the BSS. */
1125         memset(__bss_start, 0, __bss_end - __bss_start);
1126
1127         /* load/boot image from boot device */
1128         board_init_r(NULL, 0);
1129 }
1130
1131 #ifdef CONFIG_SPL_LOAD_FIT
1132 int board_fit_config_name_match(const char *name)
1133 {
1134         if (!strcmp(name, "imx6-apalis"))
1135                 return 0;
1136
1137         return -1;
1138 }
1139 #endif
1140
1141 void reset_cpu(ulong addr)
1142 {
1143 }
1144
1145 #endif /* CONFIG_SPL_BUILD */
1146
1147 static struct mxc_serial_plat mxc_serial_plat = {
1148         .reg = (struct mxc_uart *)UART1_BASE,
1149         .use_dte = true,
1150 };
1151
1152 U_BOOT_DRVINFO(mxc_serial) = {
1153         .name = "serial_mxc",
1154         .plat = &mxc_serial_plat,
1155 };