board/toradex/apalis_imx6/apalis_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <init.h>
  13 #include <net.h>
  14
  15 #include <ahci.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/imx-regs.h>
  19 #include <asm/arch/mx6-ddr.h>
  20 #include <asm/arch/mx6-pins.h>
  21 #include <asm/arch/mxc_hdmi.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/bootm.h>
  24 #include <asm/gpio.h>
  25 #include <asm/mach-imx/boot_mode.h>
  26 #include <asm/mach-imx/iomux-v3.h>
  27 #include <asm/mach-imx/sata.h>
  28 #include <asm/mach-imx/video.h>
  29 #include <dm/device-internal.h>
  30 #include <dm/platform_data/serial_mxc.h>
  31 #include <dwc_ahsata.h>
  32 #include <env.h>
  33 #include <fsl_esdhc_imx.h>
  34 #include <imx_thermal.h>
  35 #include <micrel.h>
  36 #include <miiphy.h>
  37 #include <netdev.h>
  38
  39 #include "../common/tdx-cfg-block.h"
  40 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  41 #include "pf0100.h"
  42 #endif
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  48         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  51         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  52         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  53
  54 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  55         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  56         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  57
  58 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  59         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  60
  61 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  62         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  63         PAD_CTL_SRE_SLOW)
  64
  65 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  66         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  67         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  68
  69 #define TRISTATE        (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  70
  71 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  72
  73 #define APALIS_IMX6_SATA_INIT_RETRIES   10
  74
  75 int dram_init(void)
  76 {
  77         /* use the DDR controllers configured size */
  78         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  79                                     (ulong)imx_ddr_size());
  80
  81         return 0;
  82 }
  83
  84 /* Apalis UART1 */
  85 iomux_v3_cfg_t const uart1_pads_dce[] = {
  86         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  87         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  88 };
  89 iomux_v3_cfg_t const uart1_pads_dte[] = {
  90         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  91         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  92 };
  93
  94 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  95 /* Apalis MMC1 */
  96 iomux_v3_cfg_t const usdhc1_pads[] = {
  97         MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 108 #       define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
 109 };
 110
 111 /* Apalis SD1 */
 112 iomux_v3_cfg_t const usdhc2_pads[] = {
 113         MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 120 #       define GPIO_SD_CD IMX_GPIO_NR(6, 14)
 121 };
 122
 123 /* eMMC */
 124 iomux_v3_cfg_t const usdhc3_pads[] = {
 125         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 126         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 128         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 132         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 133         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 134         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 135         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 136 };
 137 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 138
 139 int mx6_rgmii_rework(struct phy_device *phydev)
 140 {
 141         int tmp;
 142
 143         switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
 144         case PHY_ID_KSZ9131:
 145                 /* read rxc dll control - devaddr = 0x02, register = 0x4c */
 146                 tmp = ksz9031_phy_extended_read(phydev, 0x02,
 147                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
 148                                            MII_KSZ9031_MOD_DATA_NO_POST_INC);
 149                 /* disable rxdll bypass (enable 2ns skew delay on RXC) */
 150                 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
 151                 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
 152                 ksz9031_phy_extended_write(phydev, 0x02,
 153                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
 154                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 155                                            tmp);
 156                 /* read txc dll control - devaddr = 0x02, register = 0x4d */
 157                 tmp = ksz9031_phy_extended_read(phydev, 0x02,
 158                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
 159                                            MII_KSZ9031_MOD_DATA_NO_POST_INC);
 160                 /* disable rxdll bypass (enable 2ns skew delay on TXC) */
 161                 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
 162                 /* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
 163                 ksz9031_phy_extended_write(phydev, 0x02,
 164                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
 165                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 166                                            tmp);
 167
 168                 /* control data pad skew - devaddr = 0x02, register = 0x04 */
 169                 ksz9031_phy_extended_write(phydev, 0x02,
 170                                            MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 171                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 172                                            0x007d);
 173                 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 174                 ksz9031_phy_extended_write(phydev, 0x02,
 175                                            MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 176                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 177                                            0x7777);
 178                 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 179                 ksz9031_phy_extended_write(phydev, 0x02,
 180                                            MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 181                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 182                                            0xdddd);
 183                 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
 184                 ksz9031_phy_extended_write(phydev, 0x02,
 185                                            MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 186                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 187                                            0x0007);
 188                 break;
 189         case PHY_ID_KSZ9031:
 190         default:
 191                 /* control data pad skew - devaddr = 0x02, register = 0x04 */
 192                 ksz9031_phy_extended_write(phydev, 0x02,
 193                                            MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 194                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 195                                            0x0000);
 196                 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 197                 ksz9031_phy_extended_write(phydev, 0x02,
 198                                            MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 199                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 200                                            0x0000);
 201                 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 202                 ksz9031_phy_extended_write(phydev, 0x02,
 203                                            MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 204                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 205                                            0x0000);
 206                 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
 207                 ksz9031_phy_extended_write(phydev, 0x02,
 208                                            MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 209                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 210                                            0x03FF);
 211                 break;
 212         }
 213
 214         return 0;
 215 }
 216
 217 iomux_v3_cfg_t const enet_pads[] = {
 218         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 219         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 220         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 221         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 222         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 223         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 224         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 225         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 226         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 227         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 228         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 229         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 230         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 231         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 232         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 233         /* KSZ9031 PHY Reset */
 234         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL) |
 235                                                   MUX_MODE_SION,
 236 #       define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 237 };
 238
 239 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 240 iomux_v3_cfg_t const gpio_pads[] = {
 241         /* Apalis GPIO1 - GPIO8 */
 242         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 243                                           MUX_MODE_SION,
 244         MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(WEAK_PULLUP) |
 245                                           MUX_MODE_SION,
 246         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 247                                           MUX_MODE_SION,
 248         MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(WEAK_PULLUP) |
 249                                           MUX_MODE_SION,
 250         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 251                                           MUX_MODE_SION,
 252         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 253                                           MUX_MODE_SION,
 254         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 255                                           MUX_MODE_SION,
 256         MX6_PAD_GPIO_6__GPIO1_IO06      | MUX_PAD_CTRL(WEAK_PULLUP) |
 257                                           MUX_MODE_SION,
 258         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 259                                           MUX_MODE_SION,
 260 };
 261
 262 static void setup_iomux_gpio(void)
 263 {
 264         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 265 }
 266
 267 iomux_v3_cfg_t const usb_pads[] = {
 268         /* USBH_EN */
 269         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 270 #       define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 271         /* USB_VBUS_DET */
 272         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 273 #       define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
 274         /* USBO1_ID */
 275         MX6_PAD_ENET_RX_ER__USB_OTG_ID  | MUX_PAD_CTRL(WEAK_PULLUP),
 276         /* USBO1_EN */
 277         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 278 #       define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 279 };
 280
 281 /*
 282  * UARTs are used in DTE mode, switch the mode on all UARTs before
 283  * any pinmuxing connects a (DCE) output to a transceiver output.
 284  */
 285 #define UCR3            0x88    /* FIFO Control Register */
 286 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 287 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 288 #define UFCR            0x90    /* FIFO Control Register */
 289 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 290
 291 static void setup_dtemode_uart(void)
 292 {
 293         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 294         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 295         setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 296         setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 297
 298         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 299         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 300         clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
 301         clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
 302 }
 303 static void setup_dcemode_uart(void)
 304 {
 305         clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 306         clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 307         clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 308         clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 309 }
 310
 311 static void setup_iomux_dte_uart(void)
 312 {
 313         setup_dtemode_uart();
 314         imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 315                                          ARRAY_SIZE(uart1_pads_dte));
 316 }
 317 static void setup_iomux_dce_uart(void)
 318 {
 319         setup_dcemode_uart();
 320         imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
 321                                          ARRAY_SIZE(uart1_pads_dce));
 322 }
 323
 324 #ifdef CONFIG_USB_EHCI_MX6
 325 int board_ehci_hcd_init(int port)
 326 {
 327         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 328         return 0;
 329 }
 330 #endif
 331
 332 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
 333 /* use the following sequence: eMMC, MMC1, SD1 */
 334 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 335         {USDHC3_BASE_ADDR},
 336         {USDHC1_BASE_ADDR},
 337         {USDHC2_BASE_ADDR},
 338 };
 339
 340 int board_mmc_getcd(struct mmc *mmc)
 341 {
 342         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 343         int ret = true; /* default: assume inserted */
 344
 345         switch (cfg->esdhc_base) {
 346         case USDHC1_BASE_ADDR:
 347                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 348                 gpio_direction_input(GPIO_MMC_CD);
 349                 ret = !gpio_get_value(GPIO_MMC_CD);
 350                 break;
 351         case USDHC2_BASE_ADDR:
 352                 gpio_request(GPIO_MMC_CD, "SD_CD");
 353                 gpio_direction_input(GPIO_SD_CD);
 354                 ret = !gpio_get_value(GPIO_SD_CD);
 355                 break;
 356         }
 357
 358         return ret;
 359 }
 360
 361 int board_mmc_init(bd_t *bis)
 362 {
 363         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 364         unsigned reg = readl(&psrc->sbmr1) >> 11;
 365         /*
 366          * Upon reading BOOT_CFG register the following map is done:
 367          * Bit 11 and 12 of BOOT_CFG register can determine the current
 368          * mmc port
 369          * 0x1                  SD1
 370          * 0x2                  SD2
 371          * 0x3                  SD4
 372          */
 373
 374         switch (reg & 0x3) {
 375         case 0x0:
 376                 imx_iomux_v3_setup_multiple_pads(
 377                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 378                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 379                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 380                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 381                 break;
 382         case 0x1:
 383                 imx_iomux_v3_setup_multiple_pads(
 384                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 385                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 386                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 387                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 388                 break;
 389         case 0x2:
 390                 imx_iomux_v3_setup_multiple_pads(
 391                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 392                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 393                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 394                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 395                 break;
 396         default:
 397                 puts("MMC boot device not available");
 398         }
 399
 400         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 401 }
 402 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 403
 404 int board_phy_config(struct phy_device *phydev)
 405 {
 406         mx6_rgmii_rework(phydev);
 407         if (phydev->drv->config)
 408                 phydev->drv->config(phydev);
 409
 410         return 0;
 411 }
 412
 413 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 414         /*
 415          * the bootrom sets the iomux to vselect, potentially connecting
 416          * two outputs. Set this back to GPIO
 417          */
 418         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 419 };
 420
 421 #if defined(CONFIG_VIDEO_IPUV3)
 422
 423 static iomux_v3_cfg_t const backlight_pads[] = {
 424         /* Backlight on RGB connector: J15 */
 425         MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 426                                        MUX_MODE_SION,
 427 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 428         /* additional CPU pin on BKL_PWM, keep in tristate */
 429         MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 430         /* Backlight PWM, used as GPIO in U-Boot */
 431         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 432                                        MUX_MODE_SION,
 433 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 434         /* buffer output enable 0: buffer enabled */
 435         MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 436 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 437         /* PSAVE# integrated VDAC */
 438         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 439                                        MUX_MODE_SION,
 440 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 441 };
 442
 443 static iomux_v3_cfg_t const rgb_pads[] = {
 444         MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 445         MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 446         MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 447         MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 448         MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 449         MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 450         MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 451         MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 452         MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 453         MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 454         MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 455         MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 456         MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 457         MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 458         MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 459         MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 460         MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 461         MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 462         MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 463         MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 464         MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 465         MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 466         MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
 467         MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
 468         MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
 469         MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
 470         MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
 471         MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
 472 };
 473
 474 static void do_enable_hdmi(struct display_info_t const *dev)
 475 {
 476         imx_enable_hdmi_phy();
 477 }
 478
 479 static void enable_lvds(struct display_info_t const *dev)
 480 {
 481         struct iomuxc *iomux = (struct iomuxc *)
 482                                 IOMUXC_BASE_ADDR;
 483         u32 reg = readl(&iomux->gpr[2]);
 484         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 485         writel(reg, &iomux->gpr[2]);
 486         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 487         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 488         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 489 }
 490
 491 static void enable_rgb(struct display_info_t const *dev)
 492 {
 493         imx_iomux_v3_setup_multiple_pads(
 494                 rgb_pads,
 495                 ARRAY_SIZE(rgb_pads));
 496         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 497         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 498         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 499 }
 500
 501 static int detect_default(struct display_info_t const *dev)
 502 {
 503         (void) dev;
 504         return 1;
 505 }
 506
 507 struct display_info_t const displays[] = {{
 508         .bus    = -1,
 509         .addr   = 0,
 510         .pixfmt = IPU_PIX_FMT_RGB24,
 511         .detect = detect_hdmi,
 512         .enable = do_enable_hdmi,
 513         .mode   = {
 514                 .name           = "HDMI",
 515                 .refresh        = 60,
 516                 .xres           = 1024,
 517                 .yres           = 768,
 518                 .pixclock       = 15385,
 519                 .left_margin    = 220,
 520                 .right_margin   = 40,
 521                 .upper_margin   = 21,
 522                 .lower_margin   = 7,
 523                 .hsync_len      = 60,
 524                 .vsync_len      = 10,
 525                 .sync           = FB_SYNC_EXT,
 526                 .vmode          = FB_VMODE_NONINTERLACED
 527 } }, {
 528         .bus    = -1,
 529         .addr   = 0,
 530         .di     = 1,
 531         .pixfmt = IPU_PIX_FMT_RGB24,
 532         .detect = detect_default,
 533         .enable = enable_rgb,
 534         .mode   = {
 535                 .name           = "vga-rgb",
 536                 .refresh        = 60,
 537                 .xres           = 640,
 538                 .yres           = 480,
 539                 .pixclock       = 33000,
 540                 .left_margin    = 48,
 541                 .right_margin   = 16,
 542                 .upper_margin   = 31,
 543                 .lower_margin   = 11,
 544                 .hsync_len      = 96,
 545                 .vsync_len      = 2,
 546                 .sync           = 0,
 547                 .vmode          = FB_VMODE_NONINTERLACED
 548 } }, {
 549         .bus    = -1,
 550         .addr   = 0,
 551         .di     = 1,
 552         .pixfmt = IPU_PIX_FMT_RGB24,
 553         .enable = enable_rgb,
 554         .mode   = {
 555                 .name           = "wvga-rgb",
 556                 .refresh        = 60,
 557                 .xres           = 800,
 558                 .yres           = 480,
 559                 .pixclock       = 25000,
 560                 .left_margin    = 40,
 561                 .right_margin   = 88,
 562                 .upper_margin   = 33,
 563                 .lower_margin   = 10,
 564                 .hsync_len      = 128,
 565                 .vsync_len      = 2,
 566                 .sync           = 0,
 567                 .vmode          = FB_VMODE_NONINTERLACED
 568 } }, {
 569         .bus    = -1,
 570         .addr   = 0,
 571         .pixfmt = IPU_PIX_FMT_LVDS666,
 572         .enable = enable_lvds,
 573         .mode   = {
 574                 .name           = "wsvga-lvds",
 575                 .refresh        = 60,
 576                 .xres           = 1024,
 577                 .yres           = 600,
 578                 .pixclock       = 15385,
 579                 .left_margin    = 220,
 580                 .right_margin   = 40,
 581                 .upper_margin   = 21,
 582                 .lower_margin   = 7,
 583                 .hsync_len      = 60,
 584                 .vsync_len      = 10,
 585                 .sync           = FB_SYNC_EXT,
 586                 .vmode          = FB_VMODE_NONINTERLACED
 587 } } };
 588 size_t display_count = ARRAY_SIZE(displays);
 589
 590 static void setup_display(void)
 591 {
 592         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 593         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 594         int reg;
 595
 596         enable_ipu_clock();
 597         imx_setup_hdmi();
 598         /* Turn on LDB0,IPU,IPU DI0 clocks */
 599         reg = __raw_readl(&mxc_ccm->CCGR3);
 600         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 601         writel(reg, &mxc_ccm->CCGR3);
 602
 603         /* set LDB0, LDB1 clk select to 011/011 */
 604         reg = readl(&mxc_ccm->cs2cdr);
 605         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 606                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 607         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 608               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 609         writel(reg, &mxc_ccm->cs2cdr);
 610
 611         reg = readl(&mxc_ccm->cscmr2);
 612         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 613         writel(reg, &mxc_ccm->cscmr2);
 614
 615         reg = readl(&mxc_ccm->chsccdr);
 616         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 617                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 618         writel(reg, &mxc_ccm->chsccdr);
 619
 620         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 621              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 622              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 623              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 624              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 625              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 626              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 627              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 628              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 629         writel(reg, &iomux->gpr[2]);
 630
 631         reg = readl(&iomux->gpr[3]);
 632         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 633                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 634             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 635                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 636         writel(reg, &iomux->gpr[3]);
 637
 638         /* backlight unconditionally on for now */
 639         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 640                                          ARRAY_SIZE(backlight_pads));
 641         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 642         gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
 643         gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
 644         gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
 645         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 646         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 647         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 648 }
 649
 650 /*
 651  * Backlight off before OS handover
 652  */
 653 void board_preboot_os(void)
 654 {
 655         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 656         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 657 }
 658 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 659
 660 int board_early_init_f(void)
 661 {
 662         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 663                                          ARRAY_SIZE(pwr_intb_pads));
 664 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 665         setup_iomux_dte_uart();
 666 #else
 667         setup_iomux_dce_uart();
 668 #endif
 669         return 0;
 670 }
 671
 672 /*
 673  * Do not overwrite the console
 674  * Use always serial for U-Boot console
 675  */
 676 int overwrite_console(void)
 677 {
 678         return 1;
 679 }
 680
 681 int board_init(void)
 682 {
 683         /* address of boot parameters */
 684         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 685
 686 #if defined(CONFIG_VIDEO_IPUV3)
 687         setup_display();
 688 #endif
 689
 690 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 691         (void) pmic_init();
 692 #endif
 693
 694 #ifdef CONFIG_SATA
 695         setup_sata();
 696 #endif
 697
 698         setup_iomux_gpio();
 699
 700         return 0;
 701 }
 702
 703 #ifdef CONFIG_BOARD_LATE_INIT
 704 int board_late_init(void)
 705 {
 706 #if defined(CONFIG_REVISION_TAG) && \
 707     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 708         char env_str[256];
 709         u32 rev;
 710
 711         rev = get_board_rev();
 712         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 713         env_set("board_rev", env_str);
 714
 715 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 716         if ((rev & 0xfff0) == 0x0100) {
 717                 char *fdt_env;
 718
 719                 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
 720                 setup_iomux_dce_uart();
 721
 722                 /* if using the default device tree, use version for V1.0 HW */
 723                 fdt_env = env_get("fdt_file");
 724                 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
 725                         env_set("fdt_file", FDT_FILE_V1_0);
 726                         printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
 727 #ifndef CONFIG_ENV_IS_NOWHERE
 728                         env_save();
 729 #endif
 730                 }
 731         }
 732 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 733 #endif /* CONFIG_REVISION_TAG */
 734
 735 #ifdef CONFIG_CMD_USB_SDP
 736         if (is_boot_from_usb()) {
 737                 printf("Serial Downloader recovery mode, using sdp command\n");
 738                 env_set("bootdelay", "0");
 739                 env_set("bootcmd", "sdp 0");
 740         }
 741 #endif /* CONFIG_CMD_USB_SDP */
 742
 743         return 0;
 744 }
 745 #endif /* CONFIG_BOARD_LATE_INIT */
 746
 747 int checkboard(void)
 748 {
 749         char it[] = " IT";
 750         int minc, maxc;
 751
 752         switch (get_cpu_temp_grade(&minc, &maxc)) {
 753         case TEMP_AUTOMOTIVE:
 754         case TEMP_INDUSTRIAL:
 755                 break;
 756         case TEMP_EXTCOMMERCIAL:
 757         default:
 758                 it[0] = 0;
 759         };
 760         printf("Model: Toradex Apalis iMX6 %s %s%s\n",
 761                is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
 762                (gd->ram_size == 0x80000000) ? "2GB" :
 763                (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
 764         return 0;
 765 }
 766
 767 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 768 int ft_board_setup(void *blob, bd_t *bd)
 769 {
 770         return ft_common_board_setup(blob, bd);
 771 }
 772 #endif
 773
 774 #ifdef CONFIG_CMD_BMODE
 775 static const struct boot_mode board_boot_modes[] = {
 776         /* 4-bit bus width */
 777         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 778         {"sd",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 779         {NULL,  0},
 780 };
 781 #endif
 782
 783 int misc_init_r(void)
 784 {
 785 #ifdef CONFIG_CMD_BMODE
 786         add_board_boot_modes(board_boot_modes);
 787 #endif
 788         return 0;
 789 }
 790
 791 #ifdef CONFIG_LDO_BYPASS_CHECK
 792 /* TODO, use external pmic, for now always ldo_enable */
 793 void ldo_mode_set(int ldo_bypass)
 794 {
 795         return;
 796 }
 797 #endif
 798
 799 #ifdef CONFIG_SPL_BUILD
 800 #include <spl.h>
 801 #include <linux/libfdt.h>
 802 #include "asm/arch/mx6q-ddr.h"
 803 #include "asm/arch/iomux.h"
 804 #include "asm/arch/crm_regs.h"
 805
 806 static int mx6_com_dcd_table[] = {
 807 /* ddr-setup.cfg */
 808 MX6_IOM_DRAM_SDQS0, 0x00000030,
 809 MX6_IOM_DRAM_SDQS1, 0x00000030,
 810 MX6_IOM_DRAM_SDQS2, 0x00000030,
 811 MX6_IOM_DRAM_SDQS3, 0x00000030,
 812 MX6_IOM_DRAM_SDQS4, 0x00000030,
 813 MX6_IOM_DRAM_SDQS5, 0x00000030,
 814 MX6_IOM_DRAM_SDQS6, 0x00000030,
 815 MX6_IOM_DRAM_SDQS7, 0x00000030,
 816
 817 MX6_IOM_GRP_B0DS, 0x00000030,
 818 MX6_IOM_GRP_B1DS, 0x00000030,
 819 MX6_IOM_GRP_B2DS, 0x00000030,
 820 MX6_IOM_GRP_B3DS, 0x00000030,
 821 MX6_IOM_GRP_B4DS, 0x00000030,
 822 MX6_IOM_GRP_B5DS, 0x00000030,
 823 MX6_IOM_GRP_B6DS, 0x00000030,
 824 MX6_IOM_GRP_B7DS, 0x00000030,
 825 MX6_IOM_GRP_ADDDS, 0x00000030,
 826 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 827 MX6_IOM_GRP_CTLDS, 0x00000030,
 828
 829 MX6_IOM_DRAM_DQM0, 0x00020030,
 830 MX6_IOM_DRAM_DQM1, 0x00020030,
 831 MX6_IOM_DRAM_DQM2, 0x00020030,
 832 MX6_IOM_DRAM_DQM3, 0x00020030,
 833 MX6_IOM_DRAM_DQM4, 0x00020030,
 834 MX6_IOM_DRAM_DQM5, 0x00020030,
 835 MX6_IOM_DRAM_DQM6, 0x00020030,
 836 MX6_IOM_DRAM_DQM7, 0x00020030,
 837
 838 MX6_IOM_DRAM_CAS, 0x00020030,
 839 MX6_IOM_DRAM_RAS, 0x00020030,
 840 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 841 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 842
 843 MX6_IOM_DRAM_RESET, 0x00020030,
 844 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 845 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 846
 847 MX6_IOM_DRAM_SDODT0, 0x00003030,
 848 MX6_IOM_DRAM_SDODT1, 0x00003030,
 849
 850 /* (differential input) */
 851 MX6_IOM_DDRMODE_CTL, 0x00020000,
 852 /* (differential input) */
 853 MX6_IOM_GRP_DDRMODE, 0x00020000,
 854 /* disable ddr pullups */
 855 MX6_IOM_GRP_DDRPKE, 0x00000000,
 856 MX6_IOM_DRAM_SDBA2, 0x00000000,
 857 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 858 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 859
 860 /* Read data DQ Byte0-3 delay */
 861 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 862 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 863 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 864 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 865 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 866 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 867 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 868 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 869
 870 /*
 871  * MDMISC       mirroring       interleaved (row/bank/col)
 872  */
 873 MX6_MMDC_P0_MDMISC, 0x00081740,
 874
 875 /*
 876  * MDSCR        con_req
 877  */
 878 MX6_MMDC_P0_MDSCR, 0x00008000,
 879
 880 /* 1066mhz_4x128mx16.cfg */
 881
 882 MX6_MMDC_P0_MDPDC, 0x00020036,
 883 MX6_MMDC_P0_MDCFG0, 0x555A7954,
 884 MX6_MMDC_P0_MDCFG1, 0xDB328F64,
 885 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 886 MX6_MMDC_P0_MDRWD, 0x000026D2,
 887 MX6_MMDC_P0_MDOR, 0x005A1023,
 888 MX6_MMDC_P0_MDOTC, 0x09555050,
 889 MX6_MMDC_P0_MDPDC, 0x00025576,
 890 MX6_MMDC_P0_MDASP, 0x00000027,
 891 MX6_MMDC_P0_MDCTL, 0x831A0000,
 892 MX6_MMDC_P0_MDSCR, 0x04088032,
 893 MX6_MMDC_P0_MDSCR, 0x00008033,
 894 MX6_MMDC_P0_MDSCR, 0x00428031,
 895 MX6_MMDC_P0_MDSCR, 0x19308030,
 896 MX6_MMDC_P0_MDSCR, 0x04008040,
 897 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 898 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 899 MX6_MMDC_P0_MDREF, 0x00005800,
 900 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 901 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 902
 903 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
 904 MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
 905 MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
 906 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
 907
 908 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
 909 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
 910
 911 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
 912 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
 913
 914 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
 915 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
 916 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
 917 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
 918
 919 MX6_MMDC_P0_MPMUR0, 0x00000800,
 920 MX6_MMDC_P1_MPMUR0, 0x00000800,
 921 MX6_MMDC_P0_MDSCR, 0x00000000,
 922 MX6_MMDC_P0_MAPSR, 0x00011006,
 923 };
 924
 925 static int mx6_it_dcd_table[] = {
 926 /* ddr-setup.cfg */
 927 MX6_IOM_DRAM_SDQS0, 0x00000030,
 928 MX6_IOM_DRAM_SDQS1, 0x00000030,
 929 MX6_IOM_DRAM_SDQS2, 0x00000030,
 930 MX6_IOM_DRAM_SDQS3, 0x00000030,
 931 MX6_IOM_DRAM_SDQS4, 0x00000030,
 932 MX6_IOM_DRAM_SDQS5, 0x00000030,
 933 MX6_IOM_DRAM_SDQS6, 0x00000030,
 934 MX6_IOM_DRAM_SDQS7, 0x00000030,
 935
 936 MX6_IOM_GRP_B0DS, 0x00000030,
 937 MX6_IOM_GRP_B1DS, 0x00000030,
 938 MX6_IOM_GRP_B2DS, 0x00000030,
 939 MX6_IOM_GRP_B3DS, 0x00000030,
 940 MX6_IOM_GRP_B4DS, 0x00000030,
 941 MX6_IOM_GRP_B5DS, 0x00000030,
 942 MX6_IOM_GRP_B6DS, 0x00000030,
 943 MX6_IOM_GRP_B7DS, 0x00000030,
 944 MX6_IOM_GRP_ADDDS, 0x00000030,
 945 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 946 MX6_IOM_GRP_CTLDS, 0x00000030,
 947
 948 MX6_IOM_DRAM_DQM0, 0x00020030,
 949 MX6_IOM_DRAM_DQM1, 0x00020030,
 950 MX6_IOM_DRAM_DQM2, 0x00020030,
 951 MX6_IOM_DRAM_DQM3, 0x00020030,
 952 MX6_IOM_DRAM_DQM4, 0x00020030,
 953 MX6_IOM_DRAM_DQM5, 0x00020030,
 954 MX6_IOM_DRAM_DQM6, 0x00020030,
 955 MX6_IOM_DRAM_DQM7, 0x00020030,
 956
 957 MX6_IOM_DRAM_CAS, 0x00020030,
 958 MX6_IOM_DRAM_RAS, 0x00020030,
 959 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 960 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 961
 962 MX6_IOM_DRAM_RESET, 0x00020030,
 963 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 964 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 965
 966 MX6_IOM_DRAM_SDODT0, 0x00003030,
 967 MX6_IOM_DRAM_SDODT1, 0x00003030,
 968
 969 /* (differential input) */
 970 MX6_IOM_DDRMODE_CTL, 0x00020000,
 971 /* (differential input) */
 972 MX6_IOM_GRP_DDRMODE, 0x00020000,
 973 /* disable ddr pullups */
 974 MX6_IOM_GRP_DDRPKE, 0x00000000,
 975 MX6_IOM_DRAM_SDBA2, 0x00000000,
 976 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 977 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 978
 979 /* Read data DQ Byte0-3 delay */
 980 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 981 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 982 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 983 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 984 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 985 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 986 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 987 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 988
 989 /*
 990  * MDMISC       mirroring       interleaved (row/bank/col)
 991  */
 992 MX6_MMDC_P0_MDMISC, 0x00081740,
 993
 994 /*
 995  * MDSCR        con_req
 996  */
 997 MX6_MMDC_P0_MDSCR, 0x00008000,
 998
 999 /* 1066mhz_4x256mx16.cfg */
1000
1001 MX6_MMDC_P0_MDPDC, 0x00020036,
1002 MX6_MMDC_P0_MDCFG0, 0x898E78f5,
1003 MX6_MMDC_P0_MDCFG1, 0xff328f64,
1004 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
1005 MX6_MMDC_P0_MDRWD, 0x000026D2,
1006 MX6_MMDC_P0_MDOR, 0x008E1023,
1007 MX6_MMDC_P0_MDOTC, 0x09444040,
1008 MX6_MMDC_P0_MDPDC, 0x00025576,
1009 MX6_MMDC_P0_MDASP, 0x00000047,
1010 MX6_MMDC_P0_MDCTL, 0x841A0000,
1011 MX6_MMDC_P0_MDSCR, 0x02888032,
1012 MX6_MMDC_P0_MDSCR, 0x00008033,
1013 MX6_MMDC_P0_MDSCR, 0x00048031,
1014 MX6_MMDC_P0_MDSCR, 0x19408030,
1015 MX6_MMDC_P0_MDSCR, 0x04008040,
1016 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1017 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1018 MX6_MMDC_P0_MDREF, 0x00007800,
1019 MX6_MMDC_P0_MPODTCTRL, 0x00022227,
1020 MX6_MMDC_P1_MPODTCTRL, 0x00022227,
1021
1022 MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
1023 MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
1024 MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
1025 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
1026
1027 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
1028 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
1029
1030 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
1031 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
1032
1033 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1034 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1035 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1036 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1037
1038 MX6_MMDC_P0_MPMUR0, 0x00000800,
1039 MX6_MMDC_P1_MPMUR0, 0x00000800,
1040 MX6_MMDC_P0_MDSCR, 0x00000000,
1041 MX6_MMDC_P0_MAPSR, 0x00011006,
1042 };
1043
1044 static void ccgr_init(void)
1045 {
1046         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1047
1048         writel(0x00C03F3F, &ccm->CCGR0);
1049         writel(0x0030FC03, &ccm->CCGR1);
1050         writel(0x0FFFFFF3, &ccm->CCGR2);
1051         writel(0x3FF0300F, &ccm->CCGR3);
1052         writel(0x00FFF300, &ccm->CCGR4);
1053         writel(0x0F0000F3, &ccm->CCGR5);
1054         writel(0x000003FF, &ccm->CCGR6);
1055
1056 /*
1057  * Setup CCM_CCOSR register as follows:
1058  *
1059  * cko1_en  = 1    --> CKO1 enabled
1060  * cko1_div = 111  --> divide by 8
1061  * cko1_sel = 1011 --> ahb_clk_root
1062  *
1063  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1064  */
1065         writel(0x000000FB, &ccm->ccosr);
1066 }
1067
1068 static void ddr_init(int *table, int size)
1069 {
1070         int i;
1071
1072         for (i = 0; i < size / 2 ; i++)
1073                 writel(table[2 * i + 1], table[2 * i]);
1074 }
1075
1076 static void spl_dram_init(void)
1077 {
1078         int minc, maxc;
1079
1080         switch (get_cpu_temp_grade(&minc, &maxc)) {
1081         case TEMP_COMMERCIAL:
1082         case TEMP_EXTCOMMERCIAL:
1083                 puts("Commercial temperature grade DDR3 timings.\n");
1084                 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1085                 break;
1086         case TEMP_INDUSTRIAL:
1087         case TEMP_AUTOMOTIVE:
1088         default:
1089                 puts("Industrial temperature grade DDR3 timings.\n");
1090                 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1091                 break;
1092         };
1093         udelay(100);
1094 }
1095
1096 void board_init_f(ulong dummy)
1097 {
1098         /* setup AIPS and disable watchdog */
1099         arch_cpu_init();
1100
1101         ccgr_init();
1102         gpr_init();
1103
1104         /* iomux */
1105         board_early_init_f();
1106
1107         /* setup GP timer */
1108         timer_init();
1109
1110         /* UART clocks enabled and gd valid - init serial console */
1111         preloader_console_init();
1112
1113 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1114         /* Make sure we use dte mode */
1115         setup_dtemode_uart();
1116 #endif
1117
1118         /* DDR initialization */
1119         spl_dram_init();
1120
1121         /* Clear the BSS. */
1122         memset(__bss_start, 0, __bss_end - __bss_start);
1123
1124         /* load/boot image from boot device */
1125         board_init_r(NULL, 0);
1126 }
1127
1128 #ifdef CONFIG_SPL_LOAD_FIT
1129 int board_fit_config_name_match(const char *name)
1130 {
1131         if (!strcmp(name, "imx6-apalis"))
1132                 return 0;
1133
1134         return -1;
1135 }
1136 #endif
1137
1138 void reset_cpu(ulong addr)
1139 {
1140 }
1141
1142 #endif /* CONFIG_SPL_BUILD */
1143
1144 static struct mxc_serial_platdata mxc_serial_plat = {
1145         .reg = (struct mxc_uart *)UART1_BASE,
1146         .use_dte = true,
1147 };
1148
1149 U_BOOT_DEVICE(mxc_serial) = {
1150         .name = "serial_mxc",
1151         .platdata = &mxc_serial_plat,
1152 };