1 // SPDX-License-Identifier: GPL-2.0+
3 * Embest/Timll DevKit3250 board support
5 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/arch/clk.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/emc.h>
14 #include <asm/arch/wdt.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
20 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
21 static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
23 void reset_periph(void)
25 /* This function resets peripherals by triggering RESOUT_N */
26 setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
27 writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
30 writel(0, &wdt->mctrl);
31 clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
33 /* Such a long delay is needed to initialize SMSC phy */
37 int board_early_init_f(void)
39 lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
46 * nWP may be controlled by GPO19, but unpopulated by default R23
47 * makes no sense to configure this GPIO level, nWP is always high
49 lpc32xx_slc_nand_init();
56 /* adress of boot parameters */
57 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
59 #ifdef CONFIG_SYS_FLASH_CFI
60 /* Use 16-bit memory interface for NOR Flash */
61 emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
63 /* Change the NOR timings to optimum value to get maximum bandwidth */
64 emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
65 emc->stat[0].waitoen = EMC_STAT_WAITOEN(0);
66 emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
67 emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
68 emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
69 emc->stat[0].waitturn = EMC_STAT_WAITTURN(2);
77 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
78 CONFIG_SYS_SDRAM_SIZE);