4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
5 * Antoine Tenart, <atenart@adeneo-embedded.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/cache.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/ddr_defs.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/mmc_host_def.h>
20 #include <asm/arch/mem.h>
21 #include <asm/arch/mux.h>
23 DECLARE_GLOBAL_DATA_PTR;
27 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
28 #if defined(CONFIG_NAND)
34 #ifdef CONFIG_SPL_BUILD
35 static struct module_pin_mux mmc_pin_mux[] = {
36 { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
37 { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
38 { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
39 { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
40 { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
41 { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
42 { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
46 void set_uart_mux_conf(void) {}
48 void set_mux_conf_regs(void)
50 configure_module_pin_mux(mmc_pin_mux);
54 * EMIF Paramters. Refer the EMIF register documentation and the
55 * memory datasheet for details. This is for 796 MHz.
57 #define EMIF_TIM1 0x1779C9FE
58 #define EMIF_TIM2 0x50608074
59 #define EMIF_TIM3 0x009F857F
60 #define EMIF_SDREF 0x10001841
61 #define EMIF_SDCFG 0x62A73832
62 #define EMIF_PHYCFG 0x00000110
63 static const struct emif_regs ddr3_emif_regs = {
64 .sdram_config = EMIF_SDCFG,
65 .ref_ctrl = EMIF_SDREF,
66 .sdram_tim1 = EMIF_TIM1,
67 .sdram_tim2 = EMIF_TIM2,
68 .sdram_tim3 = EMIF_TIM3,
69 .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
72 static const struct cmd_control ddr3_ctrl = {
81 /* These values are obtained from the CCS app */
82 #define RD_DQS_GATE (0x1B3)
85 static struct ddr_data ddr3_data = {
86 .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
87 .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
88 .datawiratio0 = ((0x20<<10) | 0x20<<0),
89 .datagiratio0 = ((0x20<<10) | 0x20<<0),
90 .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
91 .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
94 static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
95 .dmm_lisa_map_0 = 0x00000000,
96 .dmm_lisa_map_1 = 0x00000000,
97 .dmm_lisa_map_2 = 0x80640300,
98 .dmm_lisa_map_3 = 0xC0640320,
101 void sdram_init(void)
104 * Pass in our DDR3 config information and that we have 2 EMIFs to
107 config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
108 &evm_lisa_map_regs, 2);
110 #endif /* CONFIG_SPL_BUILD */