2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
6 * Kshitij Gupta <Kshitij@ti.com>
8 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
10 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
11 * SPDX-License-Identifier: GPL-2.0+
17 #if defined(CONFIG_OMAP1610)
18 #include <./configs/omap1510.h>
23 .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
28 /*------------------------------------------------------*
29 * Ensure i-cache is enabled *
30 * To configure TC regs without fetching instruction *
31 *------------------------------------------------------*/
32 mrc p15, 0, r0, c1, c0
34 mcr p15, 0, r0, c1, c0
36 /*------------------------------------------------------*
37 *mask all IRQs by setting all bits in the INTMR default*
38 *------------------------------------------------------*/
45 /*------------------------------------------------------*
46 * Set up ARM CLM registers (IDLECT1) *
47 *------------------------------------------------------*/
48 ldr r0, REG_ARM_IDLECT1
49 ldr r1, VAL_ARM_IDLECT1
52 /*------------------------------------------------------*
53 * Set up ARM CLM registers (IDLECT2) *
54 *------------------------------------------------------*/
55 ldr r0, REG_ARM_IDLECT2
56 ldr r1, VAL_ARM_IDLECT2
59 /*------------------------------------------------------*
60 * Set up ARM CLM registers (IDLECT3) *
61 *------------------------------------------------------*/
62 ldr r0, REG_ARM_IDLECT3
63 ldr r1, VAL_ARM_IDLECT3
66 mov r1, #0x01 /* PER_EN bit */
67 ldr r0, REG_ARM_RSTCT2
68 strh r1, [r0] /* CLKM; Peripheral reset. */
70 /* Set CLKM to Sync-Scalable */
78 cmp r2, #0x100 /* wait for any bubbles to finish */
85 /* a few nops to let settle */
98 /* Ramp up the clock to 96Mhz */
100 ldr r0, REG_DPLL1_CTL
102 ands r1, r1, #0x10 /* Check if PLL is enabled. */
103 beq lock_end /* Do not look for lock if BYPASS selected */
106 ands r1, r1, #0x01 /* Check the LOCK bit.*/
107 beq 2b /* loop until bit goes hi. */
110 /*------------------------------------------------------*
111 * Turn off the watchdog during init... *
112 *------------------------------------------------------*/
114 ldr r1, WATCHDOG_VAL1
116 ldr r1, WATCHDOG_VAL2
137 /* Set memory timings corresponding to the new clock speed */
138 ldr r3, VAL_SDRAM_CONFIG_SDF0
140 /* Check execution location to determine current execution location
141 * and branch to appropriate initialization code.
143 mov r0, #0x10000000 /* Load physical SDRAM base. */
144 mov r1, pc /* Get current execution location. */
145 cmp r1, r0 /* Compare. */
146 bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */
148 /* identify the device revision, -- TMX or TMP(TMS) */
149 ldr r0, REG_DEVICE_ID
152 ldr r0, VAL_DEVICE_ID_TMP
158 /* Enable TMP/TMS device new features */
160 ldr r1, REG_TC_EMIFF_DOUBLER
163 /* Enable new ac parameters */
165 ldr r1, REG_SDRAM_CONFIG2
168 ldr r3, VAL_SDRAM_CONFIG_SDF1
173 * Delay for SDRAM initialization.
175 mov r0, #0x1800 /* value should be checked */
177 subs r0, r0, #0x1 /* Decrement count */
181 * Set SDRAM control values. Disable refresh before MRS command.
184 /* mobile ddr operation */
185 ldr r0, REG_SDRAM_OPERATION
189 /* config register */
190 ldr r0, REG_SDRAM_CONFIG
193 /* manual command register */
194 ldr r0, REG_SDRAM_MANUAL_CMD
196 /* issue set cke high */
197 mov r1, #CMD_SDRAM_CKE_SET_HIGH
201 mov r1, #CMD_SDRAM_NOP
207 bne waitMDDR1 /* delay loop */
209 /* issue precharge */
210 mov r1, #CMD_SDRAM_PRECHARGE
213 /* issue autorefresh x 2 */
214 mov r1, #CMD_SDRAM_AUTOREFRESH
218 /* mrs register ddr mobile */
219 ldr r0, REG_SDRAM_MRS
223 /* emrs1 low-power register */
224 ldr r0, REG_SDRAM_EMRS1
225 /* self refresh on all banks */
229 ldr r0, REG_DLL_URD_CONTROL
230 ldr r1, DLL_URD_CONTROL_VAL
233 ldr r0, REG_DLL_LRD_CONTROL
234 ldr r1, DLL_LRD_CONTROL_VAL
237 ldr r0, REG_DLL_WRT_CONTROL
238 ldr r1, DLL_WRT_CONTROL_VAL
248 * Delay for SDRAM initialization.
252 subs r0, r0, #1 /* Decrement count. */
257 ldr r0, REG_SDRAM_CONFIG
262 ldr r1, VAL_TC_EMIFS_CS0_CONFIG
263 ldr r0, REG_TC_EMIFS_CS0_CONFIG
264 str r1, [r0] /* Chip Select 0 */
266 ldr r1, VAL_TC_EMIFS_CS1_CONFIG
267 ldr r0, REG_TC_EMIFS_CS1_CONFIG
268 str r1, [r0] /* Chip Select 1 */
270 ldr r1, VAL_TC_EMIFS_CS3_CONFIG
271 ldr r0, REG_TC_EMIFS_CS3_CONFIG
272 str r1, [r0] /* Chip Select 3 */
274 ldr r1, VAL_TC_EMIFS_DWS
275 ldr r0, REG_TC_EMIFS_DWS
276 str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */
278 #ifdef CONFIG_H2_OMAP1610
279 /* inserting additional 2 clock cycle hold time for LAN */
280 ldr r0, REG_TC_EMIFS_CS1_ADVANCED
281 ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
284 /* Start MPU Timer 1 */
285 ldr r0, REG_MPU_LOAD_TIMER
286 ldr r1, VAL_MPU_LOAD_TIMER
289 ldr r0, REG_MPU_CNTL_TIMER
290 ldr r1, VAL_MPU_CNTL_TIMER
294 * Setup a temporary stack
297 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
300 * Save the old lr(passed in ip) and the current lr to stack
305 * go setup pll, mux, memory
310 /* back to arch calling code */
313 /* the literal pools origin */
316 REG_DEVICE_ID: /* 32 bits */
320 REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
322 REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
324 REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
326 REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
328 REG_TC_EMIFS_DWS: /* 32 bits */
330 #ifdef CONFIG_H2_OMAP1610
331 REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
335 /* MPU clock/reset/power mode control registers */
336 REG_ARM_CKCTL: /* 16 bits */
338 REG_ARM_IDLECT3: /* 16 bits */
340 REG_ARM_IDLECT2: /* 16 bits */
342 REG_ARM_IDLECT1: /* 16 bits */
344 REG_ARM_RSTCT2: /* 16 bits */
346 REG_ARM_SYSST: /* 16 bits */
349 /* DPLL control registers */
350 REG_DPLL1_CTL: /* 16 bits */
353 /* Watch Dog register */
354 /* secure watchdog stop */
357 /* watchdog write pending */
366 /* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
367 counter @8192 rows, 10 ns, 8 burst */
372 REG_TC_EMIFF_DOUBLER: /* 32 bits */
375 /* Operation register */
379 /* Manual command register */
380 REG_SDRAM_MANUAL_CMD:
383 /* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
387 /* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
391 /* WRT DLL register */
395 .word 0x03f00002 /* Phase of 72deg, write offset +31 */
397 /* URD DLL register */
401 .word 0x00800002 /* Phase of 72deg, read offset +31 */
403 /* LRD DLL register */
407 .word 0x00800002 /* read offset +31 */
425 /* 96 MHz Samsung Mobile DDR */
426 /* Original setting for TMX device */
427 VAL_SDRAM_CONFIG_SDF0:
430 /* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
431 VAL_SDRAM_CONFIG_SDF1:
435 .word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */
439 #ifdef CONFIG_OSK_OMAP5912
440 VAL_TC_EMIFS_CS0_CONFIG:
442 VAL_TC_EMIFS_CS1_CONFIG:
444 VAL_TC_EMIFS_CS2_CONFIG:
446 VAL_TC_EMIFS_CS3_CONFIG:
448 VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */
450 VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */
454 #ifdef CONFIG_H2_OMAP1610
455 VAL_TC_EMIFS_CS0_CONFIG:
457 VAL_TC_EMIFS_CS1_CONFIG:
459 VAL_TC_EMIFS_CS2_CONFIG:
461 VAL_TC_EMIFS_CS3_CONFIG:
463 VAL_TC_EMIFS_CS1_ADVANCED:
475 .word CONFIG_SYS_INIT_SP_ADDR
478 .equ CMD_SDRAM_NOP, 0x00000000
479 .equ CMD_SDRAM_PRECHARGE, 0x00000001
480 .equ CMD_SDRAM_AUTOREFRESH, 0x00000002
481 .equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007