board/ti/ks2_evm/ddr3_k2e.c

   1 /*
   2  * Keystone2: DDR3 initialization
   3  *
   4  * (C) Copyright 2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include "ddr3_cfg.h"
  12 #include <asm/arch/ddr3.h>
  13
  14 static int ddr3_size;
  15 static struct pll_init_data ddr3_400 = DDR3_PLL_400;
  16
  17 void ddr3_init(void)
  18 {
  19         char dimm_name[32];
  20
  21         if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
  22                 init_pll(&ddr3_400);
  23
  24         ddr3_get_dimm_params(dimm_name);
  25
  26         printf("Detected SO-DIMM [%s]\n", dimm_name);
  27
  28         /* Reset DDR3 PHY after PLL enabled */
  29         ddr3_reset_ddrphy();
  30
  31         if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
  32                 /* 8G SO-DIMM */
  33                 ddr3_size = 8;
  34                 printf("DRAM: 8 GiB\n");
  35                 ddr3phy_1600_8g.zq0cr1 |= 0x10000;
  36                 ddr3phy_1600_8g.zq1cr1 |= 0x10000;
  37                 ddr3phy_1600_8g.zq2cr1 |= 0x10000;
  38                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
  39                 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g);
  40         } else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) {
  41                 /* 4G SO-DIMM */
  42                 ddr3_size = 4;
  43                 printf("DRAM: 4 GiB\n");
  44                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
  45                 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
  46         }
  47 }
  48
  49 /**
  50  * ddr3_get_size - return ddr3 size in GiB
  51  */
  52 int ddr3_get_size(void)
  53 {
  54         return ddr3_size;
  55 }