board/ti/ks2_evm/board_k2g.c

   1 /*
   2  * K2G EVM : Board initialization
   3  *
   4  * (C) Copyright 2015
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #include <common.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/ti-common/keystone_net.h>
  12 #include <asm/arch/psc_defs.h>
  13 #include <asm/arch/mmc_host_def.h>
  14 #include "mux-k2g.h"
  15 #include "../common/board_detect.h"
  16
  17 #define SYS_CLK         24000000
  18
  19 unsigned int external_clk[ext_clk_count] = {
  20         [sys_clk]       =       SYS_CLK,
  21         [pa_clk]        =       SYS_CLK,
  22         [tetris_clk]    =       SYS_CLK,
  23         [ddr3a_clk]     =       SYS_CLK,
  24         [uart_clk]      =       SYS_CLK,
  25 };
  26
  27 static int arm_speeds[DEVSPEED_NUMSPDS] = {
  28         SPD400,
  29         SPD600,
  30         SPD800,
  31         SPD900,
  32         SPD1000,
  33         SPD900,
  34         SPD800,
  35         SPD600,
  36         SPD400,
  37         SPD200,
  38 };
  39
  40 static int dev_speeds[DEVSPEED_NUMSPDS] = {
  41         SPD600,
  42         SPD800,
  43         SPD900,
  44         SPD1000,
  45         SPD900,
  46         SPD800,
  47         SPD600,
  48         SPD400,
  49 };
  50
  51 static struct pll_init_data main_pll_config[NUM_SPDS] = {
  52         [SPD400]        = {MAIN_PLL, 100, 3, 2},
  53         [SPD600]        = {MAIN_PLL, 300, 6, 2},
  54         [SPD800]        = {MAIN_PLL, 200, 3, 2},
  55         [SPD900] =      {TETRIS_PLL, 75, 1, 2},
  56         [SPD1000] =     {TETRIS_PLL, 250, 3, 2},
  57 };
  58
  59 static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
  60         [SPD200] =      {TETRIS_PLL, 250, 3, 10},
  61         [SPD400] =      {TETRIS_PLL, 100, 1, 6},
  62         [SPD600] =      {TETRIS_PLL, 100, 1, 4},
  63         [SPD800] =      {TETRIS_PLL, 400, 3, 4},
  64         [SPD900] =      {TETRIS_PLL, 75, 1, 2},
  65         [SPD1000] =     {TETRIS_PLL, 250, 3, 2},
  66 };
  67
  68 static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
  69 static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
  70 static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 133, 1, 16};
  71
  72 struct pll_init_data *get_pll_init_data(int pll)
  73 {
  74         int speed;
  75         struct pll_init_data *data = NULL;
  76
  77         switch (pll) {
  78         case MAIN_PLL:
  79                 speed = get_max_dev_speed(dev_speeds);
  80                 data = &main_pll_config[speed];
  81                 break;
  82         case TETRIS_PLL:
  83                 speed = get_max_arm_speed(arm_speeds);
  84                 data = &tetris_pll_config[speed];
  85                 break;
  86         case NSS_PLL:
  87                 data = &nss_pll_config;
  88                 break;
  89         case UART_PLL:
  90                 data = &uart_pll_config;
  91                 break;
  92         case DDR3_PLL:
  93                 data = &ddr3_pll_config;
  94                 break;
  95         default:
  96                 data = NULL;
  97         }
  98
  99         return data;
 100 }
 101
 102 s16 divn_val[16] = {
 103         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 104 };
 105
 106 #if defined(CONFIG_GENERIC_MMC)
 107 int board_mmc_init(bd_t *bis)
 108 {
 109         if (psc_enable_module(KS2_LPSC_MMC)) {
 110                 printf("%s module enabled failed\n", __func__);
 111                 return -1;
 112         }
 113
 114         omap_mmc_init(0, 0, 0, -1, -1);
 115         omap_mmc_init(1, 0, 0, -1, -1);
 116         return 0;
 117 }
 118 #endif
 119
 120 #ifdef CONFIG_BOARD_EARLY_INIT_F
 121
 122 static void k2g_reset_mux_config(void)
 123 {
 124         /* Unlock the reset mux register */
 125         clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 126
 127         /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
 128         clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
 129                         RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
 130
 131         /* lock the reset mux register to prevent any spurious writes. */
 132         setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 133 }
 134
 135 int board_early_init_f(void)
 136 {
 137         init_plls();
 138
 139         k2g_mux_config();
 140
 141         k2g_reset_mux_config();
 142
 143         /* deassert FLASH_HOLD */
 144         clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
 145                      BIT(9));
 146         setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
 147                      BIT(9));
 148
 149         return 0;
 150 }
 151 #endif
 152
 153 #ifdef CONFIG_BOARD_LATE_INIT
 154 int board_late_init(void)
 155 {
 156 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
 157         int rc;
 158
 159         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 160                         CONFIG_EEPROM_CHIP_ADDRESS);
 161         if (rc)
 162                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 163
 164         board_ti_set_ethaddr(1);
 165 #endif
 166
 167         return 0;
 168 }
 169 #endif
 170
 171 #ifdef CONFIG_SPL_BUILD
 172 void spl_init_keystone_plls(void)
 173 {
 174         init_plls();
 175 }
 176 #endif
 177
 178 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
 179 struct eth_priv_t eth_priv_cfg[] = {
 180         {
 181                 .int_name       = "K2G_EMAC",
 182                 .rx_flow        = 0,
 183                 .phy_addr       = 0,
 184                 .slave_port     = 1,
 185                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
 186                 .phy_if          = PHY_INTERFACE_MODE_RGMII,
 187         },
 188 };
 189
 190 int get_num_eth_ports(void)
 191 {
 192         return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
 193 }
 194 #endif