board/ti/ks2_evm/board_k2g.c

   1 /*
   2  * K2G EVM : Board initialization
   3  *
   4  * (C) Copyright 2015
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #include <common.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/ti-common/keystone_net.h>
  12 #include <asm/arch/psc_defs.h>
  13 #include <asm/arch/mmc_host_def.h>
  14 #include <fdtdec.h>
  15 #include <i2c.h>
  16 #include "mux-k2g.h"
  17 #include "../common/board_detect.h"
  18
  19 #define K2G_GP_AUDIO_CODEC_ADDRESS      0x1B
  20
  21 const unsigned int sysclk_array[MAX_SYSCLK] = {
  22         19200000,
  23         24000000,
  24         25000000,
  25         26000000,
  26 };
  27
  28 unsigned int get_external_clk(u32 clk)
  29 {
  30         unsigned int clk_freq;
  31         u8 sysclk_index = get_sysclk_index();
  32
  33         switch (clk) {
  34         case sys_clk:
  35                 clk_freq = sysclk_array[sysclk_index];
  36                 break;
  37         case pa_clk:
  38                 clk_freq = sysclk_array[sysclk_index];
  39                 break;
  40         case tetris_clk:
  41                 clk_freq = sysclk_array[sysclk_index];
  42                 break;
  43         case ddr3a_clk:
  44                 clk_freq = sysclk_array[sysclk_index];
  45                 break;
  46         case uart_clk:
  47                 clk_freq = sysclk_array[sysclk_index];
  48                 break;
  49         default:
  50                 clk_freq = 0;
  51                 break;
  52         }
  53
  54         return clk_freq;
  55 }
  56
  57 static int arm_speeds[DEVSPEED_NUMSPDS] = {
  58         SPD400,
  59         SPD600,
  60         SPD800,
  61         SPD900,
  62         SPD1000,
  63         SPD900,
  64         SPD800,
  65         SPD600,
  66         SPD400,
  67         SPD200,
  68 };
  69
  70 static int dev_speeds[DEVSPEED_NUMSPDS] = {
  71         SPD600,
  72         SPD800,
  73         SPD900,
  74         SPD1000,
  75         SPD900,
  76         SPD800,
  77         SPD600,
  78         SPD400,
  79 };
  80
  81 static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
  82         [SYSCLK_19MHz] = {
  83                 [SPD400]        = {MAIN_PLL, 125, 3, 2},
  84                 [SPD600]        = {MAIN_PLL, 125, 2, 2},
  85                 [SPD800]        = {MAIN_PLL, 250, 3, 2},
  86                 [SPD900]        = {MAIN_PLL, 187, 2, 2},
  87                 [SPD1000]       = {MAIN_PLL, 104, 1, 2},
  88         },
  89         [SYSCLK_24MHz] = {
  90                 [SPD400]        = {MAIN_PLL, 100, 3, 2},
  91                 [SPD600]        = {MAIN_PLL, 300, 6, 2},
  92                 [SPD800]        = {MAIN_PLL, 200, 3, 2},
  93                 [SPD900]        = {MAIN_PLL, 75, 1, 2},
  94                 [SPD1000]       = {MAIN_PLL, 250, 3, 2},
  95         },
  96         [SYSCLK_25MHz] = {
  97                 [SPD400]        = {MAIN_PLL, 32, 1, 2},
  98                 [SPD600]        = {MAIN_PLL, 48, 1, 2},
  99                 [SPD800]        = {MAIN_PLL, 64, 1, 2},
 100                 [SPD900]        = {MAIN_PLL, 72, 1, 2},
 101                 [SPD1000]       = {MAIN_PLL, 80, 1, 2},
 102         },
 103         [SYSCLK_26MHz] = {
 104                 [SPD400]        = {MAIN_PLL, 400, 13, 2},
 105                 [SPD600]        = {MAIN_PLL, 230, 5, 2},
 106                 [SPD800]        = {MAIN_PLL, 123, 2, 2},
 107                 [SPD900]        = {MAIN_PLL, 69, 1, 2},
 108                 [SPD1000]       = {MAIN_PLL, 384, 5, 2},
 109         },
 110 };
 111
 112 static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
 113         [SYSCLK_19MHz] = {
 114                 [SPD200]        = {TETRIS_PLL, 625, 6, 10},
 115                 [SPD400]        = {TETRIS_PLL, 125, 1, 6},
 116                 [SPD600]        = {TETRIS_PLL, 125, 1, 4},
 117                 [SPD800]        = {TETRIS_PLL, 333, 2, 4},
 118                 [SPD900]        = {TETRIS_PLL, 187, 2, 2},
 119                 [SPD1000]       = {TETRIS_PLL, 104, 1, 2},
 120         },
 121         [SYSCLK_24MHz] = {
 122                 [SPD200]        = {TETRIS_PLL, 250, 3, 10},
 123                 [SPD400]        = {TETRIS_PLL, 100, 1, 6},
 124                 [SPD600]        = {TETRIS_PLL, 100, 1, 4},
 125                 [SPD800]        = {TETRIS_PLL, 400, 3, 4},
 126                 [SPD900]        = {TETRIS_PLL, 75, 1, 2},
 127                 [SPD1000]       = {TETRIS_PLL, 250, 3, 2},
 128         },
 129         [SYSCLK_25MHz] = {
 130                 [SPD200]        = {TETRIS_PLL, 80, 1, 10},
 131                 [SPD400]        = {TETRIS_PLL, 96, 1, 6},
 132                 [SPD600]        = {TETRIS_PLL, 96, 1, 4},
 133                 [SPD800]        = {TETRIS_PLL, 128, 1, 4},
 134                 [SPD900]        = {TETRIS_PLL, 72, 1, 2},
 135                 [SPD1000]       = {TETRIS_PLL, 80, 1, 2},
 136         },
 137         [SYSCLK_26MHz] = {
 138                 [SPD200]        = {TETRIS_PLL, 307, 4, 10},
 139                 [SPD400]        = {TETRIS_PLL, 369, 4, 6},
 140                 [SPD600]        = {TETRIS_PLL, 369, 4, 4},
 141                 [SPD800]        = {TETRIS_PLL, 123, 1, 4},
 142                 [SPD900]        = {TETRIS_PLL, 69, 1, 2},
 143                 [SPD1000]       = {TETRIS_PLL, 384, 5, 2},
 144         },
 145 };
 146
 147 static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
 148         [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
 149         [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
 150         [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
 151         [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
 152 };
 153
 154 static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
 155         [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
 156         [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
 157         [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
 158         [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
 159 };
 160
 161 static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
 162         [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
 163         [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
 164         [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
 165         [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
 166 };
 167
 168 struct pll_init_data *get_pll_init_data(int pll)
 169 {
 170         int speed;
 171         struct pll_init_data *data = NULL;
 172         u8 sysclk_index = get_sysclk_index();
 173
 174         switch (pll) {
 175         case MAIN_PLL:
 176                 speed = get_max_dev_speed(dev_speeds);
 177                 data = &main_pll_config[sysclk_index][speed];
 178                 break;
 179         case TETRIS_PLL:
 180                 speed = get_max_arm_speed(arm_speeds);
 181                 data = &tetris_pll_config[sysclk_index][speed];
 182                 break;
 183         case NSS_PLL:
 184                 data = &nss_pll_config[sysclk_index];
 185                 break;
 186         case UART_PLL:
 187                 data = &uart_pll_config[sysclk_index];
 188                 break;
 189         case DDR3_PLL:
 190                 data = &ddr3_pll_config[sysclk_index];
 191                 break;
 192         default:
 193                 data = NULL;
 194         }
 195
 196         return data;
 197 }
 198
 199 s16 divn_val[16] = {
 200         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 201 };
 202
 203 #if defined(CONFIG_MMC)
 204 int board_mmc_init(bd_t *bis)
 205 {
 206         if (psc_enable_module(KS2_LPSC_MMC)) {
 207                 printf("%s module enabled failed\n", __func__);
 208                 return -1;
 209         }
 210
 211         omap_mmc_init(0, 0, 0, -1, -1);
 212         omap_mmc_init(1, 0, 0, -1, -1);
 213         return 0;
 214 }
 215 #endif
 216
 217 #if defined(CONFIG_DTB_RESELECT)
 218 static int k2g_alt_board_detect(void)
 219 {
 220         int rc;
 221
 222         rc = i2c_set_bus_num(1);
 223         if (rc)
 224                 return rc;
 225
 226         rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
 227         if (rc)
 228                 return rc;
 229
 230         ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
 231
 232         return 0;
 233 }
 234
 235 int embedded_dtb_select(void)
 236 {
 237         int rc;
 238
 239         rc = k2g_alt_board_detect();
 240         if (rc) {
 241                 printf("Unable to do board detection\n");
 242                 return -1;
 243         }
 244
 245         fdtdec_setup();
 246
 247         return 0;
 248 }
 249 #endif
 250
 251 #ifdef CONFIG_BOARD_EARLY_INIT_F
 252
 253 static void k2g_reset_mux_config(void)
 254 {
 255         /* Unlock the reset mux register */
 256         clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 257
 258         /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
 259         clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
 260                         RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
 261
 262         /* lock the reset mux register to prevent any spurious writes. */
 263         setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 264 }
 265
 266 int board_early_init_f(void)
 267 {
 268         init_plls();
 269
 270         k2g_mux_config();
 271
 272         k2g_reset_mux_config();
 273
 274         /* deassert FLASH_HOLD */
 275         clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
 276                      BIT(9));
 277         setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
 278                      BIT(9));
 279
 280         return 0;
 281 }
 282 #endif
 283
 284 #ifdef CONFIG_BOARD_LATE_INIT
 285 int board_late_init(void)
 286 {
 287 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
 288         int rc;
 289
 290         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 291                         CONFIG_EEPROM_CHIP_ADDRESS);
 292         if (rc)
 293                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 294
 295         board_ti_set_ethaddr(1);
 296 #endif
 297
 298         return 0;
 299 }
 300 #endif
 301
 302 #ifdef CONFIG_SPL_BUILD
 303 void spl_init_keystone_plls(void)
 304 {
 305         init_plls();
 306 }
 307 #endif
 308
 309 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
 310 struct eth_priv_t eth_priv_cfg[] = {
 311         {
 312                 .int_name       = "K2G_EMAC",
 313                 .rx_flow        = 0,
 314                 .phy_addr       = 0,
 315                 .slave_port     = 1,
 316                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
 317                 .phy_if          = PHY_INTERFACE_MODE_RGMII,
 318         },
 319 };
 320
 321 int get_num_eth_ports(void)
 322 {
 323         return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
 324 }
 325 #endif