board/ti/ks2_evm/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Keystone : Board initialization
   4  *
   5  * (C) Copyright 2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include "board.h"
  11 #include <spl.h>
  12 #include <exports.h>
  13 #include <fdt_support.h>
  14 #include <asm/arch/ddr3.h>
  15 #include <asm/arch/psc_defs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/ti-common/ti-aemif.h>
  18 #include <asm/ti-common/keystone_net.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #if defined(CONFIG_TI_AEMIF)
  23 static struct aemif_config aemif_configs[] = {
  24         {                       /* CS0 */
  25                 .mode           = AEMIF_MODE_NAND,
  26                 .wr_setup       = 0xf,
  27                 .wr_strobe      = 0x3f,
  28                 .wr_hold        = 7,
  29                 .rd_setup       = 0xf,
  30                 .rd_strobe      = 0x3f,
  31                 .rd_hold        = 7,
  32                 .turn_around    = 3,
  33                 .width          = AEMIF_WIDTH_8,
  34         },
  35 };
  36 #endif
  37
  38 int dram_init(void)
  39 {
  40         u32 ddr3_size;
  41
  42         ddr3_size = ddr3_init();
  43
  44         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  45                                     CONFIG_MAX_RAM_BANK_SIZE);
  46 #if defined(CONFIG_TI_AEMIF)
  47         if (!board_is_k2g_ice())
  48                 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
  49 #endif
  50
  51         if (!board_is_k2g_ice()) {
  52                 if (ddr3_size)
  53                         ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
  54                 else
  55                         ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
  56                                       gd->ram_size >> 30);
  57         }
  58
  59         return 0;
  60 }
  61
  62 int board_init(void)
  63 {
  64         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  65
  66         return 0;
  67 }
  68
  69 #ifdef CONFIG_SPL_BUILD
  70 void spl_board_init(void)
  71 {
  72         spl_init_keystone_plls();
  73         preloader_console_init();
  74 }
  75
  76 u32 spl_boot_device(void)
  77 {
  78 #if defined(CONFIG_SPL_SPI_LOAD)
  79         return BOOT_DEVICE_SPI;
  80 #else
  81         puts("Unknown boot device\n");
  82         hang();
  83 #endif
  84 }
  85 #endif
  86
  87 #ifdef CONFIG_OF_BOARD_SETUP
  88 int ft_board_setup(void *blob, bd_t *bd)
  89 {
  90         int lpae;
  91         char *env;
  92         char *endp;
  93         int nbanks;
  94         u64 size[2];
  95         u64 start[2];
  96         u32 ddr3a_size;
  97
  98         env = env_get("mem_lpae");
  99         lpae = env && simple_strtol(env, NULL, 0);
 100
 101         ddr3a_size = 0;
 102         if (lpae) {
 103                 ddr3a_size = ddr3_get_size();
 104                 if ((ddr3a_size != 8) && (ddr3a_size != 4))
 105                         ddr3a_size = 0;
 106         }
 107
 108         nbanks = 1;
 109         start[0] = bd->bi_dram[0].start;
 110         size[0]  = bd->bi_dram[0].size;
 111
 112         /* adjust memory start address for LPAE */
 113         if (lpae) {
 114                 start[0] -= CONFIG_SYS_SDRAM_BASE;
 115                 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
 116         }
 117
 118         if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
 119                 size[1] = ((u64)ddr3a_size - 2) << 30;
 120                 start[1] = 0x880000000;
 121                 nbanks++;
 122         }
 123
 124         /* reserve memory at start of bank */
 125         env = env_get("mem_reserve_head");
 126         if (env) {
 127                 start[0] += ustrtoul(env, &endp, 0);
 128                 size[0] -= ustrtoul(env, &endp, 0);
 129         }
 130
 131         env = env_get("mem_reserve");
 132         if (env)
 133                 size[0] -= ustrtoul(env, &endp, 0);
 134
 135         fdt_fixup_memory_banks(blob, start, size, nbanks);
 136
 137         return 0;
 138 }
 139
 140 void ft_board_setup_ex(void *blob, bd_t *bd)
 141 {
 142         int lpae;
 143         u64 size;
 144         char *env;
 145         u64 *reserve_start;
 146         int unitrd_fixup = 0;
 147
 148         env = env_get("mem_lpae");
 149         lpae = env && simple_strtol(env, NULL, 0);
 150         env = env_get("uinitrd_fixup");
 151         unitrd_fixup = env && simple_strtol(env, NULL, 0);
 152
 153         /* Fix up the initrd */
 154         if (lpae && unitrd_fixup) {
 155                 int nodeoffset;
 156                 int err;
 157                 u64 *prop1, *prop2;
 158                 u64 initrd_start, initrd_end;
 159
 160                 nodeoffset = fdt_path_offset(blob, "/chosen");
 161                 if (nodeoffset >= 0) {
 162                         prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
 163                                             "linux,initrd-start", NULL);
 164                         prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
 165                                             "linux,initrd-end", NULL);
 166                         if (prop1 && prop2) {
 167                                 initrd_start = __be64_to_cpu(*prop1);
 168                                 initrd_start -= CONFIG_SYS_SDRAM_BASE;
 169                                 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
 170                                 initrd_start = __cpu_to_be64(initrd_start);
 171                                 initrd_end = __be64_to_cpu(*prop2);
 172                                 initrd_end -= CONFIG_SYS_SDRAM_BASE;
 173                                 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
 174                                 initrd_end = __cpu_to_be64(initrd_end);
 175
 176                                 err = fdt_delprop(blob, nodeoffset,
 177                                                   "linux,initrd-start");
 178                                 if (err < 0)
 179                                         puts("error deleting initrd-start\n");
 180
 181                                 err = fdt_delprop(blob, nodeoffset,
 182                                                   "linux,initrd-end");
 183                                 if (err < 0)
 184                                         puts("error deleting initrd-end\n");
 185
 186                                 err = fdt_setprop(blob, nodeoffset,
 187                                                   "linux,initrd-start",
 188                                                   &initrd_start,
 189                                                   sizeof(initrd_start));
 190                                 if (err < 0)
 191                                         puts("error adding initrd-start\n");
 192
 193                                 err = fdt_setprop(blob, nodeoffset,
 194                                                   "linux,initrd-end",
 195                                                   &initrd_end,
 196                                                   sizeof(initrd_end));
 197                                 if (err < 0)
 198                                         puts("error adding linux,initrd-end\n");
 199                         }
 200                 }
 201         }
 202
 203         if (lpae) {
 204                 /*
 205                  * the initrd and other reserved memory areas are
 206                  * embedded in in the DTB itslef. fix up these addresses
 207                  * to 36 bit format
 208                  */
 209                 reserve_start = (u64 *)((char *)blob +
 210                                        fdt_off_mem_rsvmap(blob));
 211                 while (1) {
 212                         *reserve_start = __cpu_to_be64(*reserve_start);
 213                         size = __cpu_to_be64(*(reserve_start + 1));
 214                         if (size) {
 215                                 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
 216                                 *reserve_start +=
 217                                         CONFIG_SYS_LPAE_SDRAM_BASE;
 218                                 *reserve_start =
 219                                         __cpu_to_be64(*reserve_start);
 220                         } else {
 221                                 break;
 222                         }
 223                         reserve_start += 2;
 224                 }
 225         }
 226
 227         ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 228 }
 229 #endif /* CONFIG_OF_BOARD_SETUP */
 230
 231 #if defined(CONFIG_DTB_RESELECT)
 232 int __weak embedded_dtb_select(void)
 233 {
 234         return 0;
 235 }
 236 #endif