board/ti/ks2_evm/board.c

   1 /*
   2  * Keystone : Board initialization
   3  *
   4  * (C) Copyright 2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include "board.h"
  12 #include <spl.h>
  13 #include <exports.h>
  14 #include <fdt_support.h>
  15 #include <asm/arch/ddr3.h>
  16 #include <asm/arch/psc_defs.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/ti-common/ti-aemif.h>
  19 #include <asm/ti-common/keystone_net.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #if defined(CONFIG_TI_AEMIF)
  24 static struct aemif_config aemif_configs[] = {
  25         {                       /* CS0 */
  26                 .mode           = AEMIF_MODE_NAND,
  27                 .wr_setup       = 0xf,
  28                 .wr_strobe      = 0x3f,
  29                 .wr_hold        = 7,
  30                 .rd_setup       = 0xf,
  31                 .rd_strobe      = 0x3f,
  32                 .rd_hold        = 7,
  33                 .turn_around    = 3,
  34                 .width          = AEMIF_WIDTH_8,
  35         },
  36 };
  37 #endif
  38
  39 int dram_init(void)
  40 {
  41         u32 ddr3_size;
  42
  43         ddr3_size = ddr3_init();
  44
  45         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  46                                     CONFIG_MAX_RAM_BANK_SIZE);
  47 #if defined(CONFIG_TI_AEMIF)
  48         aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
  49 #endif
  50
  51         if (ddr3_size)
  52                 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
  53         else
  54                 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, gd->ram_size >> 30);
  55
  56         return 0;
  57 }
  58
  59 int board_init(void)
  60 {
  61         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  62
  63         return 0;
  64 }
  65
  66 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
  67 #ifndef CONFIG_DM_ETH
  68 int get_eth_env_param(char *env_name)
  69 {
  70         char *env;
  71         int res = -1;
  72
  73         env = getenv(env_name);
  74         if (env)
  75                 res = simple_strtol(env, NULL, 0);
  76
  77         return res;
  78 }
  79
  80 int board_eth_init(bd_t *bis)
  81 {
  82         int j;
  83         int res;
  84         int port_num;
  85         char link_type_name[32];
  86
  87         if (cpu_is_k2g())
  88                 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
  89
  90         /* By default, select PA PLL clock as PA clock source */
  91 #ifndef CONFIG_SOC_K2G
  92         if (psc_enable_module(KS2_LPSC_PA))
  93                 return -1;
  94 #endif
  95         if (psc_enable_module(KS2_LPSC_CPGMAC))
  96                 return -1;
  97         if (psc_enable_module(KS2_LPSC_CRYPTO))
  98                 return -1;
  99
 100         if (cpu_is_k2e() || cpu_is_k2l())
 101                 pll_pa_clk_sel();
 102
 103         port_num = get_num_eth_ports();
 104
 105         for (j = 0; j < port_num; j++) {
 106                 sprintf(link_type_name, "sgmii%d_link_type", j);
 107                 res = get_eth_env_param(link_type_name);
 108                 if (res >= 0)
 109                         eth_priv_cfg[j].sgmii_link_type = res;
 110
 111                 keystone2_emac_initialize(&eth_priv_cfg[j]);
 112         }
 113
 114         return 0;
 115 }
 116 #endif
 117 #endif
 118
 119 #ifdef CONFIG_SPL_BUILD
 120 void spl_board_init(void)
 121 {
 122         spl_init_keystone_plls();
 123         preloader_console_init();
 124 }
 125
 126 u32 spl_boot_device(void)
 127 {
 128 #if defined(CONFIG_SPL_SPI_LOAD)
 129         return BOOT_DEVICE_SPI;
 130 #else
 131         puts("Unknown boot device\n");
 132         hang();
 133 #endif
 134 }
 135 #endif
 136
 137 #ifdef CONFIG_OF_BOARD_SETUP
 138 int ft_board_setup(void *blob, bd_t *bd)
 139 {
 140         int lpae;
 141         char *env;
 142         char *endp;
 143         int nbanks;
 144         u64 size[2];
 145         u64 start[2];
 146         int nodeoffset;
 147         u32 ddr3a_size;
 148         int unitrd_fixup = 0;
 149
 150         env = getenv("mem_lpae");
 151         lpae = env && simple_strtol(env, NULL, 0);
 152         env = getenv("uinitrd_fixup");
 153         unitrd_fixup = env && simple_strtol(env, NULL, 0);
 154
 155         ddr3a_size = 0;
 156         if (lpae) {
 157                 ddr3a_size = ddr3_get_size();
 158                 if ((ddr3a_size != 8) && (ddr3a_size != 4))
 159                         ddr3a_size = 0;
 160         }
 161
 162         nbanks = 1;
 163         start[0] = bd->bi_dram[0].start;
 164         size[0]  = bd->bi_dram[0].size;
 165
 166         /* adjust memory start address for LPAE */
 167         if (lpae) {
 168                 start[0] -= CONFIG_SYS_SDRAM_BASE;
 169                 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
 170         }
 171
 172         if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
 173                 size[1] = ((u64)ddr3a_size - 2) << 30;
 174                 start[1] = 0x880000000;
 175                 nbanks++;
 176         }
 177
 178         /* reserve memory at start of bank */
 179         env = getenv("mem_reserve_head");
 180         if (env) {
 181                 start[0] += ustrtoul(env, &endp, 0);
 182                 size[0] -= ustrtoul(env, &endp, 0);
 183         }
 184
 185         env = getenv("mem_reserve");
 186         if (env)
 187                 size[0] -= ustrtoul(env, &endp, 0);
 188
 189         fdt_fixup_memory_banks(blob, start, size, nbanks);
 190
 191         /* Fix up the initrd */
 192         if (lpae && unitrd_fixup) {
 193                 int err;
 194                 u32 *prop1, *prop2;
 195                 u64 initrd_start, initrd_end;
 196
 197                 nodeoffset = fdt_path_offset(blob, "/chosen");
 198                 if (nodeoffset >= 0) {
 199                         prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
 200                                             "linux,initrd-start", NULL);
 201                         prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
 202                                             "linux,initrd-end", NULL);
 203                         if (prop1 && prop2) {
 204                                 initrd_start = __be32_to_cpu(*prop1);
 205                                 initrd_start -= CONFIG_SYS_SDRAM_BASE;
 206                                 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
 207                                 initrd_start = __cpu_to_be64(initrd_start);
 208                                 initrd_end = __be32_to_cpu(*prop2);
 209                                 initrd_end -= CONFIG_SYS_SDRAM_BASE;
 210                                 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
 211                                 initrd_end = __cpu_to_be64(initrd_end);
 212
 213                                 err = fdt_delprop(blob, nodeoffset,
 214                                                   "linux,initrd-start");
 215                                 if (err < 0)
 216                                         puts("error deleting initrd-start\n");
 217
 218                                 err = fdt_delprop(blob, nodeoffset,
 219                                                   "linux,initrd-end");
 220                                 if (err < 0)
 221                                         puts("error deleting initrd-end\n");
 222
 223                                 err = fdt_setprop(blob, nodeoffset,
 224                                                   "linux,initrd-start",
 225                                                   &initrd_start,
 226                                                   sizeof(initrd_start));
 227                                 if (err < 0)
 228                                         puts("error adding initrd-start\n");
 229
 230                                 err = fdt_setprop(blob, nodeoffset,
 231                                                   "linux,initrd-end",
 232                                                   &initrd_end,
 233                                                   sizeof(initrd_end));
 234                                 if (err < 0)
 235                                         puts("error adding linux,initrd-end\n");
 236                         }
 237                 }
 238         }
 239
 240         return 0;
 241 }
 242
 243 void ft_board_setup_ex(void *blob, bd_t *bd)
 244 {
 245         int lpae;
 246         u64 size;
 247         char *env;
 248         u64 *reserve_start;
 249
 250         env = getenv("mem_lpae");
 251         lpae = env && simple_strtol(env, NULL, 0);
 252
 253         if (lpae) {
 254                 /*
 255                  * the initrd and other reserved memory areas are
 256                  * embedded in in the DTB itslef. fix up these addresses
 257                  * to 36 bit format
 258                  */
 259                 reserve_start = (u64 *)((char *)blob +
 260                                        fdt_off_mem_rsvmap(blob));
 261                 while (1) {
 262                         *reserve_start = __cpu_to_be64(*reserve_start);
 263                         size = __cpu_to_be64(*(reserve_start + 1));
 264                         if (size) {
 265                                 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
 266                                 *reserve_start +=
 267                                         CONFIG_SYS_LPAE_SDRAM_BASE;
 268                                 *reserve_start =
 269                                         __cpu_to_be64(*reserve_start);
 270                         } else {
 271                                 break;
 272                         }
 273                         reserve_start += 2;
 274                 }
 275         }
 276
 277         ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 278 }
 279 #endif /* CONFIG_OF_BOARD_SETUP */
 280
 281 #if defined(CONFIG_DTB_RESELECT)
 282 int __weak embedded_dtb_select(void)
 283 {
 284         return 0;
 285 }
 286 #endif