board/ti/dra7xx/evm.c

   1 /*
   2  * (C) Copyright 2013
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  *
   5  * Lokesh Vutla <lokeshvutla@ti.com>
   6  *
   7  * Based on previous work by:
   8  * Aneesh V       <aneesh@ti.com>
   9  * Steve Sakoman  <steve@sakoman.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13 #include <common.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <asm/gpio.h>
  17 #include <usb.h>
  18 #include <linux/usb/gadget.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/dra7xx_iodelay.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sata.h>
  24 #include <environment.h>
  25 #include <dwc3-uboot.h>
  26 #include <dwc3-omap-uboot.h>
  27 #include <ti-usb-phy-uboot.h>
  28
  29 #include "mux_data.h"
  30
  31 #ifdef CONFIG_DRIVER_TI_CPSW
  32 #include <cpsw.h>
  33 #endif
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 /* GPIO 7_11 */
  38 #define GPIO_DDR_VTT_EN 203
  39
  40 const struct omap_sysinfo sysinfo = {
  41         "Board: DRA7xx\n"
  42 };
  43
  44 /**
  45  * @brief board_init
  46  *
  47  * @return 0
  48  */
  49 int board_init(void)
  50 {
  51         gpmc_init();
  52         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  53
  54         return 0;
  55 }
  56
  57 int board_late_init(void)
  58 {
  59 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  60         unsigned int die_id[4] = { 0 };
  61
  62         if (omap_revision() == DRA722_ES1_0)
  63                 setenv("board_name", "dra72x");
  64         else
  65                 setenv("board_name", "dra7xx");
  66
  67         omap_die_id(die_id);
  68         usb_set_serial_num_from_die_id(die_id);
  69 #endif
  70         return 0;
  71 }
  72
  73 void set_muxconf_regs_essential(void)
  74 {
  75         do_set_mux32((*ctrl)->control_padconf_core_base,
  76                      early_padconf, ARRAY_SIZE(early_padconf));
  77 }
  78
  79 #ifdef CONFIG_IODELAY_RECALIBRATION
  80 void recalibrate_iodelay(void)
  81 {
  82         struct pad_conf_entry const *pads;
  83         struct iodelay_cfg_entry const *iodelay;
  84         int npads, niodelays;
  85
  86         switch (omap_revision()) {
  87         case DRA722_ES1_0:
  88                 pads = core_padconf_array_essential;
  89                 npads = ARRAY_SIZE(core_padconf_array_essential);
  90                 iodelay = iodelay_cfg_array;
  91                 niodelays = ARRAY_SIZE(iodelay_cfg_array);
  92                 break;
  93         case DRA752_ES1_0:
  94         case DRA752_ES1_1:
  95                 pads = dra74x_core_padconf_array;
  96                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
  97                 iodelay = dra742_es1_1_iodelay_cfg_array;
  98                 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
  99                 break;
 100         default:
 101         case DRA752_ES2_0:
 102                 pads = dra74x_core_padconf_array;
 103                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 104                 iodelay = dra742_es2_0_iodelay_cfg_array;
 105                 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
 106                 /* Setup port1 and port2 for rgmii with 'no-id' mode */
 107                 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
 108                                       RGMII1_ID_MODE_N_MASK);
 109                 break;
 110         }
 111         __recalibrate_iodelay(pads, npads, iodelay, niodelays);
 112 }
 113 #endif
 114
 115 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 116 int board_mmc_init(bd_t *bis)
 117 {
 118         omap_mmc_init(0, 0, 0, -1, -1);
 119         omap_mmc_init(1, 0, 0, -1, -1);
 120         return 0;
 121 }
 122 #endif
 123
 124 #ifdef CONFIG_USB_DWC3
 125 static struct dwc3_device usb_otg_ss1 = {
 126         .maximum_speed = USB_SPEED_SUPER,
 127         .base = DRA7_USB_OTG_SS1_BASE,
 128         .tx_fifo_resize = false,
 129         .index = 0,
 130 };
 131
 132 static struct dwc3_omap_device usb_otg_ss1_glue = {
 133         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 134         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 135         .index = 0,
 136 };
 137
 138 static struct ti_usb_phy_device usb_phy1_device = {
 139         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 140         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 141         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 142         .index = 0,
 143 };
 144
 145 static struct dwc3_device usb_otg_ss2 = {
 146         .maximum_speed = USB_SPEED_SUPER,
 147         .base = DRA7_USB_OTG_SS2_BASE,
 148         .tx_fifo_resize = false,
 149         .index = 1,
 150 };
 151
 152 static struct dwc3_omap_device usb_otg_ss2_glue = {
 153         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 154         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 155         .index = 1,
 156 };
 157
 158 static struct ti_usb_phy_device usb_phy2_device = {
 159         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 160         .index = 1,
 161 };
 162
 163 int board_usb_init(int index, enum usb_init_type init)
 164 {
 165         enable_usb_clocks(index);
 166         switch (index) {
 167         case 0:
 168                 if (init == USB_INIT_DEVICE) {
 169                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 170                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 171                 } else {
 172                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 173                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 174                 }
 175
 176                 ti_usb_phy_uboot_init(&usb_phy1_device);
 177                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 178                 dwc3_uboot_init(&usb_otg_ss1);
 179                 break;
 180         case 1:
 181                 if (init == USB_INIT_DEVICE) {
 182                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 183                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 184                 } else {
 185                         usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
 186                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 187                 }
 188
 189                 ti_usb_phy_uboot_init(&usb_phy2_device);
 190                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 191                 dwc3_uboot_init(&usb_otg_ss2);
 192                 break;
 193         default:
 194                 printf("Invalid Controller Index\n");
 195         }
 196
 197         return 0;
 198 }
 199
 200 int board_usb_cleanup(int index, enum usb_init_type init)
 201 {
 202         switch (index) {
 203         case 0:
 204         case 1:
 205                 ti_usb_phy_uboot_exit(index);
 206                 dwc3_uboot_exit(index);
 207                 dwc3_omap_uboot_exit(index);
 208                 break;
 209         default:
 210                 printf("Invalid Controller Index\n");
 211         }
 212         disable_usb_clocks(index);
 213         return 0;
 214 }
 215
 216 int usb_gadget_handle_interrupts(int index)
 217 {
 218         u32 status;
 219
 220         status = dwc3_omap_uboot_interrupt_status(index);
 221         if (status)
 222                 dwc3_uboot_handle_interrupt(index);
 223
 224         return 0;
 225 }
 226 #endif
 227
 228 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 229 int spl_start_uboot(void)
 230 {
 231         /* break into full u-boot on 'c' */
 232         if (serial_tstc() && serial_getc() == 'c')
 233                 return 1;
 234
 235 #ifdef CONFIG_SPL_ENV_SUPPORT
 236         env_init();
 237         env_relocate_spec();
 238         if (getenv_yesno("boot_os") != 1)
 239                 return 1;
 240 #endif
 241
 242         return 0;
 243 }
 244 #endif
 245
 246 #ifdef CONFIG_DRIVER_TI_CPSW
 247 extern u32 *const omap_si_rev;
 248
 249 static void cpsw_control(int enabled)
 250 {
 251         /* VTP can be added here */
 252
 253         return;
 254 }
 255
 256 static struct cpsw_slave_data cpsw_slaves[] = {
 257         {
 258                 .slave_reg_ofs  = 0x208,
 259                 .sliver_reg_ofs = 0xd80,
 260                 .phy_addr       = 2,
 261         },
 262         {
 263                 .slave_reg_ofs  = 0x308,
 264                 .sliver_reg_ofs = 0xdc0,
 265                 .phy_addr       = 3,
 266         },
 267 };
 268
 269 static struct cpsw_platform_data cpsw_data = {
 270         .mdio_base              = CPSW_MDIO_BASE,
 271         .cpsw_base              = CPSW_BASE,
 272         .mdio_div               = 0xff,
 273         .channels               = 8,
 274         .cpdma_reg_ofs          = 0x800,
 275         .slaves                 = 2,
 276         .slave_data             = cpsw_slaves,
 277         .ale_reg_ofs            = 0xd00,
 278         .ale_entries            = 1024,
 279         .host_port_reg_ofs      = 0x108,
 280         .hw_stats_reg_ofs       = 0x900,
 281         .bd_ram_ofs             = 0x2000,
 282         .mac_control            = (1 << 5),
 283         .control                = cpsw_control,
 284         .host_port_num          = 0,
 285         .version                = CPSW_CTRL_VERSION_2,
 286 };
 287
 288 int board_eth_init(bd_t *bis)
 289 {
 290         int ret;
 291         uint8_t mac_addr[6];
 292         uint32_t mac_hi, mac_lo;
 293         uint32_t ctrl_val;
 294
 295         /* try reading mac address from efuse */
 296         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 297         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 298         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 299         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 300         mac_addr[2] = mac_hi & 0xFF;
 301         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 302         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 303         mac_addr[5] = mac_lo & 0xFF;
 304
 305         if (!getenv("ethaddr")) {
 306                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 307
 308                 if (is_valid_ethaddr(mac_addr))
 309                         eth_setenv_enetaddr("ethaddr", mac_addr);
 310         }
 311
 312         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 313         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 314         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 315         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 316         mac_addr[2] = mac_hi & 0xFF;
 317         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 318         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 319         mac_addr[5] = mac_lo & 0xFF;
 320
 321         if (!getenv("eth1addr")) {
 322                 if (is_valid_ethaddr(mac_addr))
 323                         eth_setenv_enetaddr("eth1addr", mac_addr);
 324         }
 325
 326         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 327         ctrl_val |= 0x22;
 328         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 329
 330         if (*omap_si_rev == DRA722_ES1_0)
 331                 cpsw_data.active_slave = 1;
 332
 333         ret = cpsw_register(&cpsw_data);
 334         if (ret < 0)
 335                 printf("Error %d registering CPSW switch\n", ret);
 336
 337         return ret;
 338 }
 339 #endif
 340
 341 #ifdef CONFIG_BOARD_EARLY_INIT_F
 342 /* VTT regulator enable */
 343 static inline void vtt_regulator_enable(void)
 344 {
 345         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 346                 return;
 347
 348         /* Do not enable VTT for DRA722 */
 349         if (omap_revision() == DRA722_ES1_0)
 350                 return;
 351
 352         /*
 353          * EVM Rev G and later use gpio7_11 for DDR3 termination.
 354          * This is safe enough to do on older revs.
 355          */
 356         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 357         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 358 }
 359
 360 int board_early_init_f(void)
 361 {
 362         vtt_regulator_enable();
 363         return 0;
 364 }
 365 #endif