2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/mmc_host_def.h>
20 #include <asm/arch/sata.h>
21 #include <asm/arch/gpio.h>
22 #include <environment.h>
26 #ifdef CONFIG_DRIVER_TI_CPSW
30 DECLARE_GLOBAL_DATA_PTR;
32 const struct omap_sysinfo sysinfo = {
33 "Board: BeagleBoard x15\n"
36 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
37 .dmm_lisa_map_3 = 0x80740300,
41 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
43 *dmm_lisa_regs = &beagle_x15_lisa_regs;
46 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
47 .sdram_config_init = 0x61851b32,
48 .sdram_config = 0x61851b32,
49 .sdram_config2 = 0x00000000,
50 .ref_ctrl = 0x00001035,
51 .sdram_tim1 = 0xceef266b,
52 .sdram_tim2 = 0x328f7fda,
53 .sdram_tim3 = 0x027f88a8,
54 .read_idle_ctrl = 0x00050001,
55 .zq_config = 0x0007190b,
56 .temp_alert_config = 0x00000000,
57 .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
58 .emif_ddr_phy_ctlr_1 = 0x0e24400a,
59 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
60 .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
61 .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
62 .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
63 .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
64 .emif_rd_wr_lvl_rmp_win = 0x00000000,
65 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
66 .emif_rd_wr_lvl_ctl = 0x00000000,
67 .emif_rd_wr_exec_thresh = 0x00000305
70 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
102 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
103 .sdram_config_init = 0x61851b32,
104 .sdram_config = 0x61851b32,
105 .sdram_config2 = 0x00000000,
106 .ref_ctrl = 0x00001035,
107 .sdram_tim1 = 0xceef266b,
108 .sdram_tim2 = 0x328f7fda,
109 .sdram_tim3 = 0x027f88a8,
110 .read_idle_ctrl = 0x00050001,
111 .zq_config = 0x0007190b,
112 .temp_alert_config = 0x00000000,
113 .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
114 .emif_ddr_phy_ctlr_1 = 0x0e24400a,
115 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
116 .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
117 .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
118 .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
119 .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
120 .emif_rd_wr_lvl_rmp_win = 0x00000000,
121 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
122 .emif_rd_wr_lvl_ctl = 0x00000000,
123 .emif_rd_wr_exec_thresh = 0x00000305
126 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
156 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
160 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
163 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
168 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
172 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
173 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
176 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
177 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
182 struct vcores_data beagle_x15_volts = {
183 .mpu.value = VDD_MPU_DRA752,
184 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
185 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
186 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
187 .mpu.pmic = &tps659038,
189 .eve.value = VDD_EVE_DRA752,
190 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
191 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
192 .eve.addr = TPS659038_REG_ADDR_SMPS45,
193 .eve.pmic = &tps659038,
195 .gpu.value = VDD_GPU_DRA752,
196 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
197 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
198 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
199 .gpu.pmic = &tps659038,
201 .core.value = VDD_CORE_DRA752,
202 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
203 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
204 .core.addr = TPS659038_REG_ADDR_SMPS6,
205 .core.pmic = &tps659038,
207 .iva.value = VDD_IVA_DRA752,
208 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
209 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
210 .iva.addr = TPS659038_REG_ADDR_SMPS45,
211 .iva.pmic = &tps659038,
214 void hw_data_init(void)
216 *prcm = &dra7xx_prcm;
217 *dplls_data = &dra7xx_dplls;
218 *omap_vcores = &beagle_x15_volts;
219 *ctrl = &dra7xx_ctrl;
225 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
230 int board_late_init(void)
234 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
235 * This is the POWERHOLD-in-Low behavior.
237 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
241 static void do_set_mux32(u32 base,
242 struct pad_conf_entry const *array, int size)
245 struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
247 for (i = 0; i < size; i++, pad++)
248 writel(pad->val, base + pad->offset);
251 void set_muxconf_regs_essential(void)
253 do_set_mux32((*ctrl)->control_padconf_core_base,
254 core_padconf_array_essential,
255 sizeof(core_padconf_array_essential) /
256 sizeof(struct pad_conf_entry));
259 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
260 int board_mmc_init(bd_t *bis)
262 omap_mmc_init(0, 0, 0, -1, -1);
263 omap_mmc_init(1, 0, 0, -1, -1);
268 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
269 int spl_start_uboot(void)
271 /* break into full u-boot on 'c' */
272 if (serial_tstc() && serial_getc() == 'c')
275 #ifdef CONFIG_SPL_ENV_SUPPORT
278 if (getenv_yesno("boot_os") != 1)
286 #ifdef CONFIG_DRIVER_TI_CPSW
288 /* Delay value to add to calibrated value */
289 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
290 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
291 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
292 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
293 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
294 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
295 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
296 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
297 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
298 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
300 static void cpsw_control(int enabled)
302 /* VTP can be added here */
305 static struct cpsw_slave_data cpsw_slaves[] = {
307 .slave_reg_ofs = 0x208,
308 .sliver_reg_ofs = 0xd80,
312 .slave_reg_ofs = 0x308,
313 .sliver_reg_ofs = 0xdc0,
318 static struct cpsw_platform_data cpsw_data = {
319 .mdio_base = CPSW_MDIO_BASE,
320 .cpsw_base = CPSW_BASE,
323 .cpdma_reg_ofs = 0x800,
325 .slave_data = cpsw_slaves,
326 .ale_reg_ofs = 0xd00,
328 .host_port_reg_ofs = 0x108,
329 .hw_stats_reg_ofs = 0x900,
330 .bd_ram_ofs = 0x2000,
331 .mac_control = (1 << 5),
332 .control = cpsw_control,
334 .version = CPSW_CTRL_VERSION_2,
337 int board_eth_init(bd_t *bis)
341 uint32_t mac_hi, mac_lo;
344 /* try reading mac address from efuse */
345 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
346 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
347 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
348 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
349 mac_addr[2] = mac_hi & 0xFF;
350 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
351 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
352 mac_addr[5] = mac_lo & 0xFF;
354 if (!getenv("ethaddr")) {
355 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
357 if (is_valid_ether_addr(mac_addr))
358 eth_setenv_enetaddr("ethaddr", mac_addr);
361 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
362 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
363 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
364 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
365 mac_addr[2] = mac_hi & 0xFF;
366 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
367 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
368 mac_addr[5] = mac_lo & 0xFF;
370 if (!getenv("eth1addr")) {
371 if (is_valid_ether_addr(mac_addr))
372 eth_setenv_enetaddr("eth1addr", mac_addr);
375 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
377 writel(ctrl_val, (*ctrl)->control_core_control_io1);
379 ret = cpsw_register(&cpsw_data);
381 printf("Error %d registering CPSW switch\n", ret);
387 #ifdef CONFIG_USB_XHCI_OMAP
388 int board_usb_init(int index, enum usb_init_type init)
390 setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
391 OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);