2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/mmc_host_def.h>
20 #include <asm/arch/sata.h>
21 #include <asm/arch/gpio.h>
22 #include <environment.h>
26 #ifdef CONFIG_DRIVER_TI_CPSW
30 DECLARE_GLOBAL_DATA_PTR;
32 const struct omap_sysinfo sysinfo = {
33 "Board: BeagleBoard x15\n"
36 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
37 .dmm_lisa_map_3 = 0x80740300,
41 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
43 *dmm_lisa_regs = &beagle_x15_lisa_regs;
46 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
47 .sdram_config_init = 0x61851b32,
48 .sdram_config = 0x61851b32,
49 .sdram_config2 = 0x00000000,
50 .ref_ctrl = 0x000040F1,
51 .ref_ctrl_final = 0x00001035,
52 .sdram_tim1 = 0xceef266b,
53 .sdram_tim2 = 0x328f7fda,
54 .sdram_tim3 = 0x027f88a8,
55 .read_idle_ctrl = 0x00050001,
56 .zq_config = 0x0007190b,
57 .temp_alert_config = 0x00000000,
58 .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
59 .emif_ddr_phy_ctlr_1 = 0x0e24400a,
60 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
61 .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
62 .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
63 .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
64 .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
65 .emif_rd_wr_lvl_rmp_win = 0x00000000,
66 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
67 .emif_rd_wr_lvl_ctl = 0x00000000,
68 .emif_rd_wr_exec_thresh = 0x00000305
71 /* Ext phy ctrl regs 1-35 */
72 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
109 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
110 .sdram_config_init = 0x61851b32,
111 .sdram_config = 0x61851b32,
112 .sdram_config2 = 0x00000000,
113 .ref_ctrl = 0x000040F1,
114 .ref_ctrl_final = 0x00001035,
115 .sdram_tim1 = 0xceef266b,
116 .sdram_tim2 = 0x328f7fda,
117 .sdram_tim3 = 0x027f88a8,
118 .read_idle_ctrl = 0x00050001,
119 .zq_config = 0x0007190b,
120 .temp_alert_config = 0x00000000,
121 .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
122 .emif_ddr_phy_ctlr_1 = 0x0e24400a,
123 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
124 .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
125 .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
126 .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
127 .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
128 .emif_rd_wr_lvl_rmp_win = 0x00000000,
129 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
130 .emif_rd_wr_lvl_ctl = 0x00000000,
131 .emif_rd_wr_exec_thresh = 0x00000305
134 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
169 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
173 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
176 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
181 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
185 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
186 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
189 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
190 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
195 struct vcores_data beagle_x15_volts = {
196 .mpu.value = VDD_MPU_DRA752,
197 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
198 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
199 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
200 .mpu.pmic = &tps659038,
202 .eve.value = VDD_EVE_DRA752,
203 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
204 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
205 .eve.addr = TPS659038_REG_ADDR_SMPS45,
206 .eve.pmic = &tps659038,
208 .gpu.value = VDD_GPU_DRA752,
209 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
210 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
211 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
212 .gpu.pmic = &tps659038,
214 .core.value = VDD_CORE_DRA752,
215 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
216 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
217 .core.addr = TPS659038_REG_ADDR_SMPS6,
218 .core.pmic = &tps659038,
220 .iva.value = VDD_IVA_DRA752,
221 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
222 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
223 .iva.addr = TPS659038_REG_ADDR_SMPS45,
224 .iva.pmic = &tps659038,
227 void hw_data_init(void)
229 *prcm = &dra7xx_prcm;
230 *dplls_data = &dra7xx_dplls;
231 *omap_vcores = &beagle_x15_volts;
232 *ctrl = &dra7xx_ctrl;
238 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
243 int board_late_init(void)
247 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
248 * This is the POWERHOLD-in-Low behavior.
250 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
254 static void do_set_mux32(u32 base,
255 struct pad_conf_entry const *array, int size)
258 struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
260 for (i = 0; i < size; i++, pad++)
261 writel(pad->val, base + pad->offset);
264 void set_muxconf_regs_essential(void)
266 do_set_mux32((*ctrl)->control_padconf_core_base,
267 core_padconf_array_essential,
268 sizeof(core_padconf_array_essential) /
269 sizeof(struct pad_conf_entry));
272 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
273 int board_mmc_init(bd_t *bis)
275 omap_mmc_init(0, 0, 0, -1, -1);
276 omap_mmc_init(1, 0, 0, -1, -1);
281 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
282 int spl_start_uboot(void)
284 /* break into full u-boot on 'c' */
285 if (serial_tstc() && serial_getc() == 'c')
288 #ifdef CONFIG_SPL_ENV_SUPPORT
291 if (getenv_yesno("boot_os") != 1)
299 #ifdef CONFIG_DRIVER_TI_CPSW
301 /* Delay value to add to calibrated value */
302 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
303 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
304 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
305 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
306 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
307 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
308 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
309 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
310 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
311 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
313 static void cpsw_control(int enabled)
315 /* VTP can be added here */
318 static struct cpsw_slave_data cpsw_slaves[] = {
320 .slave_reg_ofs = 0x208,
321 .sliver_reg_ofs = 0xd80,
325 .slave_reg_ofs = 0x308,
326 .sliver_reg_ofs = 0xdc0,
331 static struct cpsw_platform_data cpsw_data = {
332 .mdio_base = CPSW_MDIO_BASE,
333 .cpsw_base = CPSW_BASE,
336 .cpdma_reg_ofs = 0x800,
338 .slave_data = cpsw_slaves,
339 .ale_reg_ofs = 0xd00,
341 .host_port_reg_ofs = 0x108,
342 .hw_stats_reg_ofs = 0x900,
343 .bd_ram_ofs = 0x2000,
344 .mac_control = (1 << 5),
345 .control = cpsw_control,
347 .version = CPSW_CTRL_VERSION_2,
350 int board_eth_init(bd_t *bis)
354 uint32_t mac_hi, mac_lo;
357 /* try reading mac address from efuse */
358 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
359 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
360 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
361 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
362 mac_addr[2] = mac_hi & 0xFF;
363 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
364 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
365 mac_addr[5] = mac_lo & 0xFF;
367 if (!getenv("ethaddr")) {
368 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
370 if (is_valid_ethaddr(mac_addr))
371 eth_setenv_enetaddr("ethaddr", mac_addr);
374 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
375 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
376 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
377 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
378 mac_addr[2] = mac_hi & 0xFF;
379 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
380 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
381 mac_addr[5] = mac_lo & 0xFF;
383 if (!getenv("eth1addr")) {
384 if (is_valid_ethaddr(mac_addr))
385 eth_setenv_enetaddr("eth1addr", mac_addr);
388 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
390 writel(ctrl_val, (*ctrl)->control_core_control_io1);
392 ret = cpsw_register(&cpsw_data);
394 printf("Error %d registering CPSW switch\n", ret);