1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Felipe Balbi <balbi@ti.com>
7 * Based on board/ti/dra7xx/evm.c
14 #include <asm/omap_common.h>
15 #include <asm/omap_sec_common.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/dra7xx_iodelay.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sata.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/omap.h>
26 #include <environment.h>
28 #include <linux/usb/gadget.h>
29 #include <dwc3-uboot.h>
30 #include <dwc3-omap-uboot.h>
31 #include <ti-usb-phy-uboot.h>
34 #include "../common/board_detect.h"
37 #define board_is_x15() board_ti_is("BBRDX15_")
38 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
39 !strncmp("B.10", board_ti_get_rev(), 3))
40 #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
41 !strncmp("C.00", board_ti_get_rev(), 3))
42 #define board_is_am572x_evm() board_ti_is("AM572PM_")
43 #define board_is_am572x_evm_reva3() \
44 (board_ti_is("AM572PM_") && \
45 !strncmp("A.30", board_ti_get_rev(), 3))
46 #define board_is_am574x_idk() board_ti_is("AM574IDK")
47 #define board_is_am572x_idk() board_ti_is("AM572IDK")
48 #define board_is_am571x_idk() board_ti_is("AM571IDK")
50 #ifdef CONFIG_DRIVER_TI_CPSW
54 DECLARE_GLOBAL_DATA_PTR;
56 #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
58 #define GPIO_DDR_VTT_EN 203
60 /* Touch screen controller to identify the LCD */
61 #define OSD_TS_FT_BUS_ADDRESS 0
62 #define OSD_TS_FT_CHIP_ADDRESS 0x38
63 #define OSD_TS_FT_REG_ID 0xA3
65 * Touchscreen IDs for various OSD panels
66 * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
68 /* Used on newer osd101t2587 Panels */
69 #define OSD_TS_FT_ID_5x46 0x54
70 /* Used on older osd101t2045 Panels */
71 #define OSD_TS_FT_ID_5606 0x08
73 #define SYSINFO_BOARD_NAME_MAX_LEN 45
75 #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
76 #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
78 const struct omap_sysinfo sysinfo = {
79 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
82 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
83 .dmm_lisa_map_3 = 0x80740300,
87 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
88 .dmm_lisa_map_3 = 0x80640100,
92 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
93 .dmm_lisa_map_2 = 0xc0600200,
94 .dmm_lisa_map_3 = 0x80600100,
98 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
100 if (board_is_am571x_idk())
101 *dmm_lisa_regs = &am571x_idk_lisa_regs;
102 else if (board_is_am574x_idk())
103 *dmm_lisa_regs = &am574x_idk_lisa_regs;
105 *dmm_lisa_regs = &beagle_x15_lisa_regs;
108 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
109 .sdram_config_init = 0x61851b32,
110 .sdram_config = 0x61851b32,
111 .sdram_config2 = 0x08000000,
112 .ref_ctrl = 0x000040F1,
113 .ref_ctrl_final = 0x00001035,
114 .sdram_tim1 = 0xcccf36ab,
115 .sdram_tim2 = 0x308f7fda,
116 .sdram_tim3 = 0x409f88a8,
117 .read_idle_ctrl = 0x00050000,
118 .zq_config = 0x5007190b,
119 .temp_alert_config = 0x00000000,
120 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
121 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
122 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
123 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
124 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
125 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
126 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
127 .emif_rd_wr_lvl_rmp_win = 0x00000000,
128 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
129 .emif_rd_wr_lvl_ctl = 0x00000000,
130 .emif_rd_wr_exec_thresh = 0x00000305
133 /* Ext phy ctrl regs 1-35 */
134 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
172 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
173 .sdram_config_init = 0x61851b32,
174 .sdram_config = 0x61851b32,
175 .sdram_config2 = 0x08000000,
176 .ref_ctrl = 0x000040F1,
177 .ref_ctrl_final = 0x00001035,
178 .sdram_tim1 = 0xcccf36b3,
179 .sdram_tim2 = 0x308f7fda,
180 .sdram_tim3 = 0x407f88a8,
181 .read_idle_ctrl = 0x00050000,
182 .zq_config = 0x5007190b,
183 .temp_alert_config = 0x00000000,
184 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
185 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
186 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
187 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
188 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
189 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
190 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
191 .emif_rd_wr_lvl_rmp_win = 0x00000000,
192 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
193 .emif_rd_wr_lvl_ctl = 0x00000000,
194 .emif_rd_wr_exec_thresh = 0x00000305
197 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
235 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
236 .sdram_config_init = 0x61863332,
237 .sdram_config = 0x61863332,
238 .sdram_config2 = 0x08000000,
239 .ref_ctrl = 0x0000514d,
240 .ref_ctrl_final = 0x0000144a,
241 .sdram_tim1 = 0xd333887c,
242 .sdram_tim2 = 0x30b37fe3,
243 .sdram_tim3 = 0x409f8ad8,
244 .read_idle_ctrl = 0x00050000,
245 .zq_config = 0x5007190b,
246 .temp_alert_config = 0x00000000,
247 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
248 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
249 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
250 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
251 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
252 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
253 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
254 .emif_rd_wr_lvl_rmp_win = 0x00000000,
255 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
256 .emif_rd_wr_lvl_ctl = 0x00000000,
257 .emif_rd_wr_exec_thresh = 0x00000305
260 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
261 .sdram_config_init = 0x61863332,
262 .sdram_config = 0x61863332,
263 .sdram_config2 = 0x08000000,
264 .ref_ctrl = 0x0000514d,
265 .ref_ctrl_final = 0x0000144a,
266 .sdram_tim1 = 0xd333887c,
267 .sdram_tim2 = 0x30b37fe3,
268 .sdram_tim3 = 0x409f8ad8,
269 .read_idle_ctrl = 0x00050000,
270 .zq_config = 0x5007190b,
271 .temp_alert_config = 0x00000000,
272 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
273 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
274 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
275 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
276 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
277 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
278 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
279 .emif_rd_wr_lvl_rmp_win = 0x00000000,
280 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
281 .emif_rd_wr_lvl_ctl = 0x00000000,
282 .emif_rd_wr_exec_thresh = 0x00000305,
283 .emif_ecc_ctrl_reg = 0xD0000001,
284 .emif_ecc_address_range_1 = 0x3FFF0000,
285 .emif_ecc_address_range_2 = 0x00000000
288 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
292 if (board_is_am571x_idk())
293 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
294 else if (board_is_am574x_idk())
295 *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
297 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
300 if (board_is_am574x_idk())
301 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
303 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
308 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
312 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
313 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
316 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
317 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
322 struct vcores_data beagle_x15_volts = {
323 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
324 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
325 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
326 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
327 .mpu.pmic = &tps659038,
328 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
330 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
331 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
332 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
333 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
334 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
335 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
336 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
337 .eve.addr = TPS659038_REG_ADDR_SMPS45,
338 .eve.pmic = &tps659038,
339 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
341 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
342 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
343 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
344 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
345 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
346 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
347 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
348 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
349 .gpu.pmic = &tps659038,
350 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
352 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
353 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
354 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
355 .core.addr = TPS659038_REG_ADDR_SMPS6,
356 .core.pmic = &tps659038,
358 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
359 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
360 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
361 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
362 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
363 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
364 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
365 .iva.addr = TPS659038_REG_ADDR_SMPS45,
366 .iva.pmic = &tps659038,
367 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
370 struct vcores_data am572x_idk_volts = {
371 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
372 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
373 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
374 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
375 .mpu.pmic = &tps659038,
376 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
378 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
379 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
380 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
381 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
382 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
383 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
384 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
385 .eve.addr = TPS659038_REG_ADDR_SMPS45,
386 .eve.pmic = &tps659038,
387 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
389 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
390 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
391 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
392 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
393 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
394 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
395 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
396 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
397 .gpu.pmic = &tps659038,
398 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
400 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
401 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
402 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
403 .core.addr = TPS659038_REG_ADDR_SMPS7,
404 .core.pmic = &tps659038,
406 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
407 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
408 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
409 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
410 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
411 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
412 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
413 .iva.addr = TPS659038_REG_ADDR_SMPS8,
414 .iva.pmic = &tps659038,
415 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
418 struct vcores_data am571x_idk_volts = {
419 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
420 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
421 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
422 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
423 .mpu.pmic = &tps659038,
424 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
426 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
427 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
428 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
429 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
430 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
431 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
432 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
433 .eve.addr = TPS659038_REG_ADDR_SMPS45,
434 .eve.pmic = &tps659038,
435 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
437 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
438 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
439 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
440 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
441 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
442 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
443 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
444 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
445 .gpu.pmic = &tps659038,
446 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
448 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
449 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
450 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
451 .core.addr = TPS659038_REG_ADDR_SMPS7,
452 .core.pmic = &tps659038,
454 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
455 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
456 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
457 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
458 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
459 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
460 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
461 .iva.addr = TPS659038_REG_ADDR_SMPS45,
462 .iva.pmic = &tps659038,
463 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
466 int get_voltrail_opp(int rail_offset)
470 switch (rail_offset) {
481 opp = DRA7_DSPEVE_OPP;
494 #ifdef CONFIG_SPL_BUILD
495 /* No env to setup for SPL */
496 static inline void setup_board_eeprom_env(void) { }
498 /* Override function to read eeprom information */
499 void do_board_detect(void)
503 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
504 CONFIG_EEPROM_CHIP_ADDRESS);
506 printf("ti_i2c_eeprom_init failed %d\n", rc);
509 #else /* CONFIG_SPL_BUILD */
511 /* Override function to read eeprom information: actual i2c read done by SPL*/
512 void do_board_detect(void)
517 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
518 CONFIG_EEPROM_CHIP_ADDRESS);
520 printf("ti_i2c_eeprom_init failed %d\n", rc);
523 bname = "BeagleBoard X15";
524 else if (board_is_am572x_evm())
525 bname = "AM572x EVM";
526 else if (board_is_am574x_idk())
527 bname = "AM574x IDK";
528 else if (board_is_am572x_idk())
529 bname = "AM572x IDK";
530 else if (board_is_am571x_idk())
531 bname = "AM571x IDK";
534 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
535 "Board: %s REV %s\n", bname, board_ti_get_rev());
538 static void setup_board_eeprom_env(void)
540 char *name = "beagle_x15";
543 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
544 CONFIG_EEPROM_CHIP_ADDRESS);
548 if (board_is_x15()) {
549 if (board_is_x15_revb1())
550 name = "beagle_x15_revb1";
551 else if (board_is_x15_revc())
552 name = "beagle_x15_revc";
555 } else if (board_is_am572x_evm()) {
556 if (board_is_am572x_evm_reva3())
557 name = "am57xx_evm_reva3";
560 } else if (board_is_am574x_idk()) {
562 } else if (board_is_am572x_idk()) {
564 } else if (board_is_am571x_idk()) {
567 printf("Unidentified board claims %s in eeprom header\n",
568 board_ti_get_name());
572 set_board_info_env(name);
575 #endif /* CONFIG_SPL_BUILD */
577 void vcores_init(void)
579 if (board_is_am572x_idk() || board_is_am574x_idk())
580 *omap_vcores = &am572x_idk_volts;
581 else if (board_is_am571x_idk())
582 *omap_vcores = &am571x_idk_volts;
584 *omap_vcores = &beagle_x15_volts;
587 void hw_data_init(void)
589 *prcm = &dra7xx_prcm;
591 *dplls_data = &dra72x_dplls;
592 else if (is_dra76x())
593 *dplls_data = &dra76x_dplls;
595 *dplls_data = &dra7xx_dplls;
596 *ctrl = &dra7xx_ctrl;
599 bool am571x_idk_needs_lcd(void)
603 gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
604 if (gpio_get_value(GPIO_ETH_LCD))
609 gpio_free(GPIO_ETH_LCD);
617 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
622 void am57x_idk_lcd_detect(void)
625 char *idk_lcd = "no";
628 /* Only valid for IDKs */
629 if (board_is_x15() || board_is_am572x_evm())
632 /* Only AM571x IDK has gpio control detect.. so check that */
633 if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
636 r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
638 printf("%s: Failed to set bus address to %d: %d\n",
639 __func__, OSD_TS_FT_BUS_ADDRESS, r);
642 r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
644 /* AM572x IDK has no explicit settings for optional LCD kit */
645 if (board_is_am571x_idk()) {
646 printf("%s: Touch screen detect failed: %d!\n",
653 r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
655 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
656 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
657 OSD_TS_FT_REG_ID, r);
662 case OSD_TS_FT_ID_5606:
663 idk_lcd = "osd101t2045";
665 case OSD_TS_FT_ID_5x46:
666 idk_lcd = "osd101t2587";
669 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
671 /* we will let default be "no lcd" */
674 env_set("idk_lcd", idk_lcd);
678 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
679 static int device_okay(const char *path)
683 node = fdt_path_offset(gd->fdt_blob, path);
687 return fdtdec_get_is_enabled(gd->fdt_blob, node);
691 int board_late_init(void)
693 setup_board_eeprom_env();
697 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
698 * This is the POWERHOLD-in-Low behavior.
700 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
703 * Default FIT boot on HS devices. Non FIT images are not allowed
706 if (get_device_type() == HS_DEVICE)
707 env_set("boot_fit", "1");
710 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
711 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
712 * PMIC Power off. So to be on the safer side set it back
713 * to POWERHOLD mode irrespective of the current state.
715 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
717 val = val | TPS65903X_PAD2_POWERHOLD_MASK;
718 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
721 omap_die_id_serial();
722 omap_set_fastboot_vars();
724 am57x_idk_lcd_detect();
726 #if !defined(CONFIG_SPL_BUILD)
727 board_ti_set_ethaddr(2);
730 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
731 if (device_okay("/ocp/omap_dwc3_1@48880000"))
732 enable_usb_clocks(0);
733 if (device_okay("/ocp/omap_dwc3_2@488c0000"))
734 enable_usb_clocks(1);
739 void set_muxconf_regs(void)
741 do_set_mux32((*ctrl)->control_padconf_core_base,
742 early_padconf, ARRAY_SIZE(early_padconf));
745 #ifdef CONFIG_IODELAY_RECALIBRATION
746 void recalibrate_iodelay(void)
748 const struct pad_conf_entry *pconf;
749 const struct iodelay_cfg_entry *iod, *delta_iod;
750 int pconf_sz, iod_sz, delta_iod_sz = 0;
753 if (board_is_am572x_idk()) {
754 pconf = core_padconf_array_essential_am572x_idk;
755 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
756 iod = iodelay_cfg_array_am572x_idk;
757 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
758 } else if (board_is_am574x_idk()) {
759 pconf = core_padconf_array_essential_am574x_idk;
760 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
761 iod = iodelay_cfg_array_am574x_idk;
762 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
763 } else if (board_is_am571x_idk()) {
764 pconf = core_padconf_array_essential_am571x_idk;
765 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
766 iod = iodelay_cfg_array_am571x_idk;
767 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
769 /* Common for X15/GPEVM */
770 pconf = core_padconf_array_essential_x15;
771 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
772 /* There never was an SR1.0 X15.. So.. */
773 if (omap_revision() == DRA752_ES1_1) {
774 iod = iodelay_cfg_array_x15_sr1_1;
775 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
777 /* Since full production should switch to SR2.0 */
778 iod = iodelay_cfg_array_x15_sr2_0;
779 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
783 /* Setup I/O isolation */
784 ret = __recalibrate_iodelay_start();
788 /* Do the muxing here */
789 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
791 /* Now do the weird minor deltas that should be safe */
792 if (board_is_x15() || board_is_am572x_evm()) {
793 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
794 board_is_x15_revc()) {
795 pconf = core_padconf_array_delta_x15_sr2_0;
796 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
798 pconf = core_padconf_array_delta_x15_sr1_1;
799 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
801 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
804 if (board_is_am571x_idk()) {
805 if (am571x_idk_needs_lcd()) {
806 pconf = core_padconf_array_vout_am571x_idk;
807 pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
808 delta_iod = iodelay_cfg_array_am571x_idk_4port;
809 delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
812 pconf = core_padconf_array_icss1eth_am571x_idk;
813 pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
815 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
818 /* Setup IOdelay configuration */
819 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
821 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
825 /* Closeup.. remove isolation */
826 __recalibrate_iodelay_end(ret);
830 #if defined(CONFIG_MMC)
831 int board_mmc_init(bd_t *bis)
833 omap_mmc_init(0, 0, 0, -1, -1);
834 omap_mmc_init(1, 0, 0, -1, -1);
838 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
840 .unsupported_caps = MMC_CAP(MMC_HS_200) |
842 .max_freq = 96000000,
845 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
847 .unsupported_caps = MMC_CAP(MMC_HS_200) |
848 MMC_CAP(UHS_SDR104) |
850 .max_freq = 48000000,
853 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
855 switch (omap_revision()) {
858 if (addr == OMAP_HSMMC1_BASE)
859 return &am57x_es1_1_mmc1_fixups;
861 return &am57x_es1_1_mmc23_fixups;
868 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
869 int spl_start_uboot(void)
871 /* break into full u-boot on 'c' */
872 if (serial_tstc() && serial_getc() == 'c')
875 #ifdef CONFIG_SPL_ENV_SUPPORT
878 if (env_get_yesno("boot_os") != 1)
886 #ifdef CONFIG_DRIVER_TI_CPSW
888 /* Delay value to add to calibrated value */
889 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
890 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
891 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
892 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
893 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
894 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
895 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
896 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
897 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
898 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
900 static void cpsw_control(int enabled)
902 /* VTP can be added here */
905 static struct cpsw_slave_data cpsw_slaves[] = {
907 .slave_reg_ofs = 0x208,
908 .sliver_reg_ofs = 0xd80,
912 .slave_reg_ofs = 0x308,
913 .sliver_reg_ofs = 0xdc0,
918 static struct cpsw_platform_data cpsw_data = {
919 .mdio_base = CPSW_MDIO_BASE,
920 .cpsw_base = CPSW_BASE,
923 .cpdma_reg_ofs = 0x800,
925 .slave_data = cpsw_slaves,
926 .ale_reg_ofs = 0xd00,
928 .host_port_reg_ofs = 0x108,
929 .hw_stats_reg_ofs = 0x900,
930 .bd_ram_ofs = 0x2000,
931 .mac_control = (1 << 5),
932 .control = cpsw_control,
934 .version = CPSW_CTRL_VERSION_2,
937 static u64 mac_to_u64(u8 mac[6])
942 for (i = 0; i < 6; i++) {
950 static void u64_to_mac(u64 addr, u8 mac[6])
960 int board_eth_init(bd_t *bis)
964 uint32_t mac_hi, mac_lo;
968 u8 mac_addr1[6], mac_addr2[6];
971 /* try reading mac address from efuse */
972 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
973 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
974 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
975 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
976 mac_addr[2] = mac_hi & 0xFF;
977 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
978 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
979 mac_addr[5] = mac_lo & 0xFF;
981 if (!env_get("ethaddr")) {
982 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
984 if (is_valid_ethaddr(mac_addr))
985 eth_env_set_enetaddr("ethaddr", mac_addr);
988 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
989 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
990 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
991 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
992 mac_addr[2] = mac_hi & 0xFF;
993 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
994 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
995 mac_addr[5] = mac_lo & 0xFF;
997 if (!env_get("eth1addr")) {
998 if (is_valid_ethaddr(mac_addr))
999 eth_env_set_enetaddr("eth1addr", mac_addr);
1002 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1004 writel(ctrl_val, (*ctrl)->control_core_control_io1);
1006 /* The phy address for the AM57xx IDK are different than x15 */
1007 if (board_is_am572x_idk() || board_is_am571x_idk() ||
1008 board_is_am574x_idk()) {
1009 cpsw_data.slave_data[0].phy_addr = 0;
1010 cpsw_data.slave_data[1].phy_addr = 1;
1013 ret = cpsw_register(&cpsw_data);
1015 printf("Error %d registering CPSW switch\n", ret);
1018 * Export any Ethernet MAC addresses from EEPROM.
1019 * On AM57xx the 2 MAC addresses define the address range
1021 board_ti_get_eth_mac_addr(0, mac_addr1);
1022 board_ti_get_eth_mac_addr(1, mac_addr2);
1024 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1025 mac1 = mac_to_u64(mac_addr1);
1026 mac2 = mac_to_u64(mac_addr2);
1028 /* must contain an address range */
1029 num_macs = mac2 - mac1 + 1;
1030 /* <= 50 to protect against user programming error */
1031 if (num_macs > 0 && num_macs <= 50) {
1032 for (i = 0; i < num_macs; i++) {
1033 u64_to_mac(mac1 + i, mac_addr);
1034 if (is_valid_ethaddr(mac_addr)) {
1035 eth_env_set_enetaddr_by_index("eth",
1047 #ifdef CONFIG_BOARD_EARLY_INIT_F
1048 /* VTT regulator enable */
1049 static inline void vtt_regulator_enable(void)
1051 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1054 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1055 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1058 int board_early_init_f(void)
1060 vtt_regulator_enable();
1065 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1066 int ft_board_setup(void *blob, bd_t *bd)
1068 ft_cpu_setup(blob, bd);
1074 #ifdef CONFIG_SPL_LOAD_FIT
1075 int board_fit_config_name_match(const char *name)
1077 if (board_is_x15()) {
1078 if (board_is_x15_revb1()) {
1079 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1081 } else if (board_is_x15_revc()) {
1082 if (!strcmp(name, "am57xx-beagle-x15-revc"))
1084 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1087 } else if (board_is_am572x_evm() &&
1088 !strcmp(name, "am57xx-beagle-x15")) {
1090 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1092 } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1094 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1102 #ifdef CONFIG_TI_SECURE_DEVICE
1103 void board_fit_image_post_process(void **p_image, size_t *p_size)
1105 secure_boot_verify_image(p_image, p_size);
1108 void board_tee_image_process(ulong tee_image, size_t tee_size)
1110 secure_tee_install((u32)tee_image);
1113 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1114 int fastboot_set_reboot_flag(void)
1116 printf("Setting reboot to fastboot flag ...\n");
1117 env_set("dofastboot", "1");
1123 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);