board/ti/am57xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   4  *
   5  * Author: Felipe Balbi <balbi@ti.com>
   6  *
   7  * Based on board/ti/dra7xx/evm.c
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <fdt_support.h>
  13 #include <init.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <serial.h>
  17 #include <usb.h>
  18 #include <asm/omap_common.h>
  19 #include <asm/omap_sec_common.h>
  20 #include <asm/emif.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/dra7xx_iodelay.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/arch/mmc_host_def.h>
  27 #include <asm/arch/sata.h>
  28 #include <asm/arch/gpio.h>
  29 #include <asm/arch/omap.h>
  30 #include <usb.h>
  31 #include <linux/usb/gadget.h>
  32 #include <dwc3-uboot.h>
  33 #include <dwc3-omap-uboot.h>
  34 #include <ti-usb-phy-uboot.h>
  35 #include <mmc.h>
  36 #include <dm/uclass.h>
  37
  38 #include "../common/board_detect.h"
  39 #include "mux_data.h"
  40
  41 #define board_is_x15()          board_ti_is("BBRDX15_")
  42 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  43                                  !strncmp("B.10", board_ti_get_rev(), 3))
  44 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  45                                  !strncmp("C.00", board_ti_get_rev(), 3))
  46 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  47 #define board_is_am572x_evm_reva3()     \
  48                                 (board_ti_is("AM572PM_") && \
  49                                  !strncmp("A.30", board_ti_get_rev(), 3))
  50 #define board_is_am574x_idk()   board_ti_is("AM574IDK")
  51 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  52 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  53
  54 #ifdef CONFIG_DRIVER_TI_CPSW
  55 #include <cpsw.h>
  56 #endif
  57
  58 DECLARE_GLOBAL_DATA_PTR;
  59
  60 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  61 /* GPIO 7_11 */
  62 #define GPIO_DDR_VTT_EN 203
  63
  64 /* Touch screen controller to identify the LCD */
  65 #define OSD_TS_FT_BUS_ADDRESS   0
  66 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  67 #define OSD_TS_FT_REG_ID        0xA3
  68 /*
  69  * Touchscreen IDs for various OSD panels
  70  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  71  */
  72 /* Used on newer osd101t2587 Panels */
  73 #define OSD_TS_FT_ID_5x46       0x54
  74 /* Used on older osd101t2045 Panels */
  75 #define OSD_TS_FT_ID_5606       0x08
  76
  77 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  78
  79 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  80 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  81
  82 const struct omap_sysinfo sysinfo = {
  83         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  84 };
  85
  86 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  87         .dmm_lisa_map_3 = 0x80740300,
  88         .is_ma_present  = 0x1
  89 };
  90
  91 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  92         .dmm_lisa_map_3 = 0x80640100,
  93         .is_ma_present  = 0x1
  94 };
  95
  96 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
  97         .dmm_lisa_map_2 = 0xc0600200,
  98         .dmm_lisa_map_3 = 0x80600100,
  99         .is_ma_present  = 0x1
 100 };
 101
 102 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 103 {
 104         if (board_is_am571x_idk())
 105                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
 106         else if (board_is_am574x_idk())
 107                 *dmm_lisa_regs = &am574x_idk_lisa_regs;
 108         else
 109                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
 110 }
 111
 112 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 113         .sdram_config_init              = 0x61851b32,
 114         .sdram_config                   = 0x61851b32,
 115         .sdram_config2                  = 0x08000000,
 116         .ref_ctrl                       = 0x000040F1,
 117         .ref_ctrl_final                 = 0x00001035,
 118         .sdram_tim1                     = 0xcccf36ab,
 119         .sdram_tim2                     = 0x308f7fda,
 120         .sdram_tim3                     = 0x409f88a8,
 121         .read_idle_ctrl                 = 0x00050000,
 122         .zq_config                      = 0x5007190b,
 123         .temp_alert_config              = 0x00000000,
 124         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 125         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 126         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 127         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 128         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 129         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 130         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 131         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 132         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 133         .emif_rd_wr_lvl_ctl             = 0x00000000,
 134         .emif_rd_wr_exec_thresh         = 0x00000305
 135 };
 136
 137 /* Ext phy ctrl regs 1-35 */
 138 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 139         0x10040100,
 140         0x00910091,
 141         0x00950095,
 142         0x009B009B,
 143         0x009E009E,
 144         0x00980098,
 145         0x00340034,
 146         0x00350035,
 147         0x00340034,
 148         0x00310031,
 149         0x00340034,
 150         0x007F007F,
 151         0x007F007F,
 152         0x007F007F,
 153         0x007F007F,
 154         0x007F007F,
 155         0x00480048,
 156         0x004A004A,
 157         0x00520052,
 158         0x00550055,
 159         0x00500050,
 160         0x00000000,
 161         0x00600020,
 162         0x40011080,
 163         0x08102040,
 164         0x0,
 165         0x0,
 166         0x0,
 167         0x0,
 168         0x0,
 169         0x0,
 170         0x0,
 171         0x0,
 172         0x0,
 173         0x0
 174 };
 175
 176 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 177         .sdram_config_init              = 0x61851b32,
 178         .sdram_config                   = 0x61851b32,
 179         .sdram_config2                  = 0x08000000,
 180         .ref_ctrl                       = 0x000040F1,
 181         .ref_ctrl_final                 = 0x00001035,
 182         .sdram_tim1                     = 0xcccf36b3,
 183         .sdram_tim2                     = 0x308f7fda,
 184         .sdram_tim3                     = 0x407f88a8,
 185         .read_idle_ctrl                 = 0x00050000,
 186         .zq_config                      = 0x5007190b,
 187         .temp_alert_config              = 0x00000000,
 188         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 189         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 190         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 191         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 192         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 193         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 194         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 195         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 196         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 197         .emif_rd_wr_lvl_ctl             = 0x00000000,
 198         .emif_rd_wr_exec_thresh         = 0x00000305
 199 };
 200
 201 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 202         0x10040100,
 203         0x00910091,
 204         0x00950095,
 205         0x009B009B,
 206         0x009E009E,
 207         0x00980098,
 208         0x00340034,
 209         0x00350035,
 210         0x00340034,
 211         0x00310031,
 212         0x00340034,
 213         0x007F007F,
 214         0x007F007F,
 215         0x007F007F,
 216         0x007F007F,
 217         0x007F007F,
 218         0x00480048,
 219         0x004A004A,
 220         0x00520052,
 221         0x00550055,
 222         0x00500050,
 223         0x00000000,
 224         0x00600020,
 225         0x40011080,
 226         0x08102040,
 227         0x0,
 228         0x0,
 229         0x0,
 230         0x0,
 231         0x0,
 232         0x0,
 233         0x0,
 234         0x0,
 235         0x0,
 236         0x0
 237 };
 238
 239 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 240         .sdram_config_init              = 0x61863332,
 241         .sdram_config                   = 0x61863332,
 242         .sdram_config2                  = 0x08000000,
 243         .ref_ctrl                       = 0x0000514d,
 244         .ref_ctrl_final                 = 0x0000144a,
 245         .sdram_tim1                     = 0xd333887c,
 246         .sdram_tim2                     = 0x30b37fe3,
 247         .sdram_tim3                     = 0x409f8ad8,
 248         .read_idle_ctrl                 = 0x00050000,
 249         .zq_config                      = 0x5007190b,
 250         .temp_alert_config              = 0x00000000,
 251         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 252         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 253         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 254         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 255         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 256         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 257         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 258         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 259         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 260         .emif_rd_wr_lvl_ctl             = 0x00000000,
 261         .emif_rd_wr_exec_thresh         = 0x00000305
 262 };
 263
 264 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
 265         .sdram_config_init              = 0x61863332,
 266         .sdram_config                   = 0x61863332,
 267         .sdram_config2                  = 0x08000000,
 268         .ref_ctrl                       = 0x0000514d,
 269         .ref_ctrl_final                 = 0x0000144a,
 270         .sdram_tim1                     = 0xd333887c,
 271         .sdram_tim2                     = 0x30b37fe3,
 272         .sdram_tim3                     = 0x409f8ad8,
 273         .read_idle_ctrl                 = 0x00050000,
 274         .zq_config                      = 0x5007190b,
 275         .temp_alert_config              = 0x00000000,
 276         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 277         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 278         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 279         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 280         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 281         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 282         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 283         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 284         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 285         .emif_rd_wr_lvl_ctl             = 0x00000000,
 286         .emif_rd_wr_exec_thresh         = 0x00000305,
 287         .emif_ecc_ctrl_reg              = 0xD0000001,
 288         .emif_ecc_address_range_1       = 0x3FFF0000,
 289         .emif_ecc_address_range_2       = 0x00000000
 290 };
 291
 292 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 293 {
 294         switch (emif_nr) {
 295         case 1:
 296                 if (board_is_am571x_idk())
 297                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 298                 else if (board_is_am574x_idk())
 299                         *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
 300                 else
 301                         *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 302                 break;
 303         case 2:
 304                 if (board_is_am574x_idk())
 305                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 306                 else
 307                         *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 308                 break;
 309         }
 310 }
 311
 312 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 313 {
 314         switch (emif_nr) {
 315         case 1:
 316                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 317                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 318                 break;
 319         case 2:
 320                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 321                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 322                 break;
 323         }
 324 }
 325
 326 struct vcores_data beagle_x15_volts = {
 327         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 328         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 329         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 330         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 331         .mpu.pmic               = &tps659038,
 332         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 333
 334         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 335         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 336         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 337         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 338         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 339         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 340         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 341         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 342         .eve.pmic               = &tps659038,
 343         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 344
 345         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 346         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 347         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 348         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 349         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 350         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 351         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 352         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 353         .gpu.pmic               = &tps659038,
 354         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 355
 356         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 357         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 358         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 359         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 360         .core.pmic              = &tps659038,
 361
 362         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 363         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 364         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 365         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 366         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 367         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 368         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 369         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 370         .iva.pmic               = &tps659038,
 371         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 372 };
 373
 374 struct vcores_data am572x_idk_volts = {
 375         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 376         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 377         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 378         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 379         .mpu.pmic               = &tps659038,
 380         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 381
 382         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 383         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 384         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 385         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 386         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 387         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 388         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 389         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 390         .eve.pmic               = &tps659038,
 391         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 392
 393         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 394         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 395         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 396         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 397         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 398         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 399         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 400         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 401         .gpu.pmic               = &tps659038,
 402         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 403
 404         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 405         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 406         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 407         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 408         .core.pmic              = &tps659038,
 409
 410         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 411         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 412         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 413         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 414         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 415         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 416         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 417         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 418         .iva.pmic               = &tps659038,
 419         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 420 };
 421
 422 struct vcores_data am571x_idk_volts = {
 423         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 424         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 425         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 426         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 427         .mpu.pmic               = &tps659038,
 428         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 429
 430         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 431         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 432         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 433         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 434         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 435         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 436         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 437         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 438         .eve.pmic               = &tps659038,
 439         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 440
 441         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 442         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 443         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 444         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 445         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 446         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 447         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 448         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 449         .gpu.pmic               = &tps659038,
 450         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 451
 452         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 453         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 454         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 455         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 456         .core.pmic              = &tps659038,
 457
 458         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 459         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 460         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 461         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 462         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 463         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 464         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 465         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 466         .iva.pmic               = &tps659038,
 467         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 468 };
 469
 470 int get_voltrail_opp(int rail_offset)
 471 {
 472         int opp;
 473
 474         switch (rail_offset) {
 475         case VOLT_MPU:
 476                 opp = DRA7_MPU_OPP;
 477                 break;
 478         case VOLT_CORE:
 479                 opp = DRA7_CORE_OPP;
 480                 break;
 481         case VOLT_GPU:
 482                 opp = DRA7_GPU_OPP;
 483                 break;
 484         case VOLT_EVE:
 485                 opp = DRA7_DSPEVE_OPP;
 486                 break;
 487         case VOLT_IVA:
 488                 opp = DRA7_IVA_OPP;
 489                 break;
 490         default:
 491                 opp = OPP_NOM;
 492         }
 493
 494         return opp;
 495 }
 496
 497
 498 #ifdef CONFIG_SPL_BUILD
 499 /* No env to setup for SPL */
 500 static inline void setup_board_eeprom_env(void) { }
 501
 502 /* Override function to read eeprom information */
 503 void do_board_detect(void)
 504 {
 505         int rc;
 506
 507         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 508                                   CONFIG_EEPROM_CHIP_ADDRESS);
 509         if (rc)
 510                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 511 }
 512
 513 #else   /* CONFIG_SPL_BUILD */
 514
 515 /* Override function to read eeprom information: actual i2c read done by SPL*/
 516 void do_board_detect(void)
 517 {
 518         char *bname = NULL;
 519         int rc;
 520
 521         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 522                                   CONFIG_EEPROM_CHIP_ADDRESS);
 523         if (rc)
 524                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 525
 526         if (board_is_x15())
 527                 bname = "BeagleBoard X15";
 528         else if (board_is_am572x_evm())
 529                 bname = "AM572x EVM";
 530         else if (board_is_am574x_idk())
 531                 bname = "AM574x IDK";
 532         else if (board_is_am572x_idk())
 533                 bname = "AM572x IDK";
 534         else if (board_is_am571x_idk())
 535                 bname = "AM571x IDK";
 536
 537         if (bname)
 538                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 539                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 540 }
 541
 542 static void setup_board_eeprom_env(void)
 543 {
 544         char *name = "beagle_x15";
 545         int rc;
 546
 547         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 548                                   CONFIG_EEPROM_CHIP_ADDRESS);
 549         if (rc)
 550                 goto invalid_eeprom;
 551
 552         if (board_is_x15()) {
 553                 if (board_is_x15_revb1())
 554                         name = "beagle_x15_revb1";
 555                 else if (board_is_x15_revc())
 556                         name = "beagle_x15_revc";
 557                 else
 558                         name = "beagle_x15";
 559         } else if (board_is_am572x_evm()) {
 560                 if (board_is_am572x_evm_reva3())
 561                         name = "am57xx_evm_reva3";
 562                 else
 563                         name = "am57xx_evm";
 564         } else if (board_is_am574x_idk()) {
 565                 name = "am574x_idk";
 566         } else if (board_is_am572x_idk()) {
 567                 name = "am572x_idk";
 568         } else if (board_is_am571x_idk()) {
 569                 name = "am571x_idk";
 570         } else {
 571                 printf("Unidentified board claims %s in eeprom header\n",
 572                        board_ti_get_name());
 573         }
 574
 575 invalid_eeprom:
 576         set_board_info_env(name);
 577 }
 578
 579 #endif  /* CONFIG_SPL_BUILD */
 580
 581 void vcores_init(void)
 582 {
 583         if (board_is_am572x_idk() || board_is_am574x_idk())
 584                 *omap_vcores = &am572x_idk_volts;
 585         else if (board_is_am571x_idk())
 586                 *omap_vcores = &am571x_idk_volts;
 587         else
 588                 *omap_vcores = &beagle_x15_volts;
 589 }
 590
 591 void hw_data_init(void)
 592 {
 593         *prcm = &dra7xx_prcm;
 594         if (is_dra72x())
 595                 *dplls_data = &dra72x_dplls;
 596         else if (is_dra76x())
 597                 *dplls_data = &dra76x_dplls;
 598         else
 599                 *dplls_data = &dra7xx_dplls;
 600         *ctrl = &dra7xx_ctrl;
 601 }
 602
 603 bool am571x_idk_needs_lcd(void)
 604 {
 605         bool needs_lcd;
 606
 607         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 608         if (gpio_get_value(GPIO_ETH_LCD))
 609                 needs_lcd = false;
 610         else
 611                 needs_lcd = true;
 612
 613         gpio_free(GPIO_ETH_LCD);
 614
 615         return needs_lcd;
 616 }
 617
 618 int board_init(void)
 619 {
 620         gpmc_init();
 621         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 622
 623         return 0;
 624 }
 625
 626 void am57x_idk_lcd_detect(void)
 627 {
 628         int r = -ENODEV;
 629         char *idk_lcd = "no";
 630         struct udevice *dev;
 631
 632         /* Only valid for IDKs */
 633         if (board_is_x15() || board_is_am572x_evm())
 634                 return;
 635
 636         /* Only AM571x IDK has gpio control detect.. so check that */
 637         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 638                 goto out;
 639
 640         r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
 641                                     OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
 642         if (r) {
 643                 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
 644                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 645                        r);
 646                 /* AM572x IDK has no explicit settings for optional LCD kit */
 647                 if (board_is_am571x_idk())
 648                         printf("%s: Touch screen detect failed: %d!\n",
 649                                __func__, r);
 650                 goto out;
 651         }
 652
 653         /* Read FT ID */
 654         r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
 655         if (r < 0) {
 656                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 657                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 658                        OSD_TS_FT_REG_ID, r);
 659                 goto out;
 660         }
 661
 662         switch (r) {
 663         case OSD_TS_FT_ID_5606:
 664                 idk_lcd = "osd101t2045";
 665                 break;
 666         case OSD_TS_FT_ID_5x46:
 667                 idk_lcd = "osd101t2587";
 668                 break;
 669         default:
 670                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 671                        __func__, r);
 672                 /* we will let default be "no lcd" */
 673         }
 674 out:
 675         env_set("idk_lcd", idk_lcd);
 676         return;
 677 }
 678
 679 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 680 static int device_okay(const char *path)
 681 {
 682         int node;
 683
 684         node = fdt_path_offset(gd->fdt_blob, path);
 685         if (node < 0)
 686                 return 0;
 687
 688         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 689 }
 690 #endif
 691
 692 int board_late_init(void)
 693 {
 694         setup_board_eeprom_env();
 695         u8 val;
 696         struct udevice *dev;
 697
 698         /*
 699          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 700          * This is the POWERHOLD-in-Low behavior.
 701          */
 702         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 703
 704         /*
 705          * Default FIT boot on HS devices. Non FIT images are not allowed
 706          * on HS devices.
 707          */
 708         if (get_device_type() == HS_DEVICE)
 709                 env_set("boot_fit", "1");
 710
 711         /*
 712          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 713          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 714          * PMIC Power off. So to be on the safer side set it back
 715          * to POWERHOLD mode irrespective of the current state.
 716          */
 717         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 718                            &val);
 719         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 720         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 721                             val);
 722
 723         omap_die_id_serial();
 724         omap_set_fastboot_vars();
 725
 726         am57x_idk_lcd_detect();
 727
 728         /* Just probe the potentially supported cdce913 device */
 729         uclass_get_device(UCLASS_CLK, 0, &dev);
 730
 731 #if !defined(CONFIG_SPL_BUILD)
 732         board_ti_set_ethaddr(2);
 733 #endif
 734
 735 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 736         if (device_okay("/ocp/omap_dwc3_1@48880000"))
 737                 enable_usb_clocks(0);
 738         if (device_okay("/ocp/omap_dwc3_2@488c0000"))
 739                 enable_usb_clocks(1);
 740 #endif
 741         return 0;
 742 }
 743
 744 void set_muxconf_regs(void)
 745 {
 746         do_set_mux32((*ctrl)->control_padconf_core_base,
 747                      early_padconf, ARRAY_SIZE(early_padconf));
 748 }
 749
 750 #ifdef CONFIG_IODELAY_RECALIBRATION
 751 void recalibrate_iodelay(void)
 752 {
 753         const struct pad_conf_entry *pconf;
 754         const struct iodelay_cfg_entry *iod, *delta_iod;
 755         int pconf_sz, iod_sz, delta_iod_sz = 0;
 756         int ret;
 757
 758         if (board_is_am572x_idk()) {
 759                 pconf = core_padconf_array_essential_am572x_idk;
 760                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 761                 iod = iodelay_cfg_array_am572x_idk;
 762                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 763         } else if (board_is_am574x_idk()) {
 764                 pconf = core_padconf_array_essential_am574x_idk;
 765                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
 766                 iod = iodelay_cfg_array_am574x_idk;
 767                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
 768         } else if (board_is_am571x_idk()) {
 769                 pconf = core_padconf_array_essential_am571x_idk;
 770                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 771                 iod = iodelay_cfg_array_am571x_idk;
 772                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 773         } else {
 774                 /* Common for X15/GPEVM */
 775                 pconf = core_padconf_array_essential_x15;
 776                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 777                 /* There never was an SR1.0 X15.. So.. */
 778                 if (omap_revision() == DRA752_ES1_1) {
 779                         iod = iodelay_cfg_array_x15_sr1_1;
 780                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 781                 } else {
 782                         /* Since full production should switch to SR2.0  */
 783                         iod = iodelay_cfg_array_x15_sr2_0;
 784                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 785                 }
 786         }
 787
 788         /* Setup I/O isolation */
 789         ret = __recalibrate_iodelay_start();
 790         if (ret)
 791                 goto err;
 792
 793         /* Do the muxing here */
 794         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 795
 796         /* Now do the weird minor deltas that should be safe */
 797         if (board_is_x15() || board_is_am572x_evm()) {
 798                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 799                     board_is_x15_revc()) {
 800                         pconf = core_padconf_array_delta_x15_sr2_0;
 801                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 802                 } else {
 803                         pconf = core_padconf_array_delta_x15_sr1_1;
 804                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 805                 }
 806                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 807         }
 808
 809         if (board_is_am571x_idk()) {
 810                 if (am571x_idk_needs_lcd()) {
 811                         pconf = core_padconf_array_vout_am571x_idk;
 812                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 813                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 814                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 815
 816                 } else {
 817                         pconf = core_padconf_array_icss1eth_am571x_idk;
 818                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 819                 }
 820                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 821         }
 822
 823         /* Setup IOdelay configuration */
 824         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 825         if (delta_iod_sz)
 826                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 827                                      delta_iod_sz);
 828
 829 err:
 830         /* Closeup.. remove isolation */
 831         __recalibrate_iodelay_end(ret);
 832 }
 833 #endif
 834
 835 #if defined(CONFIG_MMC)
 836 int board_mmc_init(bd_t *bis)
 837 {
 838         omap_mmc_init(0, 0, 0, -1, -1);
 839         omap_mmc_init(1, 0, 0, -1, -1);
 840         return 0;
 841 }
 842
 843 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
 844         .hw_rev = "rev11",
 845         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 846                             MMC_CAP(UHS_SDR104),
 847         .max_freq = 96000000,
 848 };
 849
 850 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
 851         .hw_rev = "rev11",
 852         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 853                             MMC_CAP(UHS_SDR104) |
 854                             MMC_CAP(UHS_SDR50),
 855         .max_freq = 48000000,
 856 };
 857
 858 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 859 {
 860         switch (omap_revision()) {
 861         case DRA752_ES1_0:
 862         case DRA752_ES1_1:
 863                 if (addr == OMAP_HSMMC1_BASE)
 864                         return &am57x_es1_1_mmc1_fixups;
 865                 else
 866                         return &am57x_es1_1_mmc23_fixups;
 867         default:
 868                 return NULL;
 869         }
 870 }
 871 #endif
 872
 873 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 874 int spl_start_uboot(void)
 875 {
 876         /* break into full u-boot on 'c' */
 877         if (serial_tstc() && serial_getc() == 'c')
 878                 return 1;
 879
 880 #ifdef CONFIG_SPL_ENV_SUPPORT
 881         env_init();
 882         env_load();
 883         if (env_get_yesno("boot_os") != 1)
 884                 return 1;
 885 #endif
 886
 887         return 0;
 888 }
 889 #endif
 890
 891 #ifdef CONFIG_DRIVER_TI_CPSW
 892
 893 /* Delay value to add to calibrated value */
 894 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 895 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 896 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 897 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 898 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 899 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 900 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 901 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 902 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 903 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 904
 905 static void cpsw_control(int enabled)
 906 {
 907         /* VTP can be added here */
 908 }
 909
 910 static struct cpsw_slave_data cpsw_slaves[] = {
 911         {
 912                 .slave_reg_ofs  = 0x208,
 913                 .sliver_reg_ofs = 0xd80,
 914                 .phy_addr       = 1,
 915         },
 916         {
 917                 .slave_reg_ofs  = 0x308,
 918                 .sliver_reg_ofs = 0xdc0,
 919                 .phy_addr       = 2,
 920         },
 921 };
 922
 923 static struct cpsw_platform_data cpsw_data = {
 924         .mdio_base              = CPSW_MDIO_BASE,
 925         .cpsw_base              = CPSW_BASE,
 926         .mdio_div               = 0xff,
 927         .channels               = 8,
 928         .cpdma_reg_ofs          = 0x800,
 929         .slaves                 = 1,
 930         .slave_data             = cpsw_slaves,
 931         .ale_reg_ofs            = 0xd00,
 932         .ale_entries            = 1024,
 933         .host_port_reg_ofs      = 0x108,
 934         .hw_stats_reg_ofs       = 0x900,
 935         .bd_ram_ofs             = 0x2000,
 936         .mac_control            = (1 << 5),
 937         .control                = cpsw_control,
 938         .host_port_num          = 0,
 939         .version                = CPSW_CTRL_VERSION_2,
 940 };
 941
 942 static u64 mac_to_u64(u8 mac[6])
 943 {
 944         int i;
 945         u64 addr = 0;
 946
 947         for (i = 0; i < 6; i++) {
 948                 addr <<= 8;
 949                 addr |= mac[i];
 950         }
 951
 952         return addr;
 953 }
 954
 955 static void u64_to_mac(u64 addr, u8 mac[6])
 956 {
 957         mac[5] = addr;
 958         mac[4] = addr >> 8;
 959         mac[3] = addr >> 16;
 960         mac[2] = addr >> 24;
 961         mac[1] = addr >> 32;
 962         mac[0] = addr >> 40;
 963 }
 964
 965 int board_eth_init(bd_t *bis)
 966 {
 967         int ret;
 968         uint8_t mac_addr[6];
 969         uint32_t mac_hi, mac_lo;
 970         uint32_t ctrl_val;
 971         int i;
 972         u64 mac1, mac2;
 973         u8 mac_addr1[6], mac_addr2[6];
 974         int num_macs;
 975
 976         /* try reading mac address from efuse */
 977         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 978         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 979         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 980         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 981         mac_addr[2] = mac_hi & 0xFF;
 982         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 983         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 984         mac_addr[5] = mac_lo & 0xFF;
 985
 986         if (!env_get("ethaddr")) {
 987                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 988
 989                 if (is_valid_ethaddr(mac_addr))
 990                         eth_env_set_enetaddr("ethaddr", mac_addr);
 991         }
 992
 993         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 994         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 995         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 996         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 997         mac_addr[2] = mac_hi & 0xFF;
 998         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 999         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1000         mac_addr[5] = mac_lo & 0xFF;
1001
1002         if (!env_get("eth1addr")) {
1003                 if (is_valid_ethaddr(mac_addr))
1004                         eth_env_set_enetaddr("eth1addr", mac_addr);
1005         }
1006
1007         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1008         ctrl_val |= 0x22;
1009         writel(ctrl_val, (*ctrl)->control_core_control_io1);
1010
1011         /* The phy address for the AM57xx IDK are different than x15 */
1012         if (board_is_am572x_idk() || board_is_am571x_idk() ||
1013             board_is_am574x_idk()) {
1014                 cpsw_data.slave_data[0].phy_addr = 0;
1015                 cpsw_data.slave_data[1].phy_addr = 1;
1016         }
1017
1018         ret = cpsw_register(&cpsw_data);
1019         if (ret < 0)
1020                 printf("Error %d registering CPSW switch\n", ret);
1021
1022         /*
1023          * Export any Ethernet MAC addresses from EEPROM.
1024          * On AM57xx the 2 MAC addresses define the address range
1025          */
1026         board_ti_get_eth_mac_addr(0, mac_addr1);
1027         board_ti_get_eth_mac_addr(1, mac_addr2);
1028
1029         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1030                 mac1 = mac_to_u64(mac_addr1);
1031                 mac2 = mac_to_u64(mac_addr2);
1032
1033                 /* must contain an address range */
1034                 num_macs = mac2 - mac1 + 1;
1035                 /* <= 50 to protect against user programming error */
1036                 if (num_macs > 0 && num_macs <= 50) {
1037                         for (i = 0; i < num_macs; i++) {
1038                                 u64_to_mac(mac1 + i, mac_addr);
1039                                 if (is_valid_ethaddr(mac_addr)) {
1040                                         eth_env_set_enetaddr_by_index("eth",
1041                                                                       i + 2,
1042                                                                       mac_addr);
1043                                 }
1044                         }
1045                 }
1046         }
1047
1048         return ret;
1049 }
1050 #endif
1051
1052 #ifdef CONFIG_BOARD_EARLY_INIT_F
1053 /* VTT regulator enable */
1054 static inline void vtt_regulator_enable(void)
1055 {
1056         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1057                 return;
1058
1059         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1060         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1061 }
1062
1063 int board_early_init_f(void)
1064 {
1065         vtt_regulator_enable();
1066         return 0;
1067 }
1068 #endif
1069
1070 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1071 int ft_board_setup(void *blob, bd_t *bd)
1072 {
1073         ft_cpu_setup(blob, bd);
1074
1075         return 0;
1076 }
1077 #endif
1078
1079 #ifdef CONFIG_SPL_LOAD_FIT
1080 int board_fit_config_name_match(const char *name)
1081 {
1082         if (board_is_x15()) {
1083                 if (board_is_x15_revb1()) {
1084                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1085                                 return 0;
1086                 } else if (board_is_x15_revc()) {
1087                         if (!strcmp(name, "am57xx-beagle-x15-revc"))
1088                                 return 0;
1089                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1090                         return 0;
1091                 }
1092         } else if (board_is_am572x_evm() &&
1093                    !strcmp(name, "am57xx-beagle-x15")) {
1094                 return 0;
1095         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1096                 return 0;
1097         } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1098                 return 0;
1099         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1100                 return 0;
1101         }
1102
1103         return -1;
1104 }
1105 #endif
1106
1107 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1108 int fastboot_set_reboot_flag(void)
1109 {
1110         printf("Setting reboot to fastboot flag ...\n");
1111         env_set("dofastboot", "1");
1112         env_save();
1113         return 0;
1114 }
1115 #endif
1116
1117 #ifdef CONFIG_TI_SECURE_DEVICE
1118 void board_fit_image_post_process(void **p_image, size_t *p_size)
1119 {
1120         secure_boot_verify_image(p_image, p_size);
1121 }
1122
1123 void board_tee_image_process(ulong tee_image, size_t tee_size)
1124 {
1125         secure_tee_install((u32)tee_image);
1126 }
1127
1128 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1129 #endif