board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/emif.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sata.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/omap.h>
  27 #include <environment.h>
  28 #include <usb.h>
  29 #include <linux/usb/gadget.h>
  30 #include <dwc3-uboot.h>
  31 #include <dwc3-omap-uboot.h>
  32 #include <ti-usb-phy-uboot.h>
  33
  34 #include "../common/board_detect.h"
  35 #include "mux_data.h"
  36
  37 #define board_is_x15()          board_ti_is("BBRDX15_")
  38 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  39 #define board_is_am572x_evm_reva3()     \
  40                                 (board_ti_is("AM572PM_") && \
  41                                  (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
  42 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  43
  44 #ifdef CONFIG_DRIVER_TI_CPSW
  45 #include <cpsw.h>
  46 #endif
  47
  48 DECLARE_GLOBAL_DATA_PTR;
  49
  50 /* GPIO 7_11 */
  51 #define GPIO_DDR_VTT_EN 203
  52
  53 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  54
  55 const struct omap_sysinfo sysinfo = {
  56         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  57 };
  58
  59 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  60         .dmm_lisa_map_3 = 0x80740300,
  61         .is_ma_present  = 0x1
  62 };
  63
  64 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  65 {
  66         *dmm_lisa_regs = &beagle_x15_lisa_regs;
  67 }
  68
  69 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  70         .sdram_config_init              = 0x61851b32,
  71         .sdram_config                   = 0x61851b32,
  72         .sdram_config2                  = 0x08000000,
  73         .ref_ctrl                       = 0x000040F1,
  74         .ref_ctrl_final                 = 0x00001035,
  75         .sdram_tim1                     = 0xcccf36ab,
  76         .sdram_tim2                     = 0x308f7fda,
  77         .sdram_tim3                     = 0x409f88a8,
  78         .read_idle_ctrl                 = 0x00050000,
  79         .zq_config                      = 0x5007190b,
  80         .temp_alert_config              = 0x00000000,
  81         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
  82         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
  83         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  84         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  85         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  86         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
  87         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
  88         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  89         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  90         .emif_rd_wr_lvl_ctl             = 0x00000000,
  91         .emif_rd_wr_exec_thresh         = 0x00000305
  92 };
  93
  94 /* Ext phy ctrl regs 1-35 */
  95 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  96         0x10040100,
  97         0x00910091,
  98         0x00950095,
  99         0x009B009B,
 100         0x009E009E,
 101         0x00980098,
 102         0x00340034,
 103         0x00350035,
 104         0x00340034,
 105         0x00310031,
 106         0x00340034,
 107         0x007F007F,
 108         0x007F007F,
 109         0x007F007F,
 110         0x007F007F,
 111         0x007F007F,
 112         0x00480048,
 113         0x004A004A,
 114         0x00520052,
 115         0x00550055,
 116         0x00500050,
 117         0x00000000,
 118         0x00600020,
 119         0x40011080,
 120         0x08102040,
 121         0x0,
 122         0x0,
 123         0x0,
 124         0x0,
 125         0x0,
 126         0x0,
 127         0x0,
 128         0x0,
 129         0x0,
 130         0x0
 131 };
 132
 133 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 134         .sdram_config_init              = 0x61851b32,
 135         .sdram_config                   = 0x61851b32,
 136         .sdram_config2                  = 0x08000000,
 137         .ref_ctrl                       = 0x000040F1,
 138         .ref_ctrl_final                 = 0x00001035,
 139         .sdram_tim1                     = 0xcccf36b3,
 140         .sdram_tim2                     = 0x308f7fda,
 141         .sdram_tim3                     = 0x407f88a8,
 142         .read_idle_ctrl                 = 0x00050000,
 143         .zq_config                      = 0x5007190b,
 144         .temp_alert_config              = 0x00000000,
 145         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 146         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 147         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 148         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 149         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 150         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 151         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 152         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 153         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 154         .emif_rd_wr_lvl_ctl             = 0x00000000,
 155         .emif_rd_wr_exec_thresh         = 0x00000305
 156 };
 157
 158 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 159         0x10040100,
 160         0x00910091,
 161         0x00950095,
 162         0x009B009B,
 163         0x009E009E,
 164         0x00980098,
 165         0x00340034,
 166         0x00350035,
 167         0x00340034,
 168         0x00310031,
 169         0x00340034,
 170         0x007F007F,
 171         0x007F007F,
 172         0x007F007F,
 173         0x007F007F,
 174         0x007F007F,
 175         0x00480048,
 176         0x004A004A,
 177         0x00520052,
 178         0x00550055,
 179         0x00500050,
 180         0x00000000,
 181         0x00600020,
 182         0x40011080,
 183         0x08102040,
 184         0x0,
 185         0x0,
 186         0x0,
 187         0x0,
 188         0x0,
 189         0x0,
 190         0x0,
 191         0x0,
 192         0x0,
 193         0x0
 194 };
 195
 196 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 197 {
 198         switch (emif_nr) {
 199         case 1:
 200                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 201                 break;
 202         case 2:
 203                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 204                 break;
 205         }
 206 }
 207
 208 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 209 {
 210         switch (emif_nr) {
 211         case 1:
 212                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 213                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 214                 break;
 215         case 2:
 216                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 217                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 218                 break;
 219         }
 220 }
 221
 222 struct vcores_data beagle_x15_volts = {
 223         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 224         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 225         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 226         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 227         .mpu.pmic               = &tps659038,
 228         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 229
 230         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 231         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 232         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 233         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 234         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 235         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 236         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 237         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 238         .eve.pmic               = &tps659038,
 239         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 240
 241         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 242         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 243         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 244         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 245         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 246         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 247         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 248         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 249         .gpu.pmic               = &tps659038,
 250         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 251
 252         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 253         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 254         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 255         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 256         .core.pmic              = &tps659038,
 257
 258         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 259         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 260         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 261         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 262         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 263         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 264         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 265         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 266         .iva.pmic               = &tps659038,
 267         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 268 };
 269
 270 struct vcores_data am572x_idk_volts = {
 271         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 272         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 273         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 274         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 275         .mpu.pmic               = &tps659038,
 276         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 277
 278         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 279         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 280         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 281         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 282         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 283         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 284         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 285         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 286         .eve.pmic               = &tps659038,
 287         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 288
 289         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 290         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 291         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 292         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 293         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 294         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 295         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 296         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 297         .gpu.pmic               = &tps659038,
 298         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 299
 300         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 301         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 302         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 303         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 304         .core.pmic              = &tps659038,
 305
 306         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 307         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 308         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 309         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 310         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 311         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 312         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 313         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 314         .iva.pmic               = &tps659038,
 315         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 316 };
 317
 318 int get_voltrail_opp(int rail_offset)
 319 {
 320         int opp;
 321
 322         switch (rail_offset) {
 323         case VOLT_MPU:
 324                 opp = DRA7_MPU_OPP;
 325                 break;
 326         case VOLT_CORE:
 327                 opp = DRA7_CORE_OPP;
 328                 break;
 329         case VOLT_GPU:
 330                 opp = DRA7_GPU_OPP;
 331                 break;
 332         case VOLT_EVE:
 333                 opp = DRA7_DSPEVE_OPP;
 334                 break;
 335         case VOLT_IVA:
 336                 opp = DRA7_IVA_OPP;
 337                 break;
 338         default:
 339                 opp = OPP_NOM;
 340         }
 341
 342         return opp;
 343 }
 344
 345
 346 #ifdef CONFIG_SPL_BUILD
 347 /* No env to setup for SPL */
 348 static inline void setup_board_eeprom_env(void) { }
 349
 350 /* Override function to read eeprom information */
 351 void do_board_detect(void)
 352 {
 353         int rc;
 354
 355         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 356                                   CONFIG_EEPROM_CHIP_ADDRESS);
 357         if (rc)
 358                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 359 }
 360
 361 #else   /* CONFIG_SPL_BUILD */
 362
 363 /* Override function to read eeprom information: actual i2c read done by SPL*/
 364 void do_board_detect(void)
 365 {
 366         char *bname = NULL;
 367         int rc;
 368
 369         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 370                                   CONFIG_EEPROM_CHIP_ADDRESS);
 371         if (rc)
 372                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 373
 374         if (board_is_x15())
 375                 bname = "BeagleBoard X15";
 376         else if (board_is_am572x_evm())
 377                 bname = "AM572x EVM";
 378         else if (board_is_am572x_idk())
 379                 bname = "AM572x IDK";
 380
 381         if (bname)
 382                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 383                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 384 }
 385
 386 static void setup_board_eeprom_env(void)
 387 {
 388         char *name = "beagle_x15";
 389         int rc;
 390
 391         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 392                                   CONFIG_EEPROM_CHIP_ADDRESS);
 393         if (rc)
 394                 goto invalid_eeprom;
 395
 396         if (board_is_x15()) {
 397                 name = "beagle_x15";
 398         } else if (board_is_am572x_evm()) {
 399                 if (board_is_am572x_evm_reva3())
 400                         name = "am57xx_evm_reva3";
 401                 else
 402                         name = "am57xx_evm";
 403         } else if (board_is_am572x_idk()) {
 404                 name = "am572x_idk";
 405         } else {
 406                 printf("Unidentified board claims %s in eeprom header\n",
 407                        board_ti_get_name());
 408         }
 409
 410 invalid_eeprom:
 411         set_board_info_env(name);
 412 }
 413
 414 #endif  /* CONFIG_SPL_BUILD */
 415
 416 void vcores_init(void)
 417 {
 418         if (board_is_am572x_idk())
 419                 *omap_vcores = &am572x_idk_volts;
 420         else
 421                 *omap_vcores = &beagle_x15_volts;
 422 }
 423
 424 void hw_data_init(void)
 425 {
 426         *prcm = &dra7xx_prcm;
 427         *dplls_data = &dra7xx_dplls;
 428         *ctrl = &dra7xx_ctrl;
 429 }
 430
 431 int board_init(void)
 432 {
 433         gpmc_init();
 434         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 435
 436         return 0;
 437 }
 438
 439 int board_late_init(void)
 440 {
 441         setup_board_eeprom_env();
 442
 443         /*
 444          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 445          * This is the POWERHOLD-in-Low behavior.
 446          */
 447         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 448
 449         /*
 450          * Default FIT boot on HS devices. Non FIT images are not allowed
 451          * on HS devices.
 452          */
 453         if (get_device_type() == HS_DEVICE)
 454                 setenv("boot_fit", "1");
 455
 456         return 0;
 457 }
 458
 459 void set_muxconf_regs(void)
 460 {
 461         do_set_mux32((*ctrl)->control_padconf_core_base,
 462                      early_padconf, ARRAY_SIZE(early_padconf));
 463 }
 464
 465 #ifdef CONFIG_IODELAY_RECALIBRATION
 466 void recalibrate_iodelay(void)
 467 {
 468         const struct pad_conf_entry *pconf;
 469         const struct iodelay_cfg_entry *iod;
 470         int pconf_sz, iod_sz;
 471
 472         if (board_is_am572x_idk()) {
 473                 pconf = core_padconf_array_essential_am572x_idk;
 474                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 475                 iod = iodelay_cfg_array_am572x_idk;
 476                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 477         } else {
 478                 /* Common for X15/GPEVM */
 479                 pconf = core_padconf_array_essential_x15;
 480                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 481                 iod = iodelay_cfg_array_x15;
 482                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
 483         }
 484
 485         __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
 486 }
 487 #endif
 488
 489 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 490 int board_mmc_init(bd_t *bis)
 491 {
 492         omap_mmc_init(0, 0, 0, -1, -1);
 493         omap_mmc_init(1, 0, 0, -1, -1);
 494         return 0;
 495 }
 496 #endif
 497
 498 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 499 int spl_start_uboot(void)
 500 {
 501         /* break into full u-boot on 'c' */
 502         if (serial_tstc() && serial_getc() == 'c')
 503                 return 1;
 504
 505 #ifdef CONFIG_SPL_ENV_SUPPORT
 506         env_init();
 507         env_relocate_spec();
 508         if (getenv_yesno("boot_os") != 1)
 509                 return 1;
 510 #endif
 511
 512         return 0;
 513 }
 514 #endif
 515
 516 #ifdef CONFIG_USB_DWC3
 517 static struct dwc3_device usb_otg_ss2 = {
 518         .maximum_speed = USB_SPEED_HIGH,
 519         .base = DRA7_USB_OTG_SS2_BASE,
 520         .tx_fifo_resize = false,
 521         .index = 1,
 522 };
 523
 524 static struct dwc3_omap_device usb_otg_ss2_glue = {
 525         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 526         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 527         .index = 1,
 528 };
 529
 530 static struct ti_usb_phy_device usb_phy2_device = {
 531         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 532         .index = 1,
 533 };
 534
 535 int usb_gadget_handle_interrupts(int index)
 536 {
 537         u32 status;
 538
 539         status = dwc3_omap_uboot_interrupt_status(index);
 540         if (status)
 541                 dwc3_uboot_handle_interrupt(index);
 542
 543         return 0;
 544 }
 545 #endif /* CONFIG_USB_DWC3 */
 546
 547 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 548 int board_usb_init(int index, enum usb_init_type init)
 549 {
 550         enable_usb_clocks(index);
 551         switch (index) {
 552         case 0:
 553                 if (init == USB_INIT_DEVICE) {
 554                         printf("port %d can't be used as device\n", index);
 555                         disable_usb_clocks(index);
 556                         return -EINVAL;
 557                 }
 558                 break;
 559         case 1:
 560                 if (init == USB_INIT_DEVICE) {
 561 #ifdef CONFIG_USB_DWC3
 562                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 563                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 564                         ti_usb_phy_uboot_init(&usb_phy2_device);
 565                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 566                         dwc3_uboot_init(&usb_otg_ss2);
 567 #endif
 568                 } else {
 569                         printf("port %d can't be used as host\n", index);
 570                         disable_usb_clocks(index);
 571                         return -EINVAL;
 572                 }
 573
 574                 break;
 575         default:
 576                 printf("Invalid Controller Index\n");
 577         }
 578
 579         return 0;
 580 }
 581
 582 int board_usb_cleanup(int index, enum usb_init_type init)
 583 {
 584 #ifdef CONFIG_USB_DWC3
 585         switch (index) {
 586         case 0:
 587         case 1:
 588                 if (init == USB_INIT_DEVICE) {
 589                         ti_usb_phy_uboot_exit(index);
 590                         dwc3_uboot_exit(index);
 591                         dwc3_omap_uboot_exit(index);
 592                 }
 593                 break;
 594         default:
 595                 printf("Invalid Controller Index\n");
 596         }
 597 #endif
 598         disable_usb_clocks(index);
 599         return 0;
 600 }
 601 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 602
 603 #ifdef CONFIG_DRIVER_TI_CPSW
 604
 605 /* Delay value to add to calibrated value */
 606 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 607 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 608 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 609 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 610 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 611 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 612 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 613 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 614 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 615 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 616
 617 static void cpsw_control(int enabled)
 618 {
 619         /* VTP can be added here */
 620 }
 621
 622 static struct cpsw_slave_data cpsw_slaves[] = {
 623         {
 624                 .slave_reg_ofs  = 0x208,
 625                 .sliver_reg_ofs = 0xd80,
 626                 .phy_addr       = 1,
 627         },
 628         {
 629                 .slave_reg_ofs  = 0x308,
 630                 .sliver_reg_ofs = 0xdc0,
 631                 .phy_addr       = 2,
 632         },
 633 };
 634
 635 static struct cpsw_platform_data cpsw_data = {
 636         .mdio_base              = CPSW_MDIO_BASE,
 637         .cpsw_base              = CPSW_BASE,
 638         .mdio_div               = 0xff,
 639         .channels               = 8,
 640         .cpdma_reg_ofs          = 0x800,
 641         .slaves                 = 1,
 642         .slave_data             = cpsw_slaves,
 643         .ale_reg_ofs            = 0xd00,
 644         .ale_entries            = 1024,
 645         .host_port_reg_ofs      = 0x108,
 646         .hw_stats_reg_ofs       = 0x900,
 647         .bd_ram_ofs             = 0x2000,
 648         .mac_control            = (1 << 5),
 649         .control                = cpsw_control,
 650         .host_port_num          = 0,
 651         .version                = CPSW_CTRL_VERSION_2,
 652 };
 653
 654 static u64 mac_to_u64(u8 mac[6])
 655 {
 656         int i;
 657         u64 addr = 0;
 658
 659         for (i = 0; i < 6; i++) {
 660                 addr <<= 8;
 661                 addr |= mac[i];
 662         }
 663
 664         return addr;
 665 }
 666
 667 static void u64_to_mac(u64 addr, u8 mac[6])
 668 {
 669         mac[5] = addr;
 670         mac[4] = addr >> 8;
 671         mac[3] = addr >> 16;
 672         mac[2] = addr >> 24;
 673         mac[1] = addr >> 32;
 674         mac[0] = addr >> 40;
 675 }
 676
 677 int board_eth_init(bd_t *bis)
 678 {
 679         int ret;
 680         uint8_t mac_addr[6];
 681         uint32_t mac_hi, mac_lo;
 682         uint32_t ctrl_val;
 683         int i;
 684         u64 mac1, mac2;
 685         u8 mac_addr1[6], mac_addr2[6];
 686         int num_macs;
 687
 688         /* try reading mac address from efuse */
 689         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 690         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 691         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 692         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 693         mac_addr[2] = mac_hi & 0xFF;
 694         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 695         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 696         mac_addr[5] = mac_lo & 0xFF;
 697
 698         if (!getenv("ethaddr")) {
 699                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 700
 701                 if (is_valid_ethaddr(mac_addr))
 702                         eth_setenv_enetaddr("ethaddr", mac_addr);
 703         }
 704
 705         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 706         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 707         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 708         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 709         mac_addr[2] = mac_hi & 0xFF;
 710         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 711         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 712         mac_addr[5] = mac_lo & 0xFF;
 713
 714         if (!getenv("eth1addr")) {
 715                 if (is_valid_ethaddr(mac_addr))
 716                         eth_setenv_enetaddr("eth1addr", mac_addr);
 717         }
 718
 719         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 720         ctrl_val |= 0x22;
 721         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 722
 723         /* The phy address for the AM572x IDK are different than x15 */
 724         if (board_is_am572x_idk()) {
 725                 cpsw_data.slave_data[0].phy_addr = 0;
 726                 cpsw_data.slave_data[1].phy_addr = 1;
 727         }
 728
 729         ret = cpsw_register(&cpsw_data);
 730         if (ret < 0)
 731                 printf("Error %d registering CPSW switch\n", ret);
 732
 733         /*
 734          * Export any Ethernet MAC addresses from EEPROM.
 735          * On AM57xx the 2 MAC addresses define the address range
 736          */
 737         board_ti_get_eth_mac_addr(0, mac_addr1);
 738         board_ti_get_eth_mac_addr(1, mac_addr2);
 739
 740         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
 741                 mac1 = mac_to_u64(mac_addr1);
 742                 mac2 = mac_to_u64(mac_addr2);
 743
 744                 /* must contain an address range */
 745                 num_macs = mac2 - mac1 + 1;
 746                 /* <= 50 to protect against user programming error */
 747                 if (num_macs > 0 && num_macs <= 50) {
 748                         for (i = 0; i < num_macs; i++) {
 749                                 u64_to_mac(mac1 + i, mac_addr);
 750                                 if (is_valid_ethaddr(mac_addr)) {
 751                                         eth_setenv_enetaddr_by_index("eth",
 752                                                                      i + 2,
 753                                                                      mac_addr);
 754                                 }
 755                         }
 756                 }
 757         }
 758
 759         return ret;
 760 }
 761 #endif
 762
 763 #ifdef CONFIG_BOARD_EARLY_INIT_F
 764 /* VTT regulator enable */
 765 static inline void vtt_regulator_enable(void)
 766 {
 767         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 768                 return;
 769
 770         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 771         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 772 }
 773
 774 int board_early_init_f(void)
 775 {
 776         vtt_regulator_enable();
 777         return 0;
 778 }
 779 #endif
 780
 781 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 782 int ft_board_setup(void *blob, bd_t *bd)
 783 {
 784         ft_cpu_setup(blob, bd);
 785
 786         return 0;
 787 }
 788 #endif
 789
 790 #ifdef CONFIG_SPL_LOAD_FIT
 791 int board_fit_config_name_match(const char *name)
 792 {
 793         if (board_is_x15() && !strcmp(name, "am57xx-beagle-x15"))
 794                 return 0;
 795         else if (board_is_am572x_evm() && !strcmp(name, "am57xx-beagle-x15"))
 796                 return 0;
 797         else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk"))
 798                 return 0;
 799         else
 800                 return -1;
 801 }
 802 #endif
 803
 804 #ifdef CONFIG_TI_SECURE_DEVICE
 805 void board_fit_image_post_process(void **p_image, size_t *p_size)
 806 {
 807         secure_boot_verify_image(p_image, p_size);
 808 }
 809
 810 void board_tee_image_process(ulong tee_image, size_t tee_size)
 811 {
 812         secure_tee_install((u32)tee_image);
 813 }
 814
 815 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 816 #endif