2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
16 #include <asm/omap_sec_common.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/dra7xx_iodelay.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sata.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/omap.h>
27 #include <environment.h>
29 #include <linux/usb/gadget.h>
30 #include <dwc3-uboot.h>
31 #include <dwc3-omap-uboot.h>
32 #include <ti-usb-phy-uboot.h>
34 #include "../common/board_detect.h"
37 #define board_is_x15() board_ti_is("BBRDX15_")
38 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
39 (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
40 #define board_is_am572x_evm() board_ti_is("AM572PM_")
41 #define board_is_am572x_evm_reva3() \
42 (board_ti_is("AM572PM_") && \
43 (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
44 #define board_is_am572x_idk() board_ti_is("AM572IDK")
46 #ifdef CONFIG_DRIVER_TI_CPSW
50 DECLARE_GLOBAL_DATA_PTR;
53 #define GPIO_DDR_VTT_EN 203
55 #define SYSINFO_BOARD_NAME_MAX_LEN 45
57 const struct omap_sysinfo sysinfo = {
58 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
61 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
62 .dmm_lisa_map_3 = 0x80740300,
66 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
68 *dmm_lisa_regs = &beagle_x15_lisa_regs;
71 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
72 .sdram_config_init = 0x61851b32,
73 .sdram_config = 0x61851b32,
74 .sdram_config2 = 0x08000000,
75 .ref_ctrl = 0x000040F1,
76 .ref_ctrl_final = 0x00001035,
77 .sdram_tim1 = 0xcccf36ab,
78 .sdram_tim2 = 0x308f7fda,
79 .sdram_tim3 = 0x409f88a8,
80 .read_idle_ctrl = 0x00050000,
81 .zq_config = 0x5007190b,
82 .temp_alert_config = 0x00000000,
83 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
84 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
85 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
86 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
87 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
88 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
89 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
90 .emif_rd_wr_lvl_rmp_win = 0x00000000,
91 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
92 .emif_rd_wr_lvl_ctl = 0x00000000,
93 .emif_rd_wr_exec_thresh = 0x00000305
96 /* Ext phy ctrl regs 1-35 */
97 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
135 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
136 .sdram_config_init = 0x61851b32,
137 .sdram_config = 0x61851b32,
138 .sdram_config2 = 0x08000000,
139 .ref_ctrl = 0x000040F1,
140 .ref_ctrl_final = 0x00001035,
141 .sdram_tim1 = 0xcccf36b3,
142 .sdram_tim2 = 0x308f7fda,
143 .sdram_tim3 = 0x407f88a8,
144 .read_idle_ctrl = 0x00050000,
145 .zq_config = 0x5007190b,
146 .temp_alert_config = 0x00000000,
147 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
148 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
149 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
150 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
151 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
152 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
153 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
154 .emif_rd_wr_lvl_rmp_win = 0x00000000,
155 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
156 .emif_rd_wr_lvl_ctl = 0x00000000,
157 .emif_rd_wr_exec_thresh = 0x00000305
160 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
198 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
202 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
205 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
210 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
214 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
215 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
218 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
219 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
224 struct vcores_data beagle_x15_volts = {
225 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
226 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
227 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
228 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
229 .mpu.pmic = &tps659038,
230 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
232 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
233 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
234 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
235 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
236 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
237 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
238 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
239 .eve.addr = TPS659038_REG_ADDR_SMPS45,
240 .eve.pmic = &tps659038,
241 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
243 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
244 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
245 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
246 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
247 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
248 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
249 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
250 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
251 .gpu.pmic = &tps659038,
252 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
254 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
255 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
256 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
257 .core.addr = TPS659038_REG_ADDR_SMPS6,
258 .core.pmic = &tps659038,
260 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
261 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
262 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
263 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
264 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
265 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
266 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
267 .iva.addr = TPS659038_REG_ADDR_SMPS45,
268 .iva.pmic = &tps659038,
269 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
272 struct vcores_data am572x_idk_volts = {
273 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
274 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
275 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
276 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
277 .mpu.pmic = &tps659038,
278 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
280 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
281 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
282 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
283 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
284 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
285 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
286 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
287 .eve.addr = TPS659038_REG_ADDR_SMPS45,
288 .eve.pmic = &tps659038,
289 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
291 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
292 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
293 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
294 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
295 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
296 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
297 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
298 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
299 .gpu.pmic = &tps659038,
300 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
302 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
303 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
304 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
305 .core.addr = TPS659038_REG_ADDR_SMPS7,
306 .core.pmic = &tps659038,
308 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
309 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
310 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
311 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
312 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
313 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
314 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
315 .iva.addr = TPS659038_REG_ADDR_SMPS8,
316 .iva.pmic = &tps659038,
317 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
320 int get_voltrail_opp(int rail_offset)
324 switch (rail_offset) {
335 opp = DRA7_DSPEVE_OPP;
348 #ifdef CONFIG_SPL_BUILD
349 /* No env to setup for SPL */
350 static inline void setup_board_eeprom_env(void) { }
352 /* Override function to read eeprom information */
353 void do_board_detect(void)
357 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
358 CONFIG_EEPROM_CHIP_ADDRESS);
360 printf("ti_i2c_eeprom_init failed %d\n", rc);
363 #else /* CONFIG_SPL_BUILD */
365 /* Override function to read eeprom information: actual i2c read done by SPL*/
366 void do_board_detect(void)
371 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
372 CONFIG_EEPROM_CHIP_ADDRESS);
374 printf("ti_i2c_eeprom_init failed %d\n", rc);
377 bname = "BeagleBoard X15";
378 else if (board_is_am572x_evm())
379 bname = "AM572x EVM";
380 else if (board_is_am572x_idk())
381 bname = "AM572x IDK";
384 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
385 "Board: %s REV %s\n", bname, board_ti_get_rev());
388 static void setup_board_eeprom_env(void)
390 char *name = "beagle_x15";
393 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
394 CONFIG_EEPROM_CHIP_ADDRESS);
398 if (board_is_x15()) {
399 if (board_is_x15_revb1())
400 name = "beagle_x15_revb1";
403 } else if (board_is_am572x_evm()) {
404 if (board_is_am572x_evm_reva3())
405 name = "am57xx_evm_reva3";
408 } else if (board_is_am572x_idk()) {
411 printf("Unidentified board claims %s in eeprom header\n",
412 board_ti_get_name());
416 set_board_info_env(name);
419 #endif /* CONFIG_SPL_BUILD */
421 void vcores_init(void)
423 if (board_is_am572x_idk())
424 *omap_vcores = &am572x_idk_volts;
426 *omap_vcores = &beagle_x15_volts;
429 void hw_data_init(void)
431 *prcm = &dra7xx_prcm;
432 *dplls_data = &dra7xx_dplls;
433 *ctrl = &dra7xx_ctrl;
439 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
444 int board_late_init(void)
446 setup_board_eeprom_env();
449 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
450 * This is the POWERHOLD-in-Low behavior.
452 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
455 * Default FIT boot on HS devices. Non FIT images are not allowed
458 if (get_device_type() == HS_DEVICE)
459 setenv("boot_fit", "1");
464 void set_muxconf_regs(void)
466 do_set_mux32((*ctrl)->control_padconf_core_base,
467 early_padconf, ARRAY_SIZE(early_padconf));
470 #ifdef CONFIG_IODELAY_RECALIBRATION
471 void recalibrate_iodelay(void)
473 const struct pad_conf_entry *pconf;
474 const struct iodelay_cfg_entry *iod;
475 int pconf_sz, iod_sz;
478 if (board_is_am572x_idk()) {
479 pconf = core_padconf_array_essential_am572x_idk;
480 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
481 iod = iodelay_cfg_array_am572x_idk;
482 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
484 /* Common for X15/GPEVM */
485 pconf = core_padconf_array_essential_x15;
486 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
487 /* There never was an SR1.0 X15.. So.. */
488 if (omap_revision() == DRA752_ES1_1) {
489 iod = iodelay_cfg_array_x15_sr1_1;
490 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
492 /* Since full production should switch to SR2.0 */
493 iod = iodelay_cfg_array_x15_sr2_0;
494 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
498 /* Setup I/O isolation */
499 ret = __recalibrate_iodelay_start();
503 /* Do the muxing here */
504 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
506 /* Now do the weird minor deltas that should be safe */
507 if (board_is_x15() || board_is_am572x_evm()) {
508 if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
509 pconf = core_padconf_array_delta_x15_sr2_0;
510 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
512 pconf = core_padconf_array_delta_x15_sr1_1;
513 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
515 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
518 /* Setup IOdelay configuration */
519 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
521 /* Closeup.. remove isolation */
522 __recalibrate_iodelay_end(ret);
526 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
527 int board_mmc_init(bd_t *bis)
529 omap_mmc_init(0, 0, 0, -1, -1);
530 omap_mmc_init(1, 0, 0, -1, -1);
535 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
536 int spl_start_uboot(void)
538 /* break into full u-boot on 'c' */
539 if (serial_tstc() && serial_getc() == 'c')
542 #ifdef CONFIG_SPL_ENV_SUPPORT
545 if (getenv_yesno("boot_os") != 1)
553 #ifdef CONFIG_USB_DWC3
554 static struct dwc3_device usb_otg_ss2 = {
555 .maximum_speed = USB_SPEED_HIGH,
556 .base = DRA7_USB_OTG_SS2_BASE,
557 .tx_fifo_resize = false,
561 static struct dwc3_omap_device usb_otg_ss2_glue = {
562 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
563 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
567 static struct ti_usb_phy_device usb_phy2_device = {
568 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
572 int usb_gadget_handle_interrupts(int index)
576 status = dwc3_omap_uboot_interrupt_status(index);
578 dwc3_uboot_handle_interrupt(index);
582 #endif /* CONFIG_USB_DWC3 */
584 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
585 int board_usb_init(int index, enum usb_init_type init)
587 enable_usb_clocks(index);
590 if (init == USB_INIT_DEVICE) {
591 printf("port %d can't be used as device\n", index);
592 disable_usb_clocks(index);
597 if (init == USB_INIT_DEVICE) {
598 #ifdef CONFIG_USB_DWC3
599 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
600 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
601 ti_usb_phy_uboot_init(&usb_phy2_device);
602 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
603 dwc3_uboot_init(&usb_otg_ss2);
606 printf("port %d can't be used as host\n", index);
607 disable_usb_clocks(index);
613 printf("Invalid Controller Index\n");
619 int board_usb_cleanup(int index, enum usb_init_type init)
621 #ifdef CONFIG_USB_DWC3
625 if (init == USB_INIT_DEVICE) {
626 ti_usb_phy_uboot_exit(index);
627 dwc3_uboot_exit(index);
628 dwc3_omap_uboot_exit(index);
632 printf("Invalid Controller Index\n");
635 disable_usb_clocks(index);
638 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
640 #ifdef CONFIG_DRIVER_TI_CPSW
642 /* Delay value to add to calibrated value */
643 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
644 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
645 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
646 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
647 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
648 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
649 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
650 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
651 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
652 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
654 static void cpsw_control(int enabled)
656 /* VTP can be added here */
659 static struct cpsw_slave_data cpsw_slaves[] = {
661 .slave_reg_ofs = 0x208,
662 .sliver_reg_ofs = 0xd80,
666 .slave_reg_ofs = 0x308,
667 .sliver_reg_ofs = 0xdc0,
672 static struct cpsw_platform_data cpsw_data = {
673 .mdio_base = CPSW_MDIO_BASE,
674 .cpsw_base = CPSW_BASE,
677 .cpdma_reg_ofs = 0x800,
679 .slave_data = cpsw_slaves,
680 .ale_reg_ofs = 0xd00,
682 .host_port_reg_ofs = 0x108,
683 .hw_stats_reg_ofs = 0x900,
684 .bd_ram_ofs = 0x2000,
685 .mac_control = (1 << 5),
686 .control = cpsw_control,
688 .version = CPSW_CTRL_VERSION_2,
691 static u64 mac_to_u64(u8 mac[6])
696 for (i = 0; i < 6; i++) {
704 static void u64_to_mac(u64 addr, u8 mac[6])
714 int board_eth_init(bd_t *bis)
718 uint32_t mac_hi, mac_lo;
722 u8 mac_addr1[6], mac_addr2[6];
725 /* try reading mac address from efuse */
726 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
727 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
728 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
729 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
730 mac_addr[2] = mac_hi & 0xFF;
731 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
732 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
733 mac_addr[5] = mac_lo & 0xFF;
735 if (!getenv("ethaddr")) {
736 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
738 if (is_valid_ethaddr(mac_addr))
739 eth_setenv_enetaddr("ethaddr", mac_addr);
742 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
743 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
744 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
745 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
746 mac_addr[2] = mac_hi & 0xFF;
747 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
748 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
749 mac_addr[5] = mac_lo & 0xFF;
751 if (!getenv("eth1addr")) {
752 if (is_valid_ethaddr(mac_addr))
753 eth_setenv_enetaddr("eth1addr", mac_addr);
756 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
758 writel(ctrl_val, (*ctrl)->control_core_control_io1);
760 /* The phy address for the AM572x IDK are different than x15 */
761 if (board_is_am572x_idk()) {
762 cpsw_data.slave_data[0].phy_addr = 0;
763 cpsw_data.slave_data[1].phy_addr = 1;
766 ret = cpsw_register(&cpsw_data);
768 printf("Error %d registering CPSW switch\n", ret);
771 * Export any Ethernet MAC addresses from EEPROM.
772 * On AM57xx the 2 MAC addresses define the address range
774 board_ti_get_eth_mac_addr(0, mac_addr1);
775 board_ti_get_eth_mac_addr(1, mac_addr2);
777 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
778 mac1 = mac_to_u64(mac_addr1);
779 mac2 = mac_to_u64(mac_addr2);
781 /* must contain an address range */
782 num_macs = mac2 - mac1 + 1;
783 /* <= 50 to protect against user programming error */
784 if (num_macs > 0 && num_macs <= 50) {
785 for (i = 0; i < num_macs; i++) {
786 u64_to_mac(mac1 + i, mac_addr);
787 if (is_valid_ethaddr(mac_addr)) {
788 eth_setenv_enetaddr_by_index("eth",
800 #ifdef CONFIG_BOARD_EARLY_INIT_F
801 /* VTT regulator enable */
802 static inline void vtt_regulator_enable(void)
804 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
807 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
808 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
811 int board_early_init_f(void)
813 vtt_regulator_enable();
818 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
819 int ft_board_setup(void *blob, bd_t *bd)
821 ft_cpu_setup(blob, bd);
827 #ifdef CONFIG_SPL_LOAD_FIT
828 int board_fit_config_name_match(const char *name)
830 if (board_is_x15()) {
831 if (board_is_x15_revb1()) {
832 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
834 } else if (!strcmp(name, "am57xx-beagle-x15")) {
837 } else if (board_is_am572x_evm() &&
838 !strcmp(name, "am57xx-beagle-x15")) {
840 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
848 #ifdef CONFIG_TI_SECURE_DEVICE
849 void board_fit_image_post_process(void **p_image, size_t *p_size)
851 secure_boot_verify_image(p_image, p_size);
854 void board_tee_image_process(ulong tee_image, size_t tee_size)
856 secure_tee_install((u32)tee_image);
859 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);