board/ti/am57xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   4  *
   5  * Author: Felipe Balbi <balbi@ti.com>
   6  *
   7  * Based on board/ti/dra7xx/evm.c
   8  */
   9
  10 #include <common.h>
  11 #include <palmas.h>
  12 #include <sata.h>
  13 #include <usb.h>
  14 #include <asm/omap_common.h>
  15 #include <asm/omap_sec_common.h>
  16 #include <asm/emif.h>
  17 #include <asm/gpio.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/dra7xx_iodelay.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sata.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/omap.h>
  26 #include <environment.h>
  27 #include <usb.h>
  28 #include <linux/usb/gadget.h>
  29 #include <dwc3-uboot.h>
  30 #include <dwc3-omap-uboot.h>
  31 #include <ti-usb-phy-uboot.h>
  32 #include <mmc.h>
  33
  34 #include "../common/board_detect.h"
  35 #include "mux_data.h"
  36
  37 #define board_is_x15()          board_ti_is("BBRDX15_")
  38 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  39                                  !strncmp("B.10", board_ti_get_rev(), 3))
  40 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  41                                  !strncmp("C.00", board_ti_get_rev(), 3))
  42 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  43 #define board_is_am572x_evm_reva3()     \
  44                                 (board_ti_is("AM572PM_") && \
  45                                  !strncmp("A.30", board_ti_get_rev(), 3))
  46 #define board_is_am574x_idk()   board_ti_is("AM574IDK")
  47 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  48 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  49
  50 #ifdef CONFIG_DRIVER_TI_CPSW
  51 #include <cpsw.h>
  52 #endif
  53
  54 DECLARE_GLOBAL_DATA_PTR;
  55
  56 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  57 /* GPIO 7_11 */
  58 #define GPIO_DDR_VTT_EN 203
  59
  60 /* Touch screen controller to identify the LCD */
  61 #define OSD_TS_FT_BUS_ADDRESS   0
  62 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  63 #define OSD_TS_FT_REG_ID        0xA3
  64 /*
  65  * Touchscreen IDs for various OSD panels
  66  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  67  */
  68 /* Used on newer osd101t2587 Panels */
  69 #define OSD_TS_FT_ID_5x46       0x54
  70 /* Used on older osd101t2045 Panels */
  71 #define OSD_TS_FT_ID_5606       0x08
  72
  73 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  74
  75 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  76 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  77
  78 const struct omap_sysinfo sysinfo = {
  79         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  80 };
  81
  82 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  83         .dmm_lisa_map_3 = 0x80740300,
  84         .is_ma_present  = 0x1
  85 };
  86
  87 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  88         .dmm_lisa_map_3 = 0x80640100,
  89         .is_ma_present  = 0x1
  90 };
  91
  92 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
  93         .dmm_lisa_map_2 = 0xc0600200,
  94         .dmm_lisa_map_3 = 0x80600100,
  95         .is_ma_present  = 0x1
  96 };
  97
  98 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  99 {
 100         if (board_is_am571x_idk())
 101                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
 102         else if (board_is_am574x_idk())
 103                 *dmm_lisa_regs = &am574x_idk_lisa_regs;
 104         else
 105                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
 106 }
 107
 108 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 109         .sdram_config_init              = 0x61851b32,
 110         .sdram_config                   = 0x61851b32,
 111         .sdram_config2                  = 0x08000000,
 112         .ref_ctrl                       = 0x000040F1,
 113         .ref_ctrl_final                 = 0x00001035,
 114         .sdram_tim1                     = 0xcccf36ab,
 115         .sdram_tim2                     = 0x308f7fda,
 116         .sdram_tim3                     = 0x409f88a8,
 117         .read_idle_ctrl                 = 0x00050000,
 118         .zq_config                      = 0x5007190b,
 119         .temp_alert_config              = 0x00000000,
 120         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 121         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 122         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 123         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 124         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 125         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 126         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 127         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 128         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 129         .emif_rd_wr_lvl_ctl             = 0x00000000,
 130         .emif_rd_wr_exec_thresh         = 0x00000305
 131 };
 132
 133 /* Ext phy ctrl regs 1-35 */
 134 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 135         0x10040100,
 136         0x00910091,
 137         0x00950095,
 138         0x009B009B,
 139         0x009E009E,
 140         0x00980098,
 141         0x00340034,
 142         0x00350035,
 143         0x00340034,
 144         0x00310031,
 145         0x00340034,
 146         0x007F007F,
 147         0x007F007F,
 148         0x007F007F,
 149         0x007F007F,
 150         0x007F007F,
 151         0x00480048,
 152         0x004A004A,
 153         0x00520052,
 154         0x00550055,
 155         0x00500050,
 156         0x00000000,
 157         0x00600020,
 158         0x40011080,
 159         0x08102040,
 160         0x0,
 161         0x0,
 162         0x0,
 163         0x0,
 164         0x0,
 165         0x0,
 166         0x0,
 167         0x0,
 168         0x0,
 169         0x0
 170 };
 171
 172 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 173         .sdram_config_init              = 0x61851b32,
 174         .sdram_config                   = 0x61851b32,
 175         .sdram_config2                  = 0x08000000,
 176         .ref_ctrl                       = 0x000040F1,
 177         .ref_ctrl_final                 = 0x00001035,
 178         .sdram_tim1                     = 0xcccf36b3,
 179         .sdram_tim2                     = 0x308f7fda,
 180         .sdram_tim3                     = 0x407f88a8,
 181         .read_idle_ctrl                 = 0x00050000,
 182         .zq_config                      = 0x5007190b,
 183         .temp_alert_config              = 0x00000000,
 184         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 185         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 186         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 187         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 188         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 189         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 190         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 191         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 192         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 193         .emif_rd_wr_lvl_ctl             = 0x00000000,
 194         .emif_rd_wr_exec_thresh         = 0x00000305
 195 };
 196
 197 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 198         0x10040100,
 199         0x00910091,
 200         0x00950095,
 201         0x009B009B,
 202         0x009E009E,
 203         0x00980098,
 204         0x00340034,
 205         0x00350035,
 206         0x00340034,
 207         0x00310031,
 208         0x00340034,
 209         0x007F007F,
 210         0x007F007F,
 211         0x007F007F,
 212         0x007F007F,
 213         0x007F007F,
 214         0x00480048,
 215         0x004A004A,
 216         0x00520052,
 217         0x00550055,
 218         0x00500050,
 219         0x00000000,
 220         0x00600020,
 221         0x40011080,
 222         0x08102040,
 223         0x0,
 224         0x0,
 225         0x0,
 226         0x0,
 227         0x0,
 228         0x0,
 229         0x0,
 230         0x0,
 231         0x0,
 232         0x0
 233 };
 234
 235 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 236         .sdram_config_init              = 0x61863332,
 237         .sdram_config                   = 0x61863332,
 238         .sdram_config2                  = 0x08000000,
 239         .ref_ctrl                       = 0x0000514d,
 240         .ref_ctrl_final                 = 0x0000144a,
 241         .sdram_tim1                     = 0xd333887c,
 242         .sdram_tim2                     = 0x30b37fe3,
 243         .sdram_tim3                     = 0x409f8ad8,
 244         .read_idle_ctrl                 = 0x00050000,
 245         .zq_config                      = 0x5007190b,
 246         .temp_alert_config              = 0x00000000,
 247         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 248         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 249         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 250         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 251         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 252         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 253         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 254         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 255         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 256         .emif_rd_wr_lvl_ctl             = 0x00000000,
 257         .emif_rd_wr_exec_thresh         = 0x00000305
 258 };
 259
 260 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
 261         .sdram_config_init              = 0x61863332,
 262         .sdram_config                   = 0x61863332,
 263         .sdram_config2                  = 0x08000000,
 264         .ref_ctrl                       = 0x0000514d,
 265         .ref_ctrl_final                 = 0x0000144a,
 266         .sdram_tim1                     = 0xd333887c,
 267         .sdram_tim2                     = 0x30b37fe3,
 268         .sdram_tim3                     = 0x409f8ad8,
 269         .read_idle_ctrl                 = 0x00050000,
 270         .zq_config                      = 0x5007190b,
 271         .temp_alert_config              = 0x00000000,
 272         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 273         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 274         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 275         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 276         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 277         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 278         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 279         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 280         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 281         .emif_rd_wr_lvl_ctl             = 0x00000000,
 282         .emif_rd_wr_exec_thresh         = 0x00000305,
 283         .emif_ecc_ctrl_reg              = 0xD0000001,
 284         .emif_ecc_address_range_1       = 0x3FFF0000,
 285         .emif_ecc_address_range_2       = 0x00000000
 286 };
 287
 288 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 289 {
 290         switch (emif_nr) {
 291         case 1:
 292                 if (board_is_am571x_idk())
 293                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 294                 else if (board_is_am574x_idk())
 295                         *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
 296                 else
 297                         *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 298                 break;
 299         case 2:
 300                 if (board_is_am574x_idk())
 301                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 302                 else
 303                         *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 304                 break;
 305         }
 306 }
 307
 308 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 309 {
 310         switch (emif_nr) {
 311         case 1:
 312                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 313                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 314                 break;
 315         case 2:
 316                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 317                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 318                 break;
 319         }
 320 }
 321
 322 struct vcores_data beagle_x15_volts = {
 323         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 324         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 325         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 326         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 327         .mpu.pmic               = &tps659038,
 328         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 329
 330         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 331         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 332         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 333         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 334         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 335         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 336         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 337         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 338         .eve.pmic               = &tps659038,
 339         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 340
 341         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 342         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 343         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 344         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 345         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 346         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 347         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 348         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 349         .gpu.pmic               = &tps659038,
 350         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 351
 352         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 353         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 354         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 355         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 356         .core.pmic              = &tps659038,
 357
 358         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 359         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 360         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 361         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 362         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 363         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 364         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 365         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 366         .iva.pmic               = &tps659038,
 367         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 368 };
 369
 370 struct vcores_data am572x_idk_volts = {
 371         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 372         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 373         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 374         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 375         .mpu.pmic               = &tps659038,
 376         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 377
 378         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 379         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 380         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 381         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 382         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 383         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 384         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 385         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 386         .eve.pmic               = &tps659038,
 387         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 388
 389         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 390         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 391         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 392         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 393         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 394         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 395         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 396         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 397         .gpu.pmic               = &tps659038,
 398         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 399
 400         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 401         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 402         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 403         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 404         .core.pmic              = &tps659038,
 405
 406         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 407         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 408         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 409         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 410         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 411         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 412         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 413         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 414         .iva.pmic               = &tps659038,
 415         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 416 };
 417
 418 struct vcores_data am571x_idk_volts = {
 419         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 420         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 421         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 422         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 423         .mpu.pmic               = &tps659038,
 424         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 425
 426         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 427         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 428         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 429         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 430         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 431         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 432         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 433         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 434         .eve.pmic               = &tps659038,
 435         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 436
 437         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 438         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 439         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 440         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 441         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 442         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 443         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 444         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 445         .gpu.pmic               = &tps659038,
 446         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 447
 448         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 449         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 450         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 451         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 452         .core.pmic              = &tps659038,
 453
 454         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 455         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 456         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 457         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 458         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 459         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 460         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 461         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 462         .iva.pmic               = &tps659038,
 463         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 464 };
 465
 466 int get_voltrail_opp(int rail_offset)
 467 {
 468         int opp;
 469
 470         switch (rail_offset) {
 471         case VOLT_MPU:
 472                 opp = DRA7_MPU_OPP;
 473                 break;
 474         case VOLT_CORE:
 475                 opp = DRA7_CORE_OPP;
 476                 break;
 477         case VOLT_GPU:
 478                 opp = DRA7_GPU_OPP;
 479                 break;
 480         case VOLT_EVE:
 481                 opp = DRA7_DSPEVE_OPP;
 482                 break;
 483         case VOLT_IVA:
 484                 opp = DRA7_IVA_OPP;
 485                 break;
 486         default:
 487                 opp = OPP_NOM;
 488         }
 489
 490         return opp;
 491 }
 492
 493
 494 #ifdef CONFIG_SPL_BUILD
 495 /* No env to setup for SPL */
 496 static inline void setup_board_eeprom_env(void) { }
 497
 498 /* Override function to read eeprom information */
 499 void do_board_detect(void)
 500 {
 501         int rc;
 502
 503         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 504                                   CONFIG_EEPROM_CHIP_ADDRESS);
 505         if (rc)
 506                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 507 }
 508
 509 #else   /* CONFIG_SPL_BUILD */
 510
 511 /* Override function to read eeprom information: actual i2c read done by SPL*/
 512 void do_board_detect(void)
 513 {
 514         char *bname = NULL;
 515         int rc;
 516
 517         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 518                                   CONFIG_EEPROM_CHIP_ADDRESS);
 519         if (rc)
 520                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 521
 522         if (board_is_x15())
 523                 bname = "BeagleBoard X15";
 524         else if (board_is_am572x_evm())
 525                 bname = "AM572x EVM";
 526         else if (board_is_am574x_idk())
 527                 bname = "AM574x IDK";
 528         else if (board_is_am572x_idk())
 529                 bname = "AM572x IDK";
 530         else if (board_is_am571x_idk())
 531                 bname = "AM571x IDK";
 532
 533         if (bname)
 534                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 535                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 536 }
 537
 538 static void setup_board_eeprom_env(void)
 539 {
 540         char *name = "beagle_x15";
 541         int rc;
 542
 543         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 544                                   CONFIG_EEPROM_CHIP_ADDRESS);
 545         if (rc)
 546                 goto invalid_eeprom;
 547
 548         if (board_is_x15()) {
 549                 if (board_is_x15_revb1())
 550                         name = "beagle_x15_revb1";
 551                 else if (board_is_x15_revc())
 552                         name = "beagle_x15_revc";
 553                 else
 554                         name = "beagle_x15";
 555         } else if (board_is_am572x_evm()) {
 556                 if (board_is_am572x_evm_reva3())
 557                         name = "am57xx_evm_reva3";
 558                 else
 559                         name = "am57xx_evm";
 560         } else if (board_is_am574x_idk()) {
 561                 name = "am574x_idk";
 562         } else if (board_is_am572x_idk()) {
 563                 name = "am572x_idk";
 564         } else if (board_is_am571x_idk()) {
 565                 name = "am571x_idk";
 566         } else {
 567                 printf("Unidentified board claims %s in eeprom header\n",
 568                        board_ti_get_name());
 569         }
 570
 571 invalid_eeprom:
 572         set_board_info_env(name);
 573 }
 574
 575 #endif  /* CONFIG_SPL_BUILD */
 576
 577 void vcores_init(void)
 578 {
 579         if (board_is_am572x_idk() || board_is_am574x_idk())
 580                 *omap_vcores = &am572x_idk_volts;
 581         else if (board_is_am571x_idk())
 582                 *omap_vcores = &am571x_idk_volts;
 583         else
 584                 *omap_vcores = &beagle_x15_volts;
 585 }
 586
 587 void hw_data_init(void)
 588 {
 589         *prcm = &dra7xx_prcm;
 590         if (is_dra72x())
 591                 *dplls_data = &dra72x_dplls;
 592         else if (is_dra76x())
 593                 *dplls_data = &dra76x_dplls;
 594         else
 595                 *dplls_data = &dra7xx_dplls;
 596         *ctrl = &dra7xx_ctrl;
 597 }
 598
 599 bool am571x_idk_needs_lcd(void)
 600 {
 601         bool needs_lcd;
 602
 603         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 604         if (gpio_get_value(GPIO_ETH_LCD))
 605                 needs_lcd = false;
 606         else
 607                 needs_lcd = true;
 608
 609         gpio_free(GPIO_ETH_LCD);
 610
 611         return needs_lcd;
 612 }
 613
 614 int board_init(void)
 615 {
 616         gpmc_init();
 617         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 618
 619         return 0;
 620 }
 621
 622 void am57x_idk_lcd_detect(void)
 623 {
 624         int r = -ENODEV;
 625         char *idk_lcd = "no";
 626         struct udevice *dev;
 627
 628         /* Only valid for IDKs */
 629         if (board_is_x15() || board_is_am572x_evm())
 630                 return;
 631
 632         /* Only AM571x IDK has gpio control detect.. so check that */
 633         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 634                 goto out;
 635
 636         r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
 637                                     OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
 638         if (r) {
 639                 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
 640                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 641                        r);
 642                 /* AM572x IDK has no explicit settings for optional LCD kit */
 643                 if (board_is_am571x_idk())
 644                         printf("%s: Touch screen detect failed: %d!\n",
 645                                __func__, r);
 646                 goto out;
 647         }
 648
 649         /* Read FT ID */
 650         r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
 651         if (r < 0) {
 652                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 653                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 654                        OSD_TS_FT_REG_ID, r);
 655                 goto out;
 656         }
 657
 658         switch (r) {
 659         case OSD_TS_FT_ID_5606:
 660                 idk_lcd = "osd101t2045";
 661                 break;
 662         case OSD_TS_FT_ID_5x46:
 663                 idk_lcd = "osd101t2587";
 664                 break;
 665         default:
 666                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 667                        __func__, r);
 668                 /* we will let default be "no lcd" */
 669         }
 670 out:
 671         env_set("idk_lcd", idk_lcd);
 672         return;
 673 }
 674
 675 int board_late_init(void)
 676 {
 677         setup_board_eeprom_env();
 678         u8 val;
 679
 680         /*
 681          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 682          * This is the POWERHOLD-in-Low behavior.
 683          */
 684         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 685
 686         /*
 687          * Default FIT boot on HS devices. Non FIT images are not allowed
 688          * on HS devices.
 689          */
 690         if (get_device_type() == HS_DEVICE)
 691                 env_set("boot_fit", "1");
 692
 693         /*
 694          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 695          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 696          * PMIC Power off. So to be on the safer side set it back
 697          * to POWERHOLD mode irrespective of the current state.
 698          */
 699         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 700                            &val);
 701         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 702         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 703                             val);
 704
 705         omap_die_id_serial();
 706         omap_set_fastboot_vars();
 707
 708         am57x_idk_lcd_detect();
 709
 710 #if !defined(CONFIG_SPL_BUILD)
 711         board_ti_set_ethaddr(2);
 712 #endif
 713
 714         return 0;
 715 }
 716
 717 void set_muxconf_regs(void)
 718 {
 719         do_set_mux32((*ctrl)->control_padconf_core_base,
 720                      early_padconf, ARRAY_SIZE(early_padconf));
 721 }
 722
 723 #ifdef CONFIG_IODELAY_RECALIBRATION
 724 void recalibrate_iodelay(void)
 725 {
 726         const struct pad_conf_entry *pconf;
 727         const struct iodelay_cfg_entry *iod, *delta_iod;
 728         int pconf_sz, iod_sz, delta_iod_sz = 0;
 729         int ret;
 730
 731         if (board_is_am572x_idk()) {
 732                 pconf = core_padconf_array_essential_am572x_idk;
 733                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 734                 iod = iodelay_cfg_array_am572x_idk;
 735                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 736         } else if (board_is_am574x_idk()) {
 737                 pconf = core_padconf_array_essential_am574x_idk;
 738                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
 739                 iod = iodelay_cfg_array_am574x_idk;
 740                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
 741         } else if (board_is_am571x_idk()) {
 742                 pconf = core_padconf_array_essential_am571x_idk;
 743                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 744                 iod = iodelay_cfg_array_am571x_idk;
 745                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 746         } else {
 747                 /* Common for X15/GPEVM */
 748                 pconf = core_padconf_array_essential_x15;
 749                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 750                 /* There never was an SR1.0 X15.. So.. */
 751                 if (omap_revision() == DRA752_ES1_1) {
 752                         iod = iodelay_cfg_array_x15_sr1_1;
 753                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 754                 } else {
 755                         /* Since full production should switch to SR2.0  */
 756                         iod = iodelay_cfg_array_x15_sr2_0;
 757                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 758                 }
 759         }
 760
 761         /* Setup I/O isolation */
 762         ret = __recalibrate_iodelay_start();
 763         if (ret)
 764                 goto err;
 765
 766         /* Do the muxing here */
 767         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 768
 769         /* Now do the weird minor deltas that should be safe */
 770         if (board_is_x15() || board_is_am572x_evm()) {
 771                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 772                     board_is_x15_revc()) {
 773                         pconf = core_padconf_array_delta_x15_sr2_0;
 774                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 775                 } else {
 776                         pconf = core_padconf_array_delta_x15_sr1_1;
 777                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 778                 }
 779                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 780         }
 781
 782         if (board_is_am571x_idk()) {
 783                 if (am571x_idk_needs_lcd()) {
 784                         pconf = core_padconf_array_vout_am571x_idk;
 785                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 786                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 787                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 788
 789                 } else {
 790                         pconf = core_padconf_array_icss1eth_am571x_idk;
 791                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 792                 }
 793                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 794         }
 795
 796         /* Setup IOdelay configuration */
 797         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 798         if (delta_iod_sz)
 799                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 800                                      delta_iod_sz);
 801
 802 err:
 803         /* Closeup.. remove isolation */
 804         __recalibrate_iodelay_end(ret);
 805 }
 806 #endif
 807
 808 #if defined(CONFIG_MMC)
 809 int board_mmc_init(bd_t *bis)
 810 {
 811         omap_mmc_init(0, 0, 0, -1, -1);
 812         omap_mmc_init(1, 0, 0, -1, -1);
 813         return 0;
 814 }
 815
 816 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
 817         .hw_rev = "rev11",
 818         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 819                             MMC_CAP(UHS_SDR104),
 820         .max_freq = 96000000,
 821 };
 822
 823 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
 824         .hw_rev = "rev11",
 825         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 826                             MMC_CAP(UHS_SDR104) |
 827                             MMC_CAP(UHS_SDR50),
 828         .max_freq = 48000000,
 829 };
 830
 831 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 832 {
 833         switch (omap_revision()) {
 834         case DRA752_ES1_0:
 835         case DRA752_ES1_1:
 836                 if (addr == OMAP_HSMMC1_BASE)
 837                         return &am57x_es1_1_mmc1_fixups;
 838                 else
 839                         return &am57x_es1_1_mmc23_fixups;
 840         default:
 841                 return NULL;
 842         }
 843 }
 844 #endif
 845
 846 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 847 int spl_start_uboot(void)
 848 {
 849         /* break into full u-boot on 'c' */
 850         if (serial_tstc() && serial_getc() == 'c')
 851                 return 1;
 852
 853 #ifdef CONFIG_SPL_ENV_SUPPORT
 854         env_init();
 855         env_load();
 856         if (env_get_yesno("boot_os") != 1)
 857                 return 1;
 858 #endif
 859
 860         return 0;
 861 }
 862 #endif
 863
 864 #ifdef CONFIG_USB_DWC3
 865 static struct dwc3_device usb_otg_ss2 = {
 866         .maximum_speed = USB_SPEED_HIGH,
 867         .base = DRA7_USB_OTG_SS2_BASE,
 868         .tx_fifo_resize = false,
 869         .index = 1,
 870 };
 871
 872 static struct dwc3_omap_device usb_otg_ss2_glue = {
 873         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 874         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 875         .index = 1,
 876 };
 877
 878 static struct ti_usb_phy_device usb_phy2_device = {
 879         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 880         .index = 1,
 881 };
 882
 883 int usb_gadget_handle_interrupts(int index)
 884 {
 885         u32 status;
 886
 887         status = dwc3_omap_uboot_interrupt_status(index);
 888         if (status)
 889                 dwc3_uboot_handle_interrupt(index);
 890
 891         return 0;
 892 }
 893 #endif /* CONFIG_USB_DWC3 */
 894
 895 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 896 int board_usb_init(int index, enum usb_init_type init)
 897 {
 898         enable_usb_clocks(index);
 899         switch (index) {
 900         case 0:
 901                 if (init == USB_INIT_DEVICE) {
 902                         printf("port %d can't be used as device\n", index);
 903                         disable_usb_clocks(index);
 904                         return -EINVAL;
 905                 }
 906                 break;
 907         case 1:
 908                 if (init == USB_INIT_DEVICE) {
 909 #ifdef CONFIG_USB_DWC3
 910                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 911                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 912                         ti_usb_phy_uboot_init(&usb_phy2_device);
 913                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 914                         dwc3_uboot_init(&usb_otg_ss2);
 915 #endif
 916                 } else {
 917                         printf("port %d can't be used as host\n", index);
 918                         disable_usb_clocks(index);
 919                         return -EINVAL;
 920                 }
 921
 922                 break;
 923         default:
 924                 printf("Invalid Controller Index\n");
 925         }
 926
 927         return 0;
 928 }
 929
 930 int board_usb_cleanup(int index, enum usb_init_type init)
 931 {
 932 #ifdef CONFIG_USB_DWC3
 933         switch (index) {
 934         case 0:
 935         case 1:
 936                 if (init == USB_INIT_DEVICE) {
 937                         ti_usb_phy_uboot_exit(index);
 938                         dwc3_uboot_exit(index);
 939                         dwc3_omap_uboot_exit(index);
 940                 }
 941                 break;
 942         default:
 943                 printf("Invalid Controller Index\n");
 944         }
 945 #endif
 946         disable_usb_clocks(index);
 947         return 0;
 948 }
 949 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 950
 951 #ifdef CONFIG_DRIVER_TI_CPSW
 952
 953 /* Delay value to add to calibrated value */
 954 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 955 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 956 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 957 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 958 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 959 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 960 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 961 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 962 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 963 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 964
 965 static void cpsw_control(int enabled)
 966 {
 967         /* VTP can be added here */
 968 }
 969
 970 static struct cpsw_slave_data cpsw_slaves[] = {
 971         {
 972                 .slave_reg_ofs  = 0x208,
 973                 .sliver_reg_ofs = 0xd80,
 974                 .phy_addr       = 1,
 975         },
 976         {
 977                 .slave_reg_ofs  = 0x308,
 978                 .sliver_reg_ofs = 0xdc0,
 979                 .phy_addr       = 2,
 980         },
 981 };
 982
 983 static struct cpsw_platform_data cpsw_data = {
 984         .mdio_base              = CPSW_MDIO_BASE,
 985         .cpsw_base              = CPSW_BASE,
 986         .mdio_div               = 0xff,
 987         .channels               = 8,
 988         .cpdma_reg_ofs          = 0x800,
 989         .slaves                 = 1,
 990         .slave_data             = cpsw_slaves,
 991         .ale_reg_ofs            = 0xd00,
 992         .ale_entries            = 1024,
 993         .host_port_reg_ofs      = 0x108,
 994         .hw_stats_reg_ofs       = 0x900,
 995         .bd_ram_ofs             = 0x2000,
 996         .mac_control            = (1 << 5),
 997         .control                = cpsw_control,
 998         .host_port_num          = 0,
 999         .version                = CPSW_CTRL_VERSION_2,
1000 };
1001
1002 static u64 mac_to_u64(u8 mac[6])
1003 {
1004         int i;
1005         u64 addr = 0;
1006
1007         for (i = 0; i < 6; i++) {
1008                 addr <<= 8;
1009                 addr |= mac[i];
1010         }
1011
1012         return addr;
1013 }
1014
1015 static void u64_to_mac(u64 addr, u8 mac[6])
1016 {
1017         mac[5] = addr;
1018         mac[4] = addr >> 8;
1019         mac[3] = addr >> 16;
1020         mac[2] = addr >> 24;
1021         mac[1] = addr >> 32;
1022         mac[0] = addr >> 40;
1023 }
1024
1025 int board_eth_init(bd_t *bis)
1026 {
1027         int ret;
1028         uint8_t mac_addr[6];
1029         uint32_t mac_hi, mac_lo;
1030         uint32_t ctrl_val;
1031         int i;
1032         u64 mac1, mac2;
1033         u8 mac_addr1[6], mac_addr2[6];
1034         int num_macs;
1035
1036         /* try reading mac address from efuse */
1037         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1038         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1039         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1040         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1041         mac_addr[2] = mac_hi & 0xFF;
1042         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1043         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1044         mac_addr[5] = mac_lo & 0xFF;
1045
1046         if (!env_get("ethaddr")) {
1047                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1048
1049                 if (is_valid_ethaddr(mac_addr))
1050                         eth_env_set_enetaddr("ethaddr", mac_addr);
1051         }
1052
1053         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1054         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1055         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1056         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1057         mac_addr[2] = mac_hi & 0xFF;
1058         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1059         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1060         mac_addr[5] = mac_lo & 0xFF;
1061
1062         if (!env_get("eth1addr")) {
1063                 if (is_valid_ethaddr(mac_addr))
1064                         eth_env_set_enetaddr("eth1addr", mac_addr);
1065         }
1066
1067         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1068         ctrl_val |= 0x22;
1069         writel(ctrl_val, (*ctrl)->control_core_control_io1);
1070
1071         /* The phy address for the AM57xx IDK are different than x15 */
1072         if (board_is_am572x_idk() || board_is_am571x_idk() ||
1073             board_is_am574x_idk()) {
1074                 cpsw_data.slave_data[0].phy_addr = 0;
1075                 cpsw_data.slave_data[1].phy_addr = 1;
1076         }
1077
1078         ret = cpsw_register(&cpsw_data);
1079         if (ret < 0)
1080                 printf("Error %d registering CPSW switch\n", ret);
1081
1082         /*
1083          * Export any Ethernet MAC addresses from EEPROM.
1084          * On AM57xx the 2 MAC addresses define the address range
1085          */
1086         board_ti_get_eth_mac_addr(0, mac_addr1);
1087         board_ti_get_eth_mac_addr(1, mac_addr2);
1088
1089         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1090                 mac1 = mac_to_u64(mac_addr1);
1091                 mac2 = mac_to_u64(mac_addr2);
1092
1093                 /* must contain an address range */
1094                 num_macs = mac2 - mac1 + 1;
1095                 /* <= 50 to protect against user programming error */
1096                 if (num_macs > 0 && num_macs <= 50) {
1097                         for (i = 0; i < num_macs; i++) {
1098                                 u64_to_mac(mac1 + i, mac_addr);
1099                                 if (is_valid_ethaddr(mac_addr)) {
1100                                         eth_env_set_enetaddr_by_index("eth",
1101                                                                       i + 2,
1102                                                                       mac_addr);
1103                                 }
1104                         }
1105                 }
1106         }
1107
1108         return ret;
1109 }
1110 #endif
1111
1112 #ifdef CONFIG_BOARD_EARLY_INIT_F
1113 /* VTT regulator enable */
1114 static inline void vtt_regulator_enable(void)
1115 {
1116         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1117                 return;
1118
1119         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1120         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1121 }
1122
1123 int board_early_init_f(void)
1124 {
1125         vtt_regulator_enable();
1126         return 0;
1127 }
1128 #endif
1129
1130 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1131 int ft_board_setup(void *blob, bd_t *bd)
1132 {
1133         ft_cpu_setup(blob, bd);
1134
1135         return 0;
1136 }
1137 #endif
1138
1139 #ifdef CONFIG_SPL_LOAD_FIT
1140 int board_fit_config_name_match(const char *name)
1141 {
1142         if (board_is_x15()) {
1143                 if (board_is_x15_revb1()) {
1144                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1145                                 return 0;
1146                 } else if (board_is_x15_revc()) {
1147                         if (!strcmp(name, "am57xx-beagle-x15-revc"))
1148                                 return 0;
1149                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1150                         return 0;
1151                 }
1152         } else if (board_is_am572x_evm() &&
1153                    !strcmp(name, "am57xx-beagle-x15")) {
1154                 return 0;
1155         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1156                 return 0;
1157         } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1158                 return 0;
1159         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1160                 return 0;
1161         }
1162
1163         return -1;
1164 }
1165 #endif
1166
1167 #ifdef CONFIG_TI_SECURE_DEVICE
1168 void board_fit_image_post_process(void **p_image, size_t *p_size)
1169 {
1170         secure_boot_verify_image(p_image, p_size);
1171 }
1172
1173 void board_tee_image_process(ulong tee_image, size_t tee_size)
1174 {
1175         secure_tee_install((u32)tee_image);
1176 }
1177
1178 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1179 int fastboot_set_reboot_flag(void)
1180 {
1181         printf("Setting reboot to fastboot flag ...\n");
1182         env_set("dofastboot", "1");
1183         env_save();
1184         return 0;
1185 }
1186 #endif
1187
1188 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1189 #endif