board/ti/am57xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   4  *
   5  * Author: Felipe Balbi <balbi@ti.com>
   6  *
   7  * Based on board/ti/dra7xx/evm.c
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/emif.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sata.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/omap.h>
  27 #include <usb.h>
  28 #include <linux/usb/gadget.h>
  29 #include <dwc3-uboot.h>
  30 #include <dwc3-omap-uboot.h>
  31 #include <ti-usb-phy-uboot.h>
  32 #include <mmc.h>
  33 #include <dm/uclass.h>
  34
  35 #include "../common/board_detect.h"
  36 #include "mux_data.h"
  37
  38 #define board_is_x15()          board_ti_is("BBRDX15_")
  39 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  40                                  !strncmp("B.10", board_ti_get_rev(), 3))
  41 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  42                                  !strncmp("C.00", board_ti_get_rev(), 3))
  43 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  44 #define board_is_am572x_evm_reva3()     \
  45                                 (board_ti_is("AM572PM_") && \
  46                                  !strncmp("A.30", board_ti_get_rev(), 3))
  47 #define board_is_am574x_idk()   board_ti_is("AM574IDK")
  48 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  49 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  50
  51 #ifdef CONFIG_DRIVER_TI_CPSW
  52 #include <cpsw.h>
  53 #endif
  54
  55 DECLARE_GLOBAL_DATA_PTR;
  56
  57 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  58 /* GPIO 7_11 */
  59 #define GPIO_DDR_VTT_EN 203
  60
  61 /* Touch screen controller to identify the LCD */
  62 #define OSD_TS_FT_BUS_ADDRESS   0
  63 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  64 #define OSD_TS_FT_REG_ID        0xA3
  65 /*
  66  * Touchscreen IDs for various OSD panels
  67  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  68  */
  69 /* Used on newer osd101t2587 Panels */
  70 #define OSD_TS_FT_ID_5x46       0x54
  71 /* Used on older osd101t2045 Panels */
  72 #define OSD_TS_FT_ID_5606       0x08
  73
  74 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  75
  76 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  77 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  78
  79 const struct omap_sysinfo sysinfo = {
  80         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  81 };
  82
  83 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  84         .dmm_lisa_map_3 = 0x80740300,
  85         .is_ma_present  = 0x1
  86 };
  87
  88 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  89         .dmm_lisa_map_3 = 0x80640100,
  90         .is_ma_present  = 0x1
  91 };
  92
  93 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
  94         .dmm_lisa_map_2 = 0xc0600200,
  95         .dmm_lisa_map_3 = 0x80600100,
  96         .is_ma_present  = 0x1
  97 };
  98
  99 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 100 {
 101         if (board_is_am571x_idk())
 102                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
 103         else if (board_is_am574x_idk())
 104                 *dmm_lisa_regs = &am574x_idk_lisa_regs;
 105         else
 106                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
 107 }
 108
 109 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 110         .sdram_config_init              = 0x61851b32,
 111         .sdram_config                   = 0x61851b32,
 112         .sdram_config2                  = 0x08000000,
 113         .ref_ctrl                       = 0x000040F1,
 114         .ref_ctrl_final                 = 0x00001035,
 115         .sdram_tim1                     = 0xcccf36ab,
 116         .sdram_tim2                     = 0x308f7fda,
 117         .sdram_tim3                     = 0x409f88a8,
 118         .read_idle_ctrl                 = 0x00050000,
 119         .zq_config                      = 0x5007190b,
 120         .temp_alert_config              = 0x00000000,
 121         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 122         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 123         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 124         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 125         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 126         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 127         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 128         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 129         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 130         .emif_rd_wr_lvl_ctl             = 0x00000000,
 131         .emif_rd_wr_exec_thresh         = 0x00000305
 132 };
 133
 134 /* Ext phy ctrl regs 1-35 */
 135 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 136         0x10040100,
 137         0x00910091,
 138         0x00950095,
 139         0x009B009B,
 140         0x009E009E,
 141         0x00980098,
 142         0x00340034,
 143         0x00350035,
 144         0x00340034,
 145         0x00310031,
 146         0x00340034,
 147         0x007F007F,
 148         0x007F007F,
 149         0x007F007F,
 150         0x007F007F,
 151         0x007F007F,
 152         0x00480048,
 153         0x004A004A,
 154         0x00520052,
 155         0x00550055,
 156         0x00500050,
 157         0x00000000,
 158         0x00600020,
 159         0x40011080,
 160         0x08102040,
 161         0x0,
 162         0x0,
 163         0x0,
 164         0x0,
 165         0x0,
 166         0x0,
 167         0x0,
 168         0x0,
 169         0x0,
 170         0x0
 171 };
 172
 173 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 174         .sdram_config_init              = 0x61851b32,
 175         .sdram_config                   = 0x61851b32,
 176         .sdram_config2                  = 0x08000000,
 177         .ref_ctrl                       = 0x000040F1,
 178         .ref_ctrl_final                 = 0x00001035,
 179         .sdram_tim1                     = 0xcccf36b3,
 180         .sdram_tim2                     = 0x308f7fda,
 181         .sdram_tim3                     = 0x407f88a8,
 182         .read_idle_ctrl                 = 0x00050000,
 183         .zq_config                      = 0x5007190b,
 184         .temp_alert_config              = 0x00000000,
 185         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 186         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 187         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 188         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 189         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 190         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 191         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 192         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 193         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 194         .emif_rd_wr_lvl_ctl             = 0x00000000,
 195         .emif_rd_wr_exec_thresh         = 0x00000305
 196 };
 197
 198 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 199         0x10040100,
 200         0x00910091,
 201         0x00950095,
 202         0x009B009B,
 203         0x009E009E,
 204         0x00980098,
 205         0x00340034,
 206         0x00350035,
 207         0x00340034,
 208         0x00310031,
 209         0x00340034,
 210         0x007F007F,
 211         0x007F007F,
 212         0x007F007F,
 213         0x007F007F,
 214         0x007F007F,
 215         0x00480048,
 216         0x004A004A,
 217         0x00520052,
 218         0x00550055,
 219         0x00500050,
 220         0x00000000,
 221         0x00600020,
 222         0x40011080,
 223         0x08102040,
 224         0x0,
 225         0x0,
 226         0x0,
 227         0x0,
 228         0x0,
 229         0x0,
 230         0x0,
 231         0x0,
 232         0x0,
 233         0x0
 234 };
 235
 236 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 237         .sdram_config_init              = 0x61863332,
 238         .sdram_config                   = 0x61863332,
 239         .sdram_config2                  = 0x08000000,
 240         .ref_ctrl                       = 0x0000514d,
 241         .ref_ctrl_final                 = 0x0000144a,
 242         .sdram_tim1                     = 0xd333887c,
 243         .sdram_tim2                     = 0x30b37fe3,
 244         .sdram_tim3                     = 0x409f8ad8,
 245         .read_idle_ctrl                 = 0x00050000,
 246         .zq_config                      = 0x5007190b,
 247         .temp_alert_config              = 0x00000000,
 248         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 249         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 250         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 251         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 252         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 253         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 254         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 255         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 256         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 257         .emif_rd_wr_lvl_ctl             = 0x00000000,
 258         .emif_rd_wr_exec_thresh         = 0x00000305
 259 };
 260
 261 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
 262         .sdram_config_init              = 0x61863332,
 263         .sdram_config                   = 0x61863332,
 264         .sdram_config2                  = 0x08000000,
 265         .ref_ctrl                       = 0x0000514d,
 266         .ref_ctrl_final                 = 0x0000144a,
 267         .sdram_tim1                     = 0xd333887c,
 268         .sdram_tim2                     = 0x30b37fe3,
 269         .sdram_tim3                     = 0x409f8ad8,
 270         .read_idle_ctrl                 = 0x00050000,
 271         .zq_config                      = 0x5007190b,
 272         .temp_alert_config              = 0x00000000,
 273         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 274         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 275         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 276         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 277         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 278         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 279         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 280         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 281         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 282         .emif_rd_wr_lvl_ctl             = 0x00000000,
 283         .emif_rd_wr_exec_thresh         = 0x00000305,
 284         .emif_ecc_ctrl_reg              = 0xD0000001,
 285         .emif_ecc_address_range_1       = 0x3FFF0000,
 286         .emif_ecc_address_range_2       = 0x00000000
 287 };
 288
 289 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 290 {
 291         switch (emif_nr) {
 292         case 1:
 293                 if (board_is_am571x_idk())
 294                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 295                 else if (board_is_am574x_idk())
 296                         *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
 297                 else
 298                         *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 299                 break;
 300         case 2:
 301                 if (board_is_am574x_idk())
 302                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 303                 else
 304                         *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 305                 break;
 306         }
 307 }
 308
 309 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 310 {
 311         switch (emif_nr) {
 312         case 1:
 313                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 314                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 315                 break;
 316         case 2:
 317                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 318                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 319                 break;
 320         }
 321 }
 322
 323 struct vcores_data beagle_x15_volts = {
 324         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 325         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 326         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 327         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 328         .mpu.pmic               = &tps659038,
 329         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 330
 331         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 332         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 333         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 334         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 335         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 336         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 337         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 338         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 339         .eve.pmic               = &tps659038,
 340         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 341
 342         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 343         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 344         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 345         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 346         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 347         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 348         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 349         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 350         .gpu.pmic               = &tps659038,
 351         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 352
 353         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 354         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 355         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 356         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 357         .core.pmic              = &tps659038,
 358
 359         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 360         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 361         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 362         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 363         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 364         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 365         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 366         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 367         .iva.pmic               = &tps659038,
 368         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 369 };
 370
 371 struct vcores_data am572x_idk_volts = {
 372         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 373         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 374         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 375         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 376         .mpu.pmic               = &tps659038,
 377         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 378
 379         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 380         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 381         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 382         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 383         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 384         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 385         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 386         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 387         .eve.pmic               = &tps659038,
 388         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 389
 390         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 391         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 392         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 393         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 394         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 395         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 396         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 397         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 398         .gpu.pmic               = &tps659038,
 399         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 400
 401         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 402         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 403         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 404         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 405         .core.pmic              = &tps659038,
 406
 407         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 408         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 409         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 410         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 411         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 412         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 413         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 414         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 415         .iva.pmic               = &tps659038,
 416         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 417 };
 418
 419 struct vcores_data am571x_idk_volts = {
 420         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 421         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 422         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 423         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 424         .mpu.pmic               = &tps659038,
 425         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 426
 427         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 428         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 429         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 430         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 431         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 432         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 433         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 434         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 435         .eve.pmic               = &tps659038,
 436         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 437
 438         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 439         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 440         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 441         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 442         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 443         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 444         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 445         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 446         .gpu.pmic               = &tps659038,
 447         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 448
 449         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 450         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 451         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 452         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 453         .core.pmic              = &tps659038,
 454
 455         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 456         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 457         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 458         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 459         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 460         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 461         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 462         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 463         .iva.pmic               = &tps659038,
 464         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 465 };
 466
 467 int get_voltrail_opp(int rail_offset)
 468 {
 469         int opp;
 470
 471         switch (rail_offset) {
 472         case VOLT_MPU:
 473                 opp = DRA7_MPU_OPP;
 474                 break;
 475         case VOLT_CORE:
 476                 opp = DRA7_CORE_OPP;
 477                 break;
 478         case VOLT_GPU:
 479                 opp = DRA7_GPU_OPP;
 480                 break;
 481         case VOLT_EVE:
 482                 opp = DRA7_DSPEVE_OPP;
 483                 break;
 484         case VOLT_IVA:
 485                 opp = DRA7_IVA_OPP;
 486                 break;
 487         default:
 488                 opp = OPP_NOM;
 489         }
 490
 491         return opp;
 492 }
 493
 494
 495 #ifdef CONFIG_SPL_BUILD
 496 /* No env to setup for SPL */
 497 static inline void setup_board_eeprom_env(void) { }
 498
 499 /* Override function to read eeprom information */
 500 void do_board_detect(void)
 501 {
 502         int rc;
 503
 504         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 505                                   CONFIG_EEPROM_CHIP_ADDRESS);
 506         if (rc)
 507                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 508 }
 509
 510 #else   /* CONFIG_SPL_BUILD */
 511
 512 /* Override function to read eeprom information: actual i2c read done by SPL*/
 513 void do_board_detect(void)
 514 {
 515         char *bname = NULL;
 516         int rc;
 517
 518         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 519                                   CONFIG_EEPROM_CHIP_ADDRESS);
 520         if (rc)
 521                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 522
 523         if (board_is_x15())
 524                 bname = "BeagleBoard X15";
 525         else if (board_is_am572x_evm())
 526                 bname = "AM572x EVM";
 527         else if (board_is_am574x_idk())
 528                 bname = "AM574x IDK";
 529         else if (board_is_am572x_idk())
 530                 bname = "AM572x IDK";
 531         else if (board_is_am571x_idk())
 532                 bname = "AM571x IDK";
 533
 534         if (bname)
 535                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 536                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 537 }
 538
 539 static void setup_board_eeprom_env(void)
 540 {
 541         char *name = "beagle_x15";
 542         int rc;
 543
 544         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 545                                   CONFIG_EEPROM_CHIP_ADDRESS);
 546         if (rc)
 547                 goto invalid_eeprom;
 548
 549         if (board_is_x15()) {
 550                 if (board_is_x15_revb1())
 551                         name = "beagle_x15_revb1";
 552                 else if (board_is_x15_revc())
 553                         name = "beagle_x15_revc";
 554                 else
 555                         name = "beagle_x15";
 556         } else if (board_is_am572x_evm()) {
 557                 if (board_is_am572x_evm_reva3())
 558                         name = "am57xx_evm_reva3";
 559                 else
 560                         name = "am57xx_evm";
 561         } else if (board_is_am574x_idk()) {
 562                 name = "am574x_idk";
 563         } else if (board_is_am572x_idk()) {
 564                 name = "am572x_idk";
 565         } else if (board_is_am571x_idk()) {
 566                 name = "am571x_idk";
 567         } else {
 568                 printf("Unidentified board claims %s in eeprom header\n",
 569                        board_ti_get_name());
 570         }
 571
 572 invalid_eeprom:
 573         set_board_info_env(name);
 574 }
 575
 576 #endif  /* CONFIG_SPL_BUILD */
 577
 578 void vcores_init(void)
 579 {
 580         if (board_is_am572x_idk() || board_is_am574x_idk())
 581                 *omap_vcores = &am572x_idk_volts;
 582         else if (board_is_am571x_idk())
 583                 *omap_vcores = &am571x_idk_volts;
 584         else
 585                 *omap_vcores = &beagle_x15_volts;
 586 }
 587
 588 void hw_data_init(void)
 589 {
 590         *prcm = &dra7xx_prcm;
 591         if (is_dra72x())
 592                 *dplls_data = &dra72x_dplls;
 593         else if (is_dra76x())
 594                 *dplls_data = &dra76x_dplls;
 595         else
 596                 *dplls_data = &dra7xx_dplls;
 597         *ctrl = &dra7xx_ctrl;
 598 }
 599
 600 bool am571x_idk_needs_lcd(void)
 601 {
 602         bool needs_lcd;
 603
 604         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 605         if (gpio_get_value(GPIO_ETH_LCD))
 606                 needs_lcd = false;
 607         else
 608                 needs_lcd = true;
 609
 610         gpio_free(GPIO_ETH_LCD);
 611
 612         return needs_lcd;
 613 }
 614
 615 int board_init(void)
 616 {
 617         gpmc_init();
 618         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 619
 620         return 0;
 621 }
 622
 623 void am57x_idk_lcd_detect(void)
 624 {
 625         int r = -ENODEV;
 626         char *idk_lcd = "no";
 627         struct udevice *dev;
 628
 629         /* Only valid for IDKs */
 630         if (board_is_x15() || board_is_am572x_evm())
 631                 return;
 632
 633         /* Only AM571x IDK has gpio control detect.. so check that */
 634         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 635                 goto out;
 636
 637         r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
 638                                     OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
 639         if (r) {
 640                 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
 641                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 642                        r);
 643                 /* AM572x IDK has no explicit settings for optional LCD kit */
 644                 if (board_is_am571x_idk())
 645                         printf("%s: Touch screen detect failed: %d!\n",
 646                                __func__, r);
 647                 goto out;
 648         }
 649
 650         /* Read FT ID */
 651         r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
 652         if (r < 0) {
 653                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 654                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 655                        OSD_TS_FT_REG_ID, r);
 656                 goto out;
 657         }
 658
 659         switch (r) {
 660         case OSD_TS_FT_ID_5606:
 661                 idk_lcd = "osd101t2045";
 662                 break;
 663         case OSD_TS_FT_ID_5x46:
 664                 idk_lcd = "osd101t2587";
 665                 break;
 666         default:
 667                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 668                        __func__, r);
 669                 /* we will let default be "no lcd" */
 670         }
 671 out:
 672         env_set("idk_lcd", idk_lcd);
 673         return;
 674 }
 675
 676 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 677 static int device_okay(const char *path)
 678 {
 679         int node;
 680
 681         node = fdt_path_offset(gd->fdt_blob, path);
 682         if (node < 0)
 683                 return 0;
 684
 685         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 686 }
 687 #endif
 688
 689 int board_late_init(void)
 690 {
 691         setup_board_eeprom_env();
 692         u8 val;
 693         struct udevice *dev;
 694
 695         /*
 696          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 697          * This is the POWERHOLD-in-Low behavior.
 698          */
 699         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 700
 701         /*
 702          * Default FIT boot on HS devices. Non FIT images are not allowed
 703          * on HS devices.
 704          */
 705         if (get_device_type() == HS_DEVICE)
 706                 env_set("boot_fit", "1");
 707
 708         /*
 709          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 710          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 711          * PMIC Power off. So to be on the safer side set it back
 712          * to POWERHOLD mode irrespective of the current state.
 713          */
 714         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 715                            &val);
 716         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 717         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 718                             val);
 719
 720         omap_die_id_serial();
 721         omap_set_fastboot_vars();
 722
 723         am57x_idk_lcd_detect();
 724
 725         /* Just probe the potentially supported cdce913 device */
 726         uclass_get_device(UCLASS_CLK, 0, &dev);
 727
 728 #if !defined(CONFIG_SPL_BUILD)
 729         board_ti_set_ethaddr(2);
 730 #endif
 731
 732 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 733         if (device_okay("/ocp/omap_dwc3_1@48880000"))
 734                 enable_usb_clocks(0);
 735         if (device_okay("/ocp/omap_dwc3_2@488c0000"))
 736                 enable_usb_clocks(1);
 737 #endif
 738         return 0;
 739 }
 740
 741 void set_muxconf_regs(void)
 742 {
 743         do_set_mux32((*ctrl)->control_padconf_core_base,
 744                      early_padconf, ARRAY_SIZE(early_padconf));
 745 }
 746
 747 #ifdef CONFIG_IODELAY_RECALIBRATION
 748 void recalibrate_iodelay(void)
 749 {
 750         const struct pad_conf_entry *pconf;
 751         const struct iodelay_cfg_entry *iod, *delta_iod;
 752         int pconf_sz, iod_sz, delta_iod_sz = 0;
 753         int ret;
 754
 755         if (board_is_am572x_idk()) {
 756                 pconf = core_padconf_array_essential_am572x_idk;
 757                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 758                 iod = iodelay_cfg_array_am572x_idk;
 759                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 760         } else if (board_is_am574x_idk()) {
 761                 pconf = core_padconf_array_essential_am574x_idk;
 762                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
 763                 iod = iodelay_cfg_array_am574x_idk;
 764                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
 765         } else if (board_is_am571x_idk()) {
 766                 pconf = core_padconf_array_essential_am571x_idk;
 767                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 768                 iod = iodelay_cfg_array_am571x_idk;
 769                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 770         } else {
 771                 /* Common for X15/GPEVM */
 772                 pconf = core_padconf_array_essential_x15;
 773                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 774                 /* There never was an SR1.0 X15.. So.. */
 775                 if (omap_revision() == DRA752_ES1_1) {
 776                         iod = iodelay_cfg_array_x15_sr1_1;
 777                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 778                 } else {
 779                         /* Since full production should switch to SR2.0  */
 780                         iod = iodelay_cfg_array_x15_sr2_0;
 781                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 782                 }
 783         }
 784
 785         /* Setup I/O isolation */
 786         ret = __recalibrate_iodelay_start();
 787         if (ret)
 788                 goto err;
 789
 790         /* Do the muxing here */
 791         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 792
 793         /* Now do the weird minor deltas that should be safe */
 794         if (board_is_x15() || board_is_am572x_evm()) {
 795                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 796                     board_is_x15_revc()) {
 797                         pconf = core_padconf_array_delta_x15_sr2_0;
 798                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 799                 } else {
 800                         pconf = core_padconf_array_delta_x15_sr1_1;
 801                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 802                 }
 803                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 804         }
 805
 806         if (board_is_am571x_idk()) {
 807                 if (am571x_idk_needs_lcd()) {
 808                         pconf = core_padconf_array_vout_am571x_idk;
 809                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 810                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 811                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 812
 813                 } else {
 814                         pconf = core_padconf_array_icss1eth_am571x_idk;
 815                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 816                 }
 817                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 818         }
 819
 820         /* Setup IOdelay configuration */
 821         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 822         if (delta_iod_sz)
 823                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 824                                      delta_iod_sz);
 825
 826 err:
 827         /* Closeup.. remove isolation */
 828         __recalibrate_iodelay_end(ret);
 829 }
 830 #endif
 831
 832 #if defined(CONFIG_MMC)
 833 int board_mmc_init(bd_t *bis)
 834 {
 835         omap_mmc_init(0, 0, 0, -1, -1);
 836         omap_mmc_init(1, 0, 0, -1, -1);
 837         return 0;
 838 }
 839
 840 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
 841         .hw_rev = "rev11",
 842         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 843                             MMC_CAP(UHS_SDR104),
 844         .max_freq = 96000000,
 845 };
 846
 847 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
 848         .hw_rev = "rev11",
 849         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 850                             MMC_CAP(UHS_SDR104) |
 851                             MMC_CAP(UHS_SDR50),
 852         .max_freq = 48000000,
 853 };
 854
 855 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 856 {
 857         switch (omap_revision()) {
 858         case DRA752_ES1_0:
 859         case DRA752_ES1_1:
 860                 if (addr == OMAP_HSMMC1_BASE)
 861                         return &am57x_es1_1_mmc1_fixups;
 862                 else
 863                         return &am57x_es1_1_mmc23_fixups;
 864         default:
 865                 return NULL;
 866         }
 867 }
 868 #endif
 869
 870 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 871 int spl_start_uboot(void)
 872 {
 873         /* break into full u-boot on 'c' */
 874         if (serial_tstc() && serial_getc() == 'c')
 875                 return 1;
 876
 877 #ifdef CONFIG_SPL_ENV_SUPPORT
 878         env_init();
 879         env_load();
 880         if (env_get_yesno("boot_os") != 1)
 881                 return 1;
 882 #endif
 883
 884         return 0;
 885 }
 886 #endif
 887
 888 #ifdef CONFIG_DRIVER_TI_CPSW
 889
 890 /* Delay value to add to calibrated value */
 891 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 892 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 893 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 894 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 895 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 896 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 897 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 898 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 899 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 900 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 901
 902 static void cpsw_control(int enabled)
 903 {
 904         /* VTP can be added here */
 905 }
 906
 907 static struct cpsw_slave_data cpsw_slaves[] = {
 908         {
 909                 .slave_reg_ofs  = 0x208,
 910                 .sliver_reg_ofs = 0xd80,
 911                 .phy_addr       = 1,
 912         },
 913         {
 914                 .slave_reg_ofs  = 0x308,
 915                 .sliver_reg_ofs = 0xdc0,
 916                 .phy_addr       = 2,
 917         },
 918 };
 919
 920 static struct cpsw_platform_data cpsw_data = {
 921         .mdio_base              = CPSW_MDIO_BASE,
 922         .cpsw_base              = CPSW_BASE,
 923         .mdio_div               = 0xff,
 924         .channels               = 8,
 925         .cpdma_reg_ofs          = 0x800,
 926         .slaves                 = 1,
 927         .slave_data             = cpsw_slaves,
 928         .ale_reg_ofs            = 0xd00,
 929         .ale_entries            = 1024,
 930         .host_port_reg_ofs      = 0x108,
 931         .hw_stats_reg_ofs       = 0x900,
 932         .bd_ram_ofs             = 0x2000,
 933         .mac_control            = (1 << 5),
 934         .control                = cpsw_control,
 935         .host_port_num          = 0,
 936         .version                = CPSW_CTRL_VERSION_2,
 937 };
 938
 939 static u64 mac_to_u64(u8 mac[6])
 940 {
 941         int i;
 942         u64 addr = 0;
 943
 944         for (i = 0; i < 6; i++) {
 945                 addr <<= 8;
 946                 addr |= mac[i];
 947         }
 948
 949         return addr;
 950 }
 951
 952 static void u64_to_mac(u64 addr, u8 mac[6])
 953 {
 954         mac[5] = addr;
 955         mac[4] = addr >> 8;
 956         mac[3] = addr >> 16;
 957         mac[2] = addr >> 24;
 958         mac[1] = addr >> 32;
 959         mac[0] = addr >> 40;
 960 }
 961
 962 int board_eth_init(bd_t *bis)
 963 {
 964         int ret;
 965         uint8_t mac_addr[6];
 966         uint32_t mac_hi, mac_lo;
 967         uint32_t ctrl_val;
 968         int i;
 969         u64 mac1, mac2;
 970         u8 mac_addr1[6], mac_addr2[6];
 971         int num_macs;
 972
 973         /* try reading mac address from efuse */
 974         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 975         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 976         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 977         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 978         mac_addr[2] = mac_hi & 0xFF;
 979         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 980         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 981         mac_addr[5] = mac_lo & 0xFF;
 982
 983         if (!env_get("ethaddr")) {
 984                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 985
 986                 if (is_valid_ethaddr(mac_addr))
 987                         eth_env_set_enetaddr("ethaddr", mac_addr);
 988         }
 989
 990         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 991         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 992         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 993         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 994         mac_addr[2] = mac_hi & 0xFF;
 995         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 996         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 997         mac_addr[5] = mac_lo & 0xFF;
 998
 999         if (!env_get("eth1addr")) {
1000                 if (is_valid_ethaddr(mac_addr))
1001                         eth_env_set_enetaddr("eth1addr", mac_addr);
1002         }
1003
1004         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1005         ctrl_val |= 0x22;
1006         writel(ctrl_val, (*ctrl)->control_core_control_io1);
1007
1008         /* The phy address for the AM57xx IDK are different than x15 */
1009         if (board_is_am572x_idk() || board_is_am571x_idk() ||
1010             board_is_am574x_idk()) {
1011                 cpsw_data.slave_data[0].phy_addr = 0;
1012                 cpsw_data.slave_data[1].phy_addr = 1;
1013         }
1014
1015         ret = cpsw_register(&cpsw_data);
1016         if (ret < 0)
1017                 printf("Error %d registering CPSW switch\n", ret);
1018
1019         /*
1020          * Export any Ethernet MAC addresses from EEPROM.
1021          * On AM57xx the 2 MAC addresses define the address range
1022          */
1023         board_ti_get_eth_mac_addr(0, mac_addr1);
1024         board_ti_get_eth_mac_addr(1, mac_addr2);
1025
1026         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1027                 mac1 = mac_to_u64(mac_addr1);
1028                 mac2 = mac_to_u64(mac_addr2);
1029
1030                 /* must contain an address range */
1031                 num_macs = mac2 - mac1 + 1;
1032                 /* <= 50 to protect against user programming error */
1033                 if (num_macs > 0 && num_macs <= 50) {
1034                         for (i = 0; i < num_macs; i++) {
1035                                 u64_to_mac(mac1 + i, mac_addr);
1036                                 if (is_valid_ethaddr(mac_addr)) {
1037                                         eth_env_set_enetaddr_by_index("eth",
1038                                                                       i + 2,
1039                                                                       mac_addr);
1040                                 }
1041                         }
1042                 }
1043         }
1044
1045         return ret;
1046 }
1047 #endif
1048
1049 #ifdef CONFIG_BOARD_EARLY_INIT_F
1050 /* VTT regulator enable */
1051 static inline void vtt_regulator_enable(void)
1052 {
1053         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1054                 return;
1055
1056         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1057         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1058 }
1059
1060 int board_early_init_f(void)
1061 {
1062         vtt_regulator_enable();
1063         return 0;
1064 }
1065 #endif
1066
1067 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1068 int ft_board_setup(void *blob, bd_t *bd)
1069 {
1070         ft_cpu_setup(blob, bd);
1071
1072         return 0;
1073 }
1074 #endif
1075
1076 #ifdef CONFIG_SPL_LOAD_FIT
1077 int board_fit_config_name_match(const char *name)
1078 {
1079         if (board_is_x15()) {
1080                 if (board_is_x15_revb1()) {
1081                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1082                                 return 0;
1083                 } else if (board_is_x15_revc()) {
1084                         if (!strcmp(name, "am57xx-beagle-x15-revc"))
1085                                 return 0;
1086                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1087                         return 0;
1088                 }
1089         } else if (board_is_am572x_evm() &&
1090                    !strcmp(name, "am57xx-beagle-x15")) {
1091                 return 0;
1092         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1093                 return 0;
1094         } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1095                 return 0;
1096         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1097                 return 0;
1098         }
1099
1100         return -1;
1101 }
1102 #endif
1103
1104 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1105 int fastboot_set_reboot_flag(void)
1106 {
1107         printf("Setting reboot to fastboot flag ...\n");
1108         env_set("dofastboot", "1");
1109         env_save();
1110         return 0;
1111 }
1112 #endif
1113
1114 #ifdef CONFIG_TI_SECURE_DEVICE
1115 void board_fit_image_post_process(void **p_image, size_t *p_size)
1116 {
1117         secure_boot_verify_image(p_image, p_size);
1118 }
1119
1120 void board_tee_image_process(ulong tee_image, size_t tee_size)
1121 {
1122         secure_tee_install((u32)tee_image);
1123 }
1124
1125 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1126 #endif