board/ti/am57xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   4  *
   5  * Author: Felipe Balbi <balbi@ti.com>
   6  *
   7  * Based on board/ti/dra7xx/evm.c
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <init.h>
  13 #include <palmas.h>
  14 #include <sata.h>
  15 #include <serial.h>
  16 #include <usb.h>
  17 #include <asm/omap_common.h>
  18 #include <asm/omap_sec_common.h>
  19 #include <asm/emif.h>
  20 #include <asm/gpio.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/clock.h>
  23 #include <asm/arch/dra7xx_iodelay.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/arch/mmc_host_def.h>
  26 #include <asm/arch/sata.h>
  27 #include <asm/arch/gpio.h>
  28 #include <asm/arch/omap.h>
  29 #include <usb.h>
  30 #include <linux/usb/gadget.h>
  31 #include <dwc3-uboot.h>
  32 #include <dwc3-omap-uboot.h>
  33 #include <ti-usb-phy-uboot.h>
  34 #include <mmc.h>
  35 #include <dm/uclass.h>
  36
  37 #include "../common/board_detect.h"
  38 #include "mux_data.h"
  39
  40 #define board_is_x15()          board_ti_is("BBRDX15_")
  41 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  42                                  !strncmp("B.10", board_ti_get_rev(), 3))
  43 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  44                                  !strncmp("C.00", board_ti_get_rev(), 3))
  45 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  46 #define board_is_am572x_evm_reva3()     \
  47                                 (board_ti_is("AM572PM_") && \
  48                                  !strncmp("A.30", board_ti_get_rev(), 3))
  49 #define board_is_am574x_idk()   board_ti_is("AM574IDK")
  50 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  51 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  52
  53 #ifdef CONFIG_DRIVER_TI_CPSW
  54 #include <cpsw.h>
  55 #endif
  56
  57 DECLARE_GLOBAL_DATA_PTR;
  58
  59 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  60 /* GPIO 7_11 */
  61 #define GPIO_DDR_VTT_EN 203
  62
  63 /* Touch screen controller to identify the LCD */
  64 #define OSD_TS_FT_BUS_ADDRESS   0
  65 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  66 #define OSD_TS_FT_REG_ID        0xA3
  67 /*
  68  * Touchscreen IDs for various OSD panels
  69  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  70  */
  71 /* Used on newer osd101t2587 Panels */
  72 #define OSD_TS_FT_ID_5x46       0x54
  73 /* Used on older osd101t2045 Panels */
  74 #define OSD_TS_FT_ID_5606       0x08
  75
  76 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  77
  78 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  79 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  80
  81 const struct omap_sysinfo sysinfo = {
  82         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  83 };
  84
  85 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  86         .dmm_lisa_map_3 = 0x80740300,
  87         .is_ma_present  = 0x1
  88 };
  89
  90 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  91         .dmm_lisa_map_3 = 0x80640100,
  92         .is_ma_present  = 0x1
  93 };
  94
  95 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
  96         .dmm_lisa_map_2 = 0xc0600200,
  97         .dmm_lisa_map_3 = 0x80600100,
  98         .is_ma_present  = 0x1
  99 };
 100
 101 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 102 {
 103         if (board_is_am571x_idk())
 104                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
 105         else if (board_is_am574x_idk())
 106                 *dmm_lisa_regs = &am574x_idk_lisa_regs;
 107         else
 108                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
 109 }
 110
 111 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 112         .sdram_config_init              = 0x61851b32,
 113         .sdram_config                   = 0x61851b32,
 114         .sdram_config2                  = 0x08000000,
 115         .ref_ctrl                       = 0x000040F1,
 116         .ref_ctrl_final                 = 0x00001035,
 117         .sdram_tim1                     = 0xcccf36ab,
 118         .sdram_tim2                     = 0x308f7fda,
 119         .sdram_tim3                     = 0x409f88a8,
 120         .read_idle_ctrl                 = 0x00050000,
 121         .zq_config                      = 0x5007190b,
 122         .temp_alert_config              = 0x00000000,
 123         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 124         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 125         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 126         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 127         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 128         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 129         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 130         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 131         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 132         .emif_rd_wr_lvl_ctl             = 0x00000000,
 133         .emif_rd_wr_exec_thresh         = 0x00000305
 134 };
 135
 136 /* Ext phy ctrl regs 1-35 */
 137 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 138         0x10040100,
 139         0x00910091,
 140         0x00950095,
 141         0x009B009B,
 142         0x009E009E,
 143         0x00980098,
 144         0x00340034,
 145         0x00350035,
 146         0x00340034,
 147         0x00310031,
 148         0x00340034,
 149         0x007F007F,
 150         0x007F007F,
 151         0x007F007F,
 152         0x007F007F,
 153         0x007F007F,
 154         0x00480048,
 155         0x004A004A,
 156         0x00520052,
 157         0x00550055,
 158         0x00500050,
 159         0x00000000,
 160         0x00600020,
 161         0x40011080,
 162         0x08102040,
 163         0x0,
 164         0x0,
 165         0x0,
 166         0x0,
 167         0x0,
 168         0x0,
 169         0x0,
 170         0x0,
 171         0x0,
 172         0x0
 173 };
 174
 175 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 176         .sdram_config_init              = 0x61851b32,
 177         .sdram_config                   = 0x61851b32,
 178         .sdram_config2                  = 0x08000000,
 179         .ref_ctrl                       = 0x000040F1,
 180         .ref_ctrl_final                 = 0x00001035,
 181         .sdram_tim1                     = 0xcccf36b3,
 182         .sdram_tim2                     = 0x308f7fda,
 183         .sdram_tim3                     = 0x407f88a8,
 184         .read_idle_ctrl                 = 0x00050000,
 185         .zq_config                      = 0x5007190b,
 186         .temp_alert_config              = 0x00000000,
 187         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 188         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 189         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 190         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 191         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 192         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 193         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 194         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 195         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 196         .emif_rd_wr_lvl_ctl             = 0x00000000,
 197         .emif_rd_wr_exec_thresh         = 0x00000305
 198 };
 199
 200 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 201         0x10040100,
 202         0x00910091,
 203         0x00950095,
 204         0x009B009B,
 205         0x009E009E,
 206         0x00980098,
 207         0x00340034,
 208         0x00350035,
 209         0x00340034,
 210         0x00310031,
 211         0x00340034,
 212         0x007F007F,
 213         0x007F007F,
 214         0x007F007F,
 215         0x007F007F,
 216         0x007F007F,
 217         0x00480048,
 218         0x004A004A,
 219         0x00520052,
 220         0x00550055,
 221         0x00500050,
 222         0x00000000,
 223         0x00600020,
 224         0x40011080,
 225         0x08102040,
 226         0x0,
 227         0x0,
 228         0x0,
 229         0x0,
 230         0x0,
 231         0x0,
 232         0x0,
 233         0x0,
 234         0x0,
 235         0x0
 236 };
 237
 238 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 239         .sdram_config_init              = 0x61863332,
 240         .sdram_config                   = 0x61863332,
 241         .sdram_config2                  = 0x08000000,
 242         .ref_ctrl                       = 0x0000514d,
 243         .ref_ctrl_final                 = 0x0000144a,
 244         .sdram_tim1                     = 0xd333887c,
 245         .sdram_tim2                     = 0x30b37fe3,
 246         .sdram_tim3                     = 0x409f8ad8,
 247         .read_idle_ctrl                 = 0x00050000,
 248         .zq_config                      = 0x5007190b,
 249         .temp_alert_config              = 0x00000000,
 250         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 251         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 252         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 253         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 254         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 255         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 256         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 257         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 258         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 259         .emif_rd_wr_lvl_ctl             = 0x00000000,
 260         .emif_rd_wr_exec_thresh         = 0x00000305
 261 };
 262
 263 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
 264         .sdram_config_init              = 0x61863332,
 265         .sdram_config                   = 0x61863332,
 266         .sdram_config2                  = 0x08000000,
 267         .ref_ctrl                       = 0x0000514d,
 268         .ref_ctrl_final                 = 0x0000144a,
 269         .sdram_tim1                     = 0xd333887c,
 270         .sdram_tim2                     = 0x30b37fe3,
 271         .sdram_tim3                     = 0x409f8ad8,
 272         .read_idle_ctrl                 = 0x00050000,
 273         .zq_config                      = 0x5007190b,
 274         .temp_alert_config              = 0x00000000,
 275         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 276         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 277         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 278         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 279         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 280         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 281         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 282         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 283         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 284         .emif_rd_wr_lvl_ctl             = 0x00000000,
 285         .emif_rd_wr_exec_thresh         = 0x00000305,
 286         .emif_ecc_ctrl_reg              = 0xD0000001,
 287         .emif_ecc_address_range_1       = 0x3FFF0000,
 288         .emif_ecc_address_range_2       = 0x00000000
 289 };
 290
 291 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 292 {
 293         switch (emif_nr) {
 294         case 1:
 295                 if (board_is_am571x_idk())
 296                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 297                 else if (board_is_am574x_idk())
 298                         *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
 299                 else
 300                         *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 301                 break;
 302         case 2:
 303                 if (board_is_am574x_idk())
 304                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 305                 else
 306                         *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 307                 break;
 308         }
 309 }
 310
 311 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 312 {
 313         switch (emif_nr) {
 314         case 1:
 315                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 316                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 317                 break;
 318         case 2:
 319                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 320                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 321                 break;
 322         }
 323 }
 324
 325 struct vcores_data beagle_x15_volts = {
 326         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 327         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 328         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 329         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 330         .mpu.pmic               = &tps659038,
 331         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 332
 333         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 334         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 335         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 336         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 337         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 338         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 339         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 340         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 341         .eve.pmic               = &tps659038,
 342         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 343
 344         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 345         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 346         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 347         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 348         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 349         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 350         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 351         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 352         .gpu.pmic               = &tps659038,
 353         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 354
 355         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 356         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 357         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 358         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 359         .core.pmic              = &tps659038,
 360
 361         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 362         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 363         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 364         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 365         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 366         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 367         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 368         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 369         .iva.pmic               = &tps659038,
 370         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 371 };
 372
 373 struct vcores_data am572x_idk_volts = {
 374         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 375         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 376         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 377         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 378         .mpu.pmic               = &tps659038,
 379         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 380
 381         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 382         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 383         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 384         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 385         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 386         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 387         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 388         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 389         .eve.pmic               = &tps659038,
 390         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 391
 392         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 393         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 394         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 395         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 396         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 397         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 398         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 399         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 400         .gpu.pmic               = &tps659038,
 401         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 402
 403         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 404         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 405         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 406         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 407         .core.pmic              = &tps659038,
 408
 409         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 410         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 411         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 412         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 413         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 414         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 415         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 416         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 417         .iva.pmic               = &tps659038,
 418         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 419 };
 420
 421 struct vcores_data am571x_idk_volts = {
 422         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 423         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 424         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 425         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 426         .mpu.pmic               = &tps659038,
 427         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 428
 429         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 430         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 431         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 432         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 433         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 434         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 435         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 436         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 437         .eve.pmic               = &tps659038,
 438         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 439
 440         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 441         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 442         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 443         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 444         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 445         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 446         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 447         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 448         .gpu.pmic               = &tps659038,
 449         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 450
 451         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 452         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 453         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 454         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 455         .core.pmic              = &tps659038,
 456
 457         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 458         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 459         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 460         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 461         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 462         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 463         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 464         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 465         .iva.pmic               = &tps659038,
 466         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 467 };
 468
 469 int get_voltrail_opp(int rail_offset)
 470 {
 471         int opp;
 472
 473         switch (rail_offset) {
 474         case VOLT_MPU:
 475                 opp = DRA7_MPU_OPP;
 476                 break;
 477         case VOLT_CORE:
 478                 opp = DRA7_CORE_OPP;
 479                 break;
 480         case VOLT_GPU:
 481                 opp = DRA7_GPU_OPP;
 482                 break;
 483         case VOLT_EVE:
 484                 opp = DRA7_DSPEVE_OPP;
 485                 break;
 486         case VOLT_IVA:
 487                 opp = DRA7_IVA_OPP;
 488                 break;
 489         default:
 490                 opp = OPP_NOM;
 491         }
 492
 493         return opp;
 494 }
 495
 496
 497 #ifdef CONFIG_SPL_BUILD
 498 /* No env to setup for SPL */
 499 static inline void setup_board_eeprom_env(void) { }
 500
 501 /* Override function to read eeprom information */
 502 void do_board_detect(void)
 503 {
 504         int rc;
 505
 506         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 507                                   CONFIG_EEPROM_CHIP_ADDRESS);
 508         if (rc)
 509                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 510 }
 511
 512 #else   /* CONFIG_SPL_BUILD */
 513
 514 /* Override function to read eeprom information: actual i2c read done by SPL*/
 515 void do_board_detect(void)
 516 {
 517         char *bname = NULL;
 518         int rc;
 519
 520         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 521                                   CONFIG_EEPROM_CHIP_ADDRESS);
 522         if (rc)
 523                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 524
 525         if (board_is_x15())
 526                 bname = "BeagleBoard X15";
 527         else if (board_is_am572x_evm())
 528                 bname = "AM572x EVM";
 529         else if (board_is_am574x_idk())
 530                 bname = "AM574x IDK";
 531         else if (board_is_am572x_idk())
 532                 bname = "AM572x IDK";
 533         else if (board_is_am571x_idk())
 534                 bname = "AM571x IDK";
 535
 536         if (bname)
 537                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 538                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 539 }
 540
 541 static void setup_board_eeprom_env(void)
 542 {
 543         char *name = "beagle_x15";
 544         int rc;
 545
 546         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 547                                   CONFIG_EEPROM_CHIP_ADDRESS);
 548         if (rc)
 549                 goto invalid_eeprom;
 550
 551         if (board_is_x15()) {
 552                 if (board_is_x15_revb1())
 553                         name = "beagle_x15_revb1";
 554                 else if (board_is_x15_revc())
 555                         name = "beagle_x15_revc";
 556                 else
 557                         name = "beagle_x15";
 558         } else if (board_is_am572x_evm()) {
 559                 if (board_is_am572x_evm_reva3())
 560                         name = "am57xx_evm_reva3";
 561                 else
 562                         name = "am57xx_evm";
 563         } else if (board_is_am574x_idk()) {
 564                 name = "am574x_idk";
 565         } else if (board_is_am572x_idk()) {
 566                 name = "am572x_idk";
 567         } else if (board_is_am571x_idk()) {
 568                 name = "am571x_idk";
 569         } else {
 570                 printf("Unidentified board claims %s in eeprom header\n",
 571                        board_ti_get_name());
 572         }
 573
 574 invalid_eeprom:
 575         set_board_info_env(name);
 576 }
 577
 578 #endif  /* CONFIG_SPL_BUILD */
 579
 580 void vcores_init(void)
 581 {
 582         if (board_is_am572x_idk() || board_is_am574x_idk())
 583                 *omap_vcores = &am572x_idk_volts;
 584         else if (board_is_am571x_idk())
 585                 *omap_vcores = &am571x_idk_volts;
 586         else
 587                 *omap_vcores = &beagle_x15_volts;
 588 }
 589
 590 void hw_data_init(void)
 591 {
 592         *prcm = &dra7xx_prcm;
 593         if (is_dra72x())
 594                 *dplls_data = &dra72x_dplls;
 595         else if (is_dra76x())
 596                 *dplls_data = &dra76x_dplls;
 597         else
 598                 *dplls_data = &dra7xx_dplls;
 599         *ctrl = &dra7xx_ctrl;
 600 }
 601
 602 bool am571x_idk_needs_lcd(void)
 603 {
 604         bool needs_lcd;
 605
 606         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 607         if (gpio_get_value(GPIO_ETH_LCD))
 608                 needs_lcd = false;
 609         else
 610                 needs_lcd = true;
 611
 612         gpio_free(GPIO_ETH_LCD);
 613
 614         return needs_lcd;
 615 }
 616
 617 int board_init(void)
 618 {
 619         gpmc_init();
 620         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 621
 622         return 0;
 623 }
 624
 625 void am57x_idk_lcd_detect(void)
 626 {
 627         int r = -ENODEV;
 628         char *idk_lcd = "no";
 629         struct udevice *dev;
 630
 631         /* Only valid for IDKs */
 632         if (board_is_x15() || board_is_am572x_evm())
 633                 return;
 634
 635         /* Only AM571x IDK has gpio control detect.. so check that */
 636         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 637                 goto out;
 638
 639         r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
 640                                     OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
 641         if (r) {
 642                 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
 643                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 644                        r);
 645                 /* AM572x IDK has no explicit settings for optional LCD kit */
 646                 if (board_is_am571x_idk())
 647                         printf("%s: Touch screen detect failed: %d!\n",
 648                                __func__, r);
 649                 goto out;
 650         }
 651
 652         /* Read FT ID */
 653         r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
 654         if (r < 0) {
 655                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 656                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 657                        OSD_TS_FT_REG_ID, r);
 658                 goto out;
 659         }
 660
 661         switch (r) {
 662         case OSD_TS_FT_ID_5606:
 663                 idk_lcd = "osd101t2045";
 664                 break;
 665         case OSD_TS_FT_ID_5x46:
 666                 idk_lcd = "osd101t2587";
 667                 break;
 668         default:
 669                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 670                        __func__, r);
 671                 /* we will let default be "no lcd" */
 672         }
 673 out:
 674         env_set("idk_lcd", idk_lcd);
 675         return;
 676 }
 677
 678 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 679 static int device_okay(const char *path)
 680 {
 681         int node;
 682
 683         node = fdt_path_offset(gd->fdt_blob, path);
 684         if (node < 0)
 685                 return 0;
 686
 687         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 688 }
 689 #endif
 690
 691 int board_late_init(void)
 692 {
 693         setup_board_eeprom_env();
 694         u8 val;
 695         struct udevice *dev;
 696
 697         /*
 698          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 699          * This is the POWERHOLD-in-Low behavior.
 700          */
 701         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 702
 703         /*
 704          * Default FIT boot on HS devices. Non FIT images are not allowed
 705          * on HS devices.
 706          */
 707         if (get_device_type() == HS_DEVICE)
 708                 env_set("boot_fit", "1");
 709
 710         /*
 711          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 712          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 713          * PMIC Power off. So to be on the safer side set it back
 714          * to POWERHOLD mode irrespective of the current state.
 715          */
 716         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 717                            &val);
 718         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 719         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 720                             val);
 721
 722         omap_die_id_serial();
 723         omap_set_fastboot_vars();
 724
 725         am57x_idk_lcd_detect();
 726
 727         /* Just probe the potentially supported cdce913 device */
 728         uclass_get_device(UCLASS_CLK, 0, &dev);
 729
 730 #if !defined(CONFIG_SPL_BUILD)
 731         board_ti_set_ethaddr(2);
 732 #endif
 733
 734 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 735         if (device_okay("/ocp/omap_dwc3_1@48880000"))
 736                 enable_usb_clocks(0);
 737         if (device_okay("/ocp/omap_dwc3_2@488c0000"))
 738                 enable_usb_clocks(1);
 739 #endif
 740         return 0;
 741 }
 742
 743 void set_muxconf_regs(void)
 744 {
 745         do_set_mux32((*ctrl)->control_padconf_core_base,
 746                      early_padconf, ARRAY_SIZE(early_padconf));
 747 }
 748
 749 #ifdef CONFIG_IODELAY_RECALIBRATION
 750 void recalibrate_iodelay(void)
 751 {
 752         const struct pad_conf_entry *pconf;
 753         const struct iodelay_cfg_entry *iod, *delta_iod;
 754         int pconf_sz, iod_sz, delta_iod_sz = 0;
 755         int ret;
 756
 757         if (board_is_am572x_idk()) {
 758                 pconf = core_padconf_array_essential_am572x_idk;
 759                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 760                 iod = iodelay_cfg_array_am572x_idk;
 761                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 762         } else if (board_is_am574x_idk()) {
 763                 pconf = core_padconf_array_essential_am574x_idk;
 764                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
 765                 iod = iodelay_cfg_array_am574x_idk;
 766                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
 767         } else if (board_is_am571x_idk()) {
 768                 pconf = core_padconf_array_essential_am571x_idk;
 769                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 770                 iod = iodelay_cfg_array_am571x_idk;
 771                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 772         } else {
 773                 /* Common for X15/GPEVM */
 774                 pconf = core_padconf_array_essential_x15;
 775                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 776                 /* There never was an SR1.0 X15.. So.. */
 777                 if (omap_revision() == DRA752_ES1_1) {
 778                         iod = iodelay_cfg_array_x15_sr1_1;
 779                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 780                 } else {
 781                         /* Since full production should switch to SR2.0  */
 782                         iod = iodelay_cfg_array_x15_sr2_0;
 783                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 784                 }
 785         }
 786
 787         /* Setup I/O isolation */
 788         ret = __recalibrate_iodelay_start();
 789         if (ret)
 790                 goto err;
 791
 792         /* Do the muxing here */
 793         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 794
 795         /* Now do the weird minor deltas that should be safe */
 796         if (board_is_x15() || board_is_am572x_evm()) {
 797                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 798                     board_is_x15_revc()) {
 799                         pconf = core_padconf_array_delta_x15_sr2_0;
 800                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 801                 } else {
 802                         pconf = core_padconf_array_delta_x15_sr1_1;
 803                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 804                 }
 805                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 806         }
 807
 808         if (board_is_am571x_idk()) {
 809                 if (am571x_idk_needs_lcd()) {
 810                         pconf = core_padconf_array_vout_am571x_idk;
 811                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 812                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 813                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 814
 815                 } else {
 816                         pconf = core_padconf_array_icss1eth_am571x_idk;
 817                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 818                 }
 819                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 820         }
 821
 822         /* Setup IOdelay configuration */
 823         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 824         if (delta_iod_sz)
 825                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 826                                      delta_iod_sz);
 827
 828 err:
 829         /* Closeup.. remove isolation */
 830         __recalibrate_iodelay_end(ret);
 831 }
 832 #endif
 833
 834 #if defined(CONFIG_MMC)
 835 int board_mmc_init(bd_t *bis)
 836 {
 837         omap_mmc_init(0, 0, 0, -1, -1);
 838         omap_mmc_init(1, 0, 0, -1, -1);
 839         return 0;
 840 }
 841
 842 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
 843         .hw_rev = "rev11",
 844         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 845                             MMC_CAP(UHS_SDR104),
 846         .max_freq = 96000000,
 847 };
 848
 849 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
 850         .hw_rev = "rev11",
 851         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 852                             MMC_CAP(UHS_SDR104) |
 853                             MMC_CAP(UHS_SDR50),
 854         .max_freq = 48000000,
 855 };
 856
 857 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 858 {
 859         switch (omap_revision()) {
 860         case DRA752_ES1_0:
 861         case DRA752_ES1_1:
 862                 if (addr == OMAP_HSMMC1_BASE)
 863                         return &am57x_es1_1_mmc1_fixups;
 864                 else
 865                         return &am57x_es1_1_mmc23_fixups;
 866         default:
 867                 return NULL;
 868         }
 869 }
 870 #endif
 871
 872 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 873 int spl_start_uboot(void)
 874 {
 875         /* break into full u-boot on 'c' */
 876         if (serial_tstc() && serial_getc() == 'c')
 877                 return 1;
 878
 879 #ifdef CONFIG_SPL_ENV_SUPPORT
 880         env_init();
 881         env_load();
 882         if (env_get_yesno("boot_os") != 1)
 883                 return 1;
 884 #endif
 885
 886         return 0;
 887 }
 888 #endif
 889
 890 #ifdef CONFIG_DRIVER_TI_CPSW
 891
 892 /* Delay value to add to calibrated value */
 893 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 894 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 895 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 896 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 897 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 898 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 899 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 900 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 901 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 902 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 903
 904 static void cpsw_control(int enabled)
 905 {
 906         /* VTP can be added here */
 907 }
 908
 909 static struct cpsw_slave_data cpsw_slaves[] = {
 910         {
 911                 .slave_reg_ofs  = 0x208,
 912                 .sliver_reg_ofs = 0xd80,
 913                 .phy_addr       = 1,
 914         },
 915         {
 916                 .slave_reg_ofs  = 0x308,
 917                 .sliver_reg_ofs = 0xdc0,
 918                 .phy_addr       = 2,
 919         },
 920 };
 921
 922 static struct cpsw_platform_data cpsw_data = {
 923         .mdio_base              = CPSW_MDIO_BASE,
 924         .cpsw_base              = CPSW_BASE,
 925         .mdio_div               = 0xff,
 926         .channels               = 8,
 927         .cpdma_reg_ofs          = 0x800,
 928         .slaves                 = 1,
 929         .slave_data             = cpsw_slaves,
 930         .ale_reg_ofs            = 0xd00,
 931         .ale_entries            = 1024,
 932         .host_port_reg_ofs      = 0x108,
 933         .hw_stats_reg_ofs       = 0x900,
 934         .bd_ram_ofs             = 0x2000,
 935         .mac_control            = (1 << 5),
 936         .control                = cpsw_control,
 937         .host_port_num          = 0,
 938         .version                = CPSW_CTRL_VERSION_2,
 939 };
 940
 941 static u64 mac_to_u64(u8 mac[6])
 942 {
 943         int i;
 944         u64 addr = 0;
 945
 946         for (i = 0; i < 6; i++) {
 947                 addr <<= 8;
 948                 addr |= mac[i];
 949         }
 950
 951         return addr;
 952 }
 953
 954 static void u64_to_mac(u64 addr, u8 mac[6])
 955 {
 956         mac[5] = addr;
 957         mac[4] = addr >> 8;
 958         mac[3] = addr >> 16;
 959         mac[2] = addr >> 24;
 960         mac[1] = addr >> 32;
 961         mac[0] = addr >> 40;
 962 }
 963
 964 int board_eth_init(bd_t *bis)
 965 {
 966         int ret;
 967         uint8_t mac_addr[6];
 968         uint32_t mac_hi, mac_lo;
 969         uint32_t ctrl_val;
 970         int i;
 971         u64 mac1, mac2;
 972         u8 mac_addr1[6], mac_addr2[6];
 973         int num_macs;
 974
 975         /* try reading mac address from efuse */
 976         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 977         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 978         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 979         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 980         mac_addr[2] = mac_hi & 0xFF;
 981         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 982         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 983         mac_addr[5] = mac_lo & 0xFF;
 984
 985         if (!env_get("ethaddr")) {
 986                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 987
 988                 if (is_valid_ethaddr(mac_addr))
 989                         eth_env_set_enetaddr("ethaddr", mac_addr);
 990         }
 991
 992         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 993         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 994         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 995         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 996         mac_addr[2] = mac_hi & 0xFF;
 997         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 998         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 999         mac_addr[5] = mac_lo & 0xFF;
1000
1001         if (!env_get("eth1addr")) {
1002                 if (is_valid_ethaddr(mac_addr))
1003                         eth_env_set_enetaddr("eth1addr", mac_addr);
1004         }
1005
1006         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1007         ctrl_val |= 0x22;
1008         writel(ctrl_val, (*ctrl)->control_core_control_io1);
1009
1010         /* The phy address for the AM57xx IDK are different than x15 */
1011         if (board_is_am572x_idk() || board_is_am571x_idk() ||
1012             board_is_am574x_idk()) {
1013                 cpsw_data.slave_data[0].phy_addr = 0;
1014                 cpsw_data.slave_data[1].phy_addr = 1;
1015         }
1016
1017         ret = cpsw_register(&cpsw_data);
1018         if (ret < 0)
1019                 printf("Error %d registering CPSW switch\n", ret);
1020
1021         /*
1022          * Export any Ethernet MAC addresses from EEPROM.
1023          * On AM57xx the 2 MAC addresses define the address range
1024          */
1025         board_ti_get_eth_mac_addr(0, mac_addr1);
1026         board_ti_get_eth_mac_addr(1, mac_addr2);
1027
1028         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1029                 mac1 = mac_to_u64(mac_addr1);
1030                 mac2 = mac_to_u64(mac_addr2);
1031
1032                 /* must contain an address range */
1033                 num_macs = mac2 - mac1 + 1;
1034                 /* <= 50 to protect against user programming error */
1035                 if (num_macs > 0 && num_macs <= 50) {
1036                         for (i = 0; i < num_macs; i++) {
1037                                 u64_to_mac(mac1 + i, mac_addr);
1038                                 if (is_valid_ethaddr(mac_addr)) {
1039                                         eth_env_set_enetaddr_by_index("eth",
1040                                                                       i + 2,
1041                                                                       mac_addr);
1042                                 }
1043                         }
1044                 }
1045         }
1046
1047         return ret;
1048 }
1049 #endif
1050
1051 #ifdef CONFIG_BOARD_EARLY_INIT_F
1052 /* VTT regulator enable */
1053 static inline void vtt_regulator_enable(void)
1054 {
1055         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1056                 return;
1057
1058         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1059         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1060 }
1061
1062 int board_early_init_f(void)
1063 {
1064         vtt_regulator_enable();
1065         return 0;
1066 }
1067 #endif
1068
1069 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1070 int ft_board_setup(void *blob, bd_t *bd)
1071 {
1072         ft_cpu_setup(blob, bd);
1073
1074         return 0;
1075 }
1076 #endif
1077
1078 #ifdef CONFIG_SPL_LOAD_FIT
1079 int board_fit_config_name_match(const char *name)
1080 {
1081         if (board_is_x15()) {
1082                 if (board_is_x15_revb1()) {
1083                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1084                                 return 0;
1085                 } else if (board_is_x15_revc()) {
1086                         if (!strcmp(name, "am57xx-beagle-x15-revc"))
1087                                 return 0;
1088                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1089                         return 0;
1090                 }
1091         } else if (board_is_am572x_evm() &&
1092                    !strcmp(name, "am57xx-beagle-x15")) {
1093                 return 0;
1094         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1095                 return 0;
1096         } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1097                 return 0;
1098         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1099                 return 0;
1100         }
1101
1102         return -1;
1103 }
1104 #endif
1105
1106 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1107 int fastboot_set_reboot_flag(void)
1108 {
1109         printf("Setting reboot to fastboot flag ...\n");
1110         env_set("dofastboot", "1");
1111         env_save();
1112         return 0;
1113 }
1114 #endif
1115
1116 #ifdef CONFIG_TI_SECURE_DEVICE
1117 void board_fit_image_post_process(void **p_image, size_t *p_size)
1118 {
1119         secure_boot_verify_image(p_image, p_size);
1120 }
1121
1122 void board_tee_image_process(ulong tee_image, size_t tee_size)
1123 {
1124         secure_tee_install((u32)tee_image);
1125 }
1126
1127 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1128 #endif