2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
16 #include <asm/omap_sec_common.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/dra7xx_iodelay.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sata.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/omap.h>
27 #include <environment.h>
29 #include <linux/usb/gadget.h>
30 #include <dwc3-uboot.h>
31 #include <dwc3-omap-uboot.h>
32 #include <ti-usb-phy-uboot.h>
34 #include "../common/board_detect.h"
37 #define board_is_x15() board_ti_is("BBRDX15_")
38 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
39 (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
40 #define board_is_am572x_evm() board_ti_is("AM572PM_")
41 #define board_is_am572x_evm_reva3() \
42 (board_ti_is("AM572PM_") && \
43 (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
44 #define board_is_am572x_idk() board_ti_is("AM572IDK")
45 #define board_is_am571x_idk() board_ti_is("AM571IDK")
47 #ifdef CONFIG_DRIVER_TI_CPSW
51 DECLARE_GLOBAL_DATA_PTR;
54 #define GPIO_DDR_VTT_EN 203
56 #define SYSINFO_BOARD_NAME_MAX_LEN 45
58 const struct omap_sysinfo sysinfo = {
59 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
62 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
63 .dmm_lisa_map_3 = 0x80740300,
67 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
68 .dmm_lisa_map_3 = 0x80640100,
72 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
74 if (board_is_am571x_idk())
75 *dmm_lisa_regs = &am571x_idk_lisa_regs;
77 *dmm_lisa_regs = &beagle_x15_lisa_regs;
80 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
81 .sdram_config_init = 0x61851b32,
82 .sdram_config = 0x61851b32,
83 .sdram_config2 = 0x08000000,
84 .ref_ctrl = 0x000040F1,
85 .ref_ctrl_final = 0x00001035,
86 .sdram_tim1 = 0xcccf36ab,
87 .sdram_tim2 = 0x308f7fda,
88 .sdram_tim3 = 0x409f88a8,
89 .read_idle_ctrl = 0x00050000,
90 .zq_config = 0x5007190b,
91 .temp_alert_config = 0x00000000,
92 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
93 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
94 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
95 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
96 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
97 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
98 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
99 .emif_rd_wr_lvl_rmp_win = 0x00000000,
100 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
101 .emif_rd_wr_lvl_ctl = 0x00000000,
102 .emif_rd_wr_exec_thresh = 0x00000305
105 /* Ext phy ctrl regs 1-35 */
106 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
144 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
145 .sdram_config_init = 0x61851b32,
146 .sdram_config = 0x61851b32,
147 .sdram_config2 = 0x08000000,
148 .ref_ctrl = 0x000040F1,
149 .ref_ctrl_final = 0x00001035,
150 .sdram_tim1 = 0xcccf36b3,
151 .sdram_tim2 = 0x308f7fda,
152 .sdram_tim3 = 0x407f88a8,
153 .read_idle_ctrl = 0x00050000,
154 .zq_config = 0x5007190b,
155 .temp_alert_config = 0x00000000,
156 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
157 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
158 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
159 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
160 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
161 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
162 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
163 .emif_rd_wr_lvl_rmp_win = 0x00000000,
164 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
165 .emif_rd_wr_lvl_ctl = 0x00000000,
166 .emif_rd_wr_exec_thresh = 0x00000305
169 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
207 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
211 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
214 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
219 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
223 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
224 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
227 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
228 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
233 struct vcores_data beagle_x15_volts = {
234 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
235 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
236 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
237 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
238 .mpu.pmic = &tps659038,
239 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
241 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
242 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
243 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
244 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
245 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
246 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
247 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
248 .eve.addr = TPS659038_REG_ADDR_SMPS45,
249 .eve.pmic = &tps659038,
250 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
252 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
253 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
254 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
255 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
256 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
257 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
258 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
259 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
260 .gpu.pmic = &tps659038,
261 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
263 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
264 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
265 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
266 .core.addr = TPS659038_REG_ADDR_SMPS6,
267 .core.pmic = &tps659038,
269 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
270 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
271 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
272 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
273 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
274 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
275 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
276 .iva.addr = TPS659038_REG_ADDR_SMPS45,
277 .iva.pmic = &tps659038,
278 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
281 struct vcores_data am572x_idk_volts = {
282 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
283 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
284 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
285 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
286 .mpu.pmic = &tps659038,
287 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
289 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
290 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
291 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
292 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
293 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
294 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
295 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
296 .eve.addr = TPS659038_REG_ADDR_SMPS45,
297 .eve.pmic = &tps659038,
298 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
300 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
301 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
302 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
303 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
304 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
305 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
306 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
307 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
308 .gpu.pmic = &tps659038,
309 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
311 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
312 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
313 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
314 .core.addr = TPS659038_REG_ADDR_SMPS7,
315 .core.pmic = &tps659038,
317 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
318 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
319 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
320 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
321 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
322 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
323 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
324 .iva.addr = TPS659038_REG_ADDR_SMPS8,
325 .iva.pmic = &tps659038,
326 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
329 int get_voltrail_opp(int rail_offset)
333 switch (rail_offset) {
344 opp = DRA7_DSPEVE_OPP;
357 #ifdef CONFIG_SPL_BUILD
358 /* No env to setup for SPL */
359 static inline void setup_board_eeprom_env(void) { }
361 /* Override function to read eeprom information */
362 void do_board_detect(void)
366 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
367 CONFIG_EEPROM_CHIP_ADDRESS);
369 printf("ti_i2c_eeprom_init failed %d\n", rc);
372 #else /* CONFIG_SPL_BUILD */
374 /* Override function to read eeprom information: actual i2c read done by SPL*/
375 void do_board_detect(void)
380 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
381 CONFIG_EEPROM_CHIP_ADDRESS);
383 printf("ti_i2c_eeprom_init failed %d\n", rc);
386 bname = "BeagleBoard X15";
387 else if (board_is_am572x_evm())
388 bname = "AM572x EVM";
389 else if (board_is_am572x_idk())
390 bname = "AM572x IDK";
391 else if (board_is_am571x_idk())
392 bname = "AM571x IDK";
395 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
396 "Board: %s REV %s\n", bname, board_ti_get_rev());
399 static void setup_board_eeprom_env(void)
401 char *name = "beagle_x15";
404 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
405 CONFIG_EEPROM_CHIP_ADDRESS);
409 if (board_is_x15()) {
410 if (board_is_x15_revb1())
411 name = "beagle_x15_revb1";
414 } else if (board_is_am572x_evm()) {
415 if (board_is_am572x_evm_reva3())
416 name = "am57xx_evm_reva3";
419 } else if (board_is_am572x_idk()) {
421 } else if (board_is_am571x_idk()) {
424 printf("Unidentified board claims %s in eeprom header\n",
425 board_ti_get_name());
429 set_board_info_env(name);
432 #endif /* CONFIG_SPL_BUILD */
434 void vcores_init(void)
436 if (board_is_am572x_idk())
437 *omap_vcores = &am572x_idk_volts;
439 *omap_vcores = &beagle_x15_volts;
442 void hw_data_init(void)
444 *prcm = &dra7xx_prcm;
445 *dplls_data = &dra7xx_dplls;
446 *ctrl = &dra7xx_ctrl;
452 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
457 int board_late_init(void)
459 setup_board_eeprom_env();
462 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
463 * This is the POWERHOLD-in-Low behavior.
465 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
468 * Default FIT boot on HS devices. Non FIT images are not allowed
471 if (get_device_type() == HS_DEVICE)
472 setenv("boot_fit", "1");
477 void set_muxconf_regs(void)
479 do_set_mux32((*ctrl)->control_padconf_core_base,
480 early_padconf, ARRAY_SIZE(early_padconf));
483 #ifdef CONFIG_IODELAY_RECALIBRATION
484 void recalibrate_iodelay(void)
486 const struct pad_conf_entry *pconf;
487 const struct iodelay_cfg_entry *iod;
488 int pconf_sz, iod_sz;
491 if (board_is_am572x_idk()) {
492 pconf = core_padconf_array_essential_am572x_idk;
493 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
494 iod = iodelay_cfg_array_am572x_idk;
495 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
496 } else if (board_is_am571x_idk()) {
497 pconf = core_padconf_array_essential_am571x_idk;
498 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
499 iod = iodelay_cfg_array_am571x_idk;
500 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
502 /* Common for X15/GPEVM */
503 pconf = core_padconf_array_essential_x15;
504 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
505 /* There never was an SR1.0 X15.. So.. */
506 if (omap_revision() == DRA752_ES1_1) {
507 iod = iodelay_cfg_array_x15_sr1_1;
508 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
510 /* Since full production should switch to SR2.0 */
511 iod = iodelay_cfg_array_x15_sr2_0;
512 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
516 /* Setup I/O isolation */
517 ret = __recalibrate_iodelay_start();
521 /* Do the muxing here */
522 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
524 /* Now do the weird minor deltas that should be safe */
525 if (board_is_x15() || board_is_am572x_evm()) {
526 if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
527 pconf = core_padconf_array_delta_x15_sr2_0;
528 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
530 pconf = core_padconf_array_delta_x15_sr1_1;
531 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
533 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
536 /* Setup IOdelay configuration */
537 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
539 /* Closeup.. remove isolation */
540 __recalibrate_iodelay_end(ret);
544 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
545 int board_mmc_init(bd_t *bis)
547 omap_mmc_init(0, 0, 0, -1, -1);
548 omap_mmc_init(1, 0, 0, -1, -1);
553 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
554 int spl_start_uboot(void)
556 /* break into full u-boot on 'c' */
557 if (serial_tstc() && serial_getc() == 'c')
560 #ifdef CONFIG_SPL_ENV_SUPPORT
563 if (getenv_yesno("boot_os") != 1)
571 #ifdef CONFIG_USB_DWC3
572 static struct dwc3_device usb_otg_ss2 = {
573 .maximum_speed = USB_SPEED_HIGH,
574 .base = DRA7_USB_OTG_SS2_BASE,
575 .tx_fifo_resize = false,
579 static struct dwc3_omap_device usb_otg_ss2_glue = {
580 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
581 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
585 static struct ti_usb_phy_device usb_phy2_device = {
586 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
590 int usb_gadget_handle_interrupts(int index)
594 status = dwc3_omap_uboot_interrupt_status(index);
596 dwc3_uboot_handle_interrupt(index);
600 #endif /* CONFIG_USB_DWC3 */
602 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
603 int board_usb_init(int index, enum usb_init_type init)
605 enable_usb_clocks(index);
608 if (init == USB_INIT_DEVICE) {
609 printf("port %d can't be used as device\n", index);
610 disable_usb_clocks(index);
615 if (init == USB_INIT_DEVICE) {
616 #ifdef CONFIG_USB_DWC3
617 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
618 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
619 ti_usb_phy_uboot_init(&usb_phy2_device);
620 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
621 dwc3_uboot_init(&usb_otg_ss2);
624 printf("port %d can't be used as host\n", index);
625 disable_usb_clocks(index);
631 printf("Invalid Controller Index\n");
637 int board_usb_cleanup(int index, enum usb_init_type init)
639 #ifdef CONFIG_USB_DWC3
643 if (init == USB_INIT_DEVICE) {
644 ti_usb_phy_uboot_exit(index);
645 dwc3_uboot_exit(index);
646 dwc3_omap_uboot_exit(index);
650 printf("Invalid Controller Index\n");
653 disable_usb_clocks(index);
656 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
658 #ifdef CONFIG_DRIVER_TI_CPSW
660 /* Delay value to add to calibrated value */
661 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
662 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
663 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
664 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
665 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
666 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
667 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
668 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
669 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
670 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
672 static void cpsw_control(int enabled)
674 /* VTP can be added here */
677 static struct cpsw_slave_data cpsw_slaves[] = {
679 .slave_reg_ofs = 0x208,
680 .sliver_reg_ofs = 0xd80,
684 .slave_reg_ofs = 0x308,
685 .sliver_reg_ofs = 0xdc0,
690 static struct cpsw_platform_data cpsw_data = {
691 .mdio_base = CPSW_MDIO_BASE,
692 .cpsw_base = CPSW_BASE,
695 .cpdma_reg_ofs = 0x800,
697 .slave_data = cpsw_slaves,
698 .ale_reg_ofs = 0xd00,
700 .host_port_reg_ofs = 0x108,
701 .hw_stats_reg_ofs = 0x900,
702 .bd_ram_ofs = 0x2000,
703 .mac_control = (1 << 5),
704 .control = cpsw_control,
706 .version = CPSW_CTRL_VERSION_2,
709 static u64 mac_to_u64(u8 mac[6])
714 for (i = 0; i < 6; i++) {
722 static void u64_to_mac(u64 addr, u8 mac[6])
732 int board_eth_init(bd_t *bis)
736 uint32_t mac_hi, mac_lo;
740 u8 mac_addr1[6], mac_addr2[6];
743 /* try reading mac address from efuse */
744 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
745 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
746 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
747 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
748 mac_addr[2] = mac_hi & 0xFF;
749 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
750 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
751 mac_addr[5] = mac_lo & 0xFF;
753 if (!getenv("ethaddr")) {
754 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
756 if (is_valid_ethaddr(mac_addr))
757 eth_setenv_enetaddr("ethaddr", mac_addr);
760 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
761 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
762 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
763 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
764 mac_addr[2] = mac_hi & 0xFF;
765 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
766 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
767 mac_addr[5] = mac_lo & 0xFF;
769 if (!getenv("eth1addr")) {
770 if (is_valid_ethaddr(mac_addr))
771 eth_setenv_enetaddr("eth1addr", mac_addr);
774 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
776 writel(ctrl_val, (*ctrl)->control_core_control_io1);
778 /* The phy address for the AM57xx IDK are different than x15 */
779 if (board_is_am572x_idk() || board_is_am571x_idk()) {
780 cpsw_data.slave_data[0].phy_addr = 0;
781 cpsw_data.slave_data[1].phy_addr = 1;
784 ret = cpsw_register(&cpsw_data);
786 printf("Error %d registering CPSW switch\n", ret);
789 * Export any Ethernet MAC addresses from EEPROM.
790 * On AM57xx the 2 MAC addresses define the address range
792 board_ti_get_eth_mac_addr(0, mac_addr1);
793 board_ti_get_eth_mac_addr(1, mac_addr2);
795 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
796 mac1 = mac_to_u64(mac_addr1);
797 mac2 = mac_to_u64(mac_addr2);
799 /* must contain an address range */
800 num_macs = mac2 - mac1 + 1;
801 /* <= 50 to protect against user programming error */
802 if (num_macs > 0 && num_macs <= 50) {
803 for (i = 0; i < num_macs; i++) {
804 u64_to_mac(mac1 + i, mac_addr);
805 if (is_valid_ethaddr(mac_addr)) {
806 eth_setenv_enetaddr_by_index("eth",
818 #ifdef CONFIG_BOARD_EARLY_INIT_F
819 /* VTT regulator enable */
820 static inline void vtt_regulator_enable(void)
822 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
825 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
826 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
829 int board_early_init_f(void)
831 vtt_regulator_enable();
836 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
837 int ft_board_setup(void *blob, bd_t *bd)
839 ft_cpu_setup(blob, bd);
845 #ifdef CONFIG_SPL_LOAD_FIT
846 int board_fit_config_name_match(const char *name)
848 if (board_is_x15()) {
849 if (board_is_x15_revb1()) {
850 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
852 } else if (!strcmp(name, "am57xx-beagle-x15")) {
855 } else if (board_is_am572x_evm() &&
856 !strcmp(name, "am57xx-beagle-x15")) {
858 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
866 #ifdef CONFIG_TI_SECURE_DEVICE
867 void board_fit_image_post_process(void **p_image, size_t *p_size)
869 secure_boot_verify_image(p_image, p_size);
872 void board_tee_image_process(ulong tee_image, size_t tee_size)
874 secure_tee_install((u32)tee_image);
877 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);