board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/emif.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sata.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/omap.h>
  27 #include <environment.h>
  28 #include <usb.h>
  29 #include <linux/usb/gadget.h>
  30 #include <dwc3-uboot.h>
  31 #include <dwc3-omap-uboot.h>
  32 #include <ti-usb-phy-uboot.h>
  33
  34 #include "../common/board_detect.h"
  35 #include "mux_data.h"
  36
  37 #define board_is_x15()          board_ti_is("BBRDX15_")
  38 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  39                                  (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
  40 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  41 #define board_is_am572x_evm_reva3()     \
  42                                 (board_ti_is("AM572PM_") && \
  43                                  (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
  44 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  45 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  46
  47 #ifdef CONFIG_DRIVER_TI_CPSW
  48 #include <cpsw.h>
  49 #endif
  50
  51 DECLARE_GLOBAL_DATA_PTR;
  52
  53 /* GPIO 7_11 */
  54 #define GPIO_DDR_VTT_EN 203
  55
  56 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  57
  58 const struct omap_sysinfo sysinfo = {
  59         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  60 };
  61
  62 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  63         .dmm_lisa_map_3 = 0x80740300,
  64         .is_ma_present  = 0x1
  65 };
  66
  67 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  68         .dmm_lisa_map_3 = 0x80640100,
  69         .is_ma_present  = 0x1
  70 };
  71
  72 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  73 {
  74         if (board_is_am571x_idk())
  75                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
  76         else
  77                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
  78 }
  79
  80 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  81         .sdram_config_init              = 0x61851b32,
  82         .sdram_config                   = 0x61851b32,
  83         .sdram_config2                  = 0x08000000,
  84         .ref_ctrl                       = 0x000040F1,
  85         .ref_ctrl_final                 = 0x00001035,
  86         .sdram_tim1                     = 0xcccf36ab,
  87         .sdram_tim2                     = 0x308f7fda,
  88         .sdram_tim3                     = 0x409f88a8,
  89         .read_idle_ctrl                 = 0x00050000,
  90         .zq_config                      = 0x5007190b,
  91         .temp_alert_config              = 0x00000000,
  92         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
  93         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
  94         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  95         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  96         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  97         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
  98         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
  99         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 100         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 101         .emif_rd_wr_lvl_ctl             = 0x00000000,
 102         .emif_rd_wr_exec_thresh         = 0x00000305
 103 };
 104
 105 /* Ext phy ctrl regs 1-35 */
 106 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 107         0x10040100,
 108         0x00910091,
 109         0x00950095,
 110         0x009B009B,
 111         0x009E009E,
 112         0x00980098,
 113         0x00340034,
 114         0x00350035,
 115         0x00340034,
 116         0x00310031,
 117         0x00340034,
 118         0x007F007F,
 119         0x007F007F,
 120         0x007F007F,
 121         0x007F007F,
 122         0x007F007F,
 123         0x00480048,
 124         0x004A004A,
 125         0x00520052,
 126         0x00550055,
 127         0x00500050,
 128         0x00000000,
 129         0x00600020,
 130         0x40011080,
 131         0x08102040,
 132         0x0,
 133         0x0,
 134         0x0,
 135         0x0,
 136         0x0,
 137         0x0,
 138         0x0,
 139         0x0,
 140         0x0,
 141         0x0
 142 };
 143
 144 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 145         .sdram_config_init              = 0x61851b32,
 146         .sdram_config                   = 0x61851b32,
 147         .sdram_config2                  = 0x08000000,
 148         .ref_ctrl                       = 0x000040F1,
 149         .ref_ctrl_final                 = 0x00001035,
 150         .sdram_tim1                     = 0xcccf36b3,
 151         .sdram_tim2                     = 0x308f7fda,
 152         .sdram_tim3                     = 0x407f88a8,
 153         .read_idle_ctrl                 = 0x00050000,
 154         .zq_config                      = 0x5007190b,
 155         .temp_alert_config              = 0x00000000,
 156         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 157         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 158         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 159         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 160         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 161         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 162         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 163         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 164         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 165         .emif_rd_wr_lvl_ctl             = 0x00000000,
 166         .emif_rd_wr_exec_thresh         = 0x00000305
 167 };
 168
 169 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 170         0x10040100,
 171         0x00910091,
 172         0x00950095,
 173         0x009B009B,
 174         0x009E009E,
 175         0x00980098,
 176         0x00340034,
 177         0x00350035,
 178         0x00340034,
 179         0x00310031,
 180         0x00340034,
 181         0x007F007F,
 182         0x007F007F,
 183         0x007F007F,
 184         0x007F007F,
 185         0x007F007F,
 186         0x00480048,
 187         0x004A004A,
 188         0x00520052,
 189         0x00550055,
 190         0x00500050,
 191         0x00000000,
 192         0x00600020,
 193         0x40011080,
 194         0x08102040,
 195         0x0,
 196         0x0,
 197         0x0,
 198         0x0,
 199         0x0,
 200         0x0,
 201         0x0,
 202         0x0,
 203         0x0,
 204         0x0
 205 };
 206
 207 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 208 {
 209         switch (emif_nr) {
 210         case 1:
 211                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 212                 break;
 213         case 2:
 214                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 215                 break;
 216         }
 217 }
 218
 219 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 220 {
 221         switch (emif_nr) {
 222         case 1:
 223                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 224                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 225                 break;
 226         case 2:
 227                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 228                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 229                 break;
 230         }
 231 }
 232
 233 struct vcores_data beagle_x15_volts = {
 234         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 235         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 236         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 237         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 238         .mpu.pmic               = &tps659038,
 239         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 240
 241         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 242         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 243         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 244         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 245         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 246         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 247         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 248         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 249         .eve.pmic               = &tps659038,
 250         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 251
 252         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 253         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 254         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 255         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 256         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 257         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 258         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 259         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 260         .gpu.pmic               = &tps659038,
 261         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 262
 263         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 264         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 265         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 266         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 267         .core.pmic              = &tps659038,
 268
 269         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 270         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 271         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 272         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 273         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 274         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 275         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 276         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 277         .iva.pmic               = &tps659038,
 278         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 279 };
 280
 281 struct vcores_data am572x_idk_volts = {
 282         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 283         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 284         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 285         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 286         .mpu.pmic               = &tps659038,
 287         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 288
 289         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 290         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 291         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 292         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 293         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 294         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 295         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 296         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 297         .eve.pmic               = &tps659038,
 298         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 299
 300         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 301         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 302         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 303         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 304         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 305         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 306         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 307         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 308         .gpu.pmic               = &tps659038,
 309         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 310
 311         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 312         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 313         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 314         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 315         .core.pmic              = &tps659038,
 316
 317         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 318         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 319         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 320         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 321         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 322         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 323         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 324         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 325         .iva.pmic               = &tps659038,
 326         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 327 };
 328
 329 int get_voltrail_opp(int rail_offset)
 330 {
 331         int opp;
 332
 333         switch (rail_offset) {
 334         case VOLT_MPU:
 335                 opp = DRA7_MPU_OPP;
 336                 break;
 337         case VOLT_CORE:
 338                 opp = DRA7_CORE_OPP;
 339                 break;
 340         case VOLT_GPU:
 341                 opp = DRA7_GPU_OPP;
 342                 break;
 343         case VOLT_EVE:
 344                 opp = DRA7_DSPEVE_OPP;
 345                 break;
 346         case VOLT_IVA:
 347                 opp = DRA7_IVA_OPP;
 348                 break;
 349         default:
 350                 opp = OPP_NOM;
 351         }
 352
 353         return opp;
 354 }
 355
 356
 357 #ifdef CONFIG_SPL_BUILD
 358 /* No env to setup for SPL */
 359 static inline void setup_board_eeprom_env(void) { }
 360
 361 /* Override function to read eeprom information */
 362 void do_board_detect(void)
 363 {
 364         int rc;
 365
 366         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 367                                   CONFIG_EEPROM_CHIP_ADDRESS);
 368         if (rc)
 369                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 370 }
 371
 372 #else   /* CONFIG_SPL_BUILD */
 373
 374 /* Override function to read eeprom information: actual i2c read done by SPL*/
 375 void do_board_detect(void)
 376 {
 377         char *bname = NULL;
 378         int rc;
 379
 380         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 381                                   CONFIG_EEPROM_CHIP_ADDRESS);
 382         if (rc)
 383                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 384
 385         if (board_is_x15())
 386                 bname = "BeagleBoard X15";
 387         else if (board_is_am572x_evm())
 388                 bname = "AM572x EVM";
 389         else if (board_is_am572x_idk())
 390                 bname = "AM572x IDK";
 391         else if (board_is_am571x_idk())
 392                 bname = "AM571x IDK";
 393
 394         if (bname)
 395                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 396                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 397 }
 398
 399 static void setup_board_eeprom_env(void)
 400 {
 401         char *name = "beagle_x15";
 402         int rc;
 403
 404         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 405                                   CONFIG_EEPROM_CHIP_ADDRESS);
 406         if (rc)
 407                 goto invalid_eeprom;
 408
 409         if (board_is_x15()) {
 410                 if (board_is_x15_revb1())
 411                         name = "beagle_x15_revb1";
 412                 else
 413                         name = "beagle_x15";
 414         } else if (board_is_am572x_evm()) {
 415                 if (board_is_am572x_evm_reva3())
 416                         name = "am57xx_evm_reva3";
 417                 else
 418                         name = "am57xx_evm";
 419         } else if (board_is_am572x_idk()) {
 420                 name = "am572x_idk";
 421         } else if (board_is_am571x_idk()) {
 422                 name = "am571x_idk";
 423         } else {
 424                 printf("Unidentified board claims %s in eeprom header\n",
 425                        board_ti_get_name());
 426         }
 427
 428 invalid_eeprom:
 429         set_board_info_env(name);
 430 }
 431
 432 #endif  /* CONFIG_SPL_BUILD */
 433
 434 void vcores_init(void)
 435 {
 436         if (board_is_am572x_idk())
 437                 *omap_vcores = &am572x_idk_volts;
 438         else
 439                 *omap_vcores = &beagle_x15_volts;
 440 }
 441
 442 void hw_data_init(void)
 443 {
 444         *prcm = &dra7xx_prcm;
 445         *dplls_data = &dra7xx_dplls;
 446         *ctrl = &dra7xx_ctrl;
 447 }
 448
 449 int board_init(void)
 450 {
 451         gpmc_init();
 452         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 453
 454         return 0;
 455 }
 456
 457 int board_late_init(void)
 458 {
 459         setup_board_eeprom_env();
 460
 461         /*
 462          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 463          * This is the POWERHOLD-in-Low behavior.
 464          */
 465         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 466
 467         /*
 468          * Default FIT boot on HS devices. Non FIT images are not allowed
 469          * on HS devices.
 470          */
 471         if (get_device_type() == HS_DEVICE)
 472                 setenv("boot_fit", "1");
 473
 474         return 0;
 475 }
 476
 477 void set_muxconf_regs(void)
 478 {
 479         do_set_mux32((*ctrl)->control_padconf_core_base,
 480                      early_padconf, ARRAY_SIZE(early_padconf));
 481 }
 482
 483 #ifdef CONFIG_IODELAY_RECALIBRATION
 484 void recalibrate_iodelay(void)
 485 {
 486         const struct pad_conf_entry *pconf;
 487         const struct iodelay_cfg_entry *iod;
 488         int pconf_sz, iod_sz;
 489         int ret;
 490
 491         if (board_is_am572x_idk()) {
 492                 pconf = core_padconf_array_essential_am572x_idk;
 493                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 494                 iod = iodelay_cfg_array_am572x_idk;
 495                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 496         } else if (board_is_am571x_idk()) {
 497                 pconf = core_padconf_array_essential_am571x_idk;
 498                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 499                 iod = iodelay_cfg_array_am571x_idk;
 500                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 501         } else {
 502                 /* Common for X15/GPEVM */
 503                 pconf = core_padconf_array_essential_x15;
 504                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 505                 /* There never was an SR1.0 X15.. So.. */
 506                 if (omap_revision() == DRA752_ES1_1) {
 507                         iod = iodelay_cfg_array_x15_sr1_1;
 508                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 509                 } else {
 510                         /* Since full production should switch to SR2.0  */
 511                         iod = iodelay_cfg_array_x15_sr2_0;
 512                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 513                 }
 514         }
 515
 516         /* Setup I/O isolation */
 517         ret = __recalibrate_iodelay_start();
 518         if (ret)
 519                 goto err;
 520
 521         /* Do the muxing here */
 522         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 523
 524         /* Now do the weird minor deltas that should be safe */
 525         if (board_is_x15() || board_is_am572x_evm()) {
 526                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
 527                         pconf = core_padconf_array_delta_x15_sr2_0;
 528                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 529                 } else {
 530                         pconf = core_padconf_array_delta_x15_sr1_1;
 531                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 532                 }
 533                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 534         }
 535
 536         /* Setup IOdelay configuration */
 537         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 538 err:
 539         /* Closeup.. remove isolation */
 540         __recalibrate_iodelay_end(ret);
 541 }
 542 #endif
 543
 544 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 545 int board_mmc_init(bd_t *bis)
 546 {
 547         omap_mmc_init(0, 0, 0, -1, -1);
 548         omap_mmc_init(1, 0, 0, -1, -1);
 549         return 0;
 550 }
 551 #endif
 552
 553 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 554 int spl_start_uboot(void)
 555 {
 556         /* break into full u-boot on 'c' */
 557         if (serial_tstc() && serial_getc() == 'c')
 558                 return 1;
 559
 560 #ifdef CONFIG_SPL_ENV_SUPPORT
 561         env_init();
 562         env_relocate_spec();
 563         if (getenv_yesno("boot_os") != 1)
 564                 return 1;
 565 #endif
 566
 567         return 0;
 568 }
 569 #endif
 570
 571 #ifdef CONFIG_USB_DWC3
 572 static struct dwc3_device usb_otg_ss2 = {
 573         .maximum_speed = USB_SPEED_HIGH,
 574         .base = DRA7_USB_OTG_SS2_BASE,
 575         .tx_fifo_resize = false,
 576         .index = 1,
 577 };
 578
 579 static struct dwc3_omap_device usb_otg_ss2_glue = {
 580         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 581         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 582         .index = 1,
 583 };
 584
 585 static struct ti_usb_phy_device usb_phy2_device = {
 586         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 587         .index = 1,
 588 };
 589
 590 int usb_gadget_handle_interrupts(int index)
 591 {
 592         u32 status;
 593
 594         status = dwc3_omap_uboot_interrupt_status(index);
 595         if (status)
 596                 dwc3_uboot_handle_interrupt(index);
 597
 598         return 0;
 599 }
 600 #endif /* CONFIG_USB_DWC3 */
 601
 602 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 603 int board_usb_init(int index, enum usb_init_type init)
 604 {
 605         enable_usb_clocks(index);
 606         switch (index) {
 607         case 0:
 608                 if (init == USB_INIT_DEVICE) {
 609                         printf("port %d can't be used as device\n", index);
 610                         disable_usb_clocks(index);
 611                         return -EINVAL;
 612                 }
 613                 break;
 614         case 1:
 615                 if (init == USB_INIT_DEVICE) {
 616 #ifdef CONFIG_USB_DWC3
 617                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 618                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 619                         ti_usb_phy_uboot_init(&usb_phy2_device);
 620                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 621                         dwc3_uboot_init(&usb_otg_ss2);
 622 #endif
 623                 } else {
 624                         printf("port %d can't be used as host\n", index);
 625                         disable_usb_clocks(index);
 626                         return -EINVAL;
 627                 }
 628
 629                 break;
 630         default:
 631                 printf("Invalid Controller Index\n");
 632         }
 633
 634         return 0;
 635 }
 636
 637 int board_usb_cleanup(int index, enum usb_init_type init)
 638 {
 639 #ifdef CONFIG_USB_DWC3
 640         switch (index) {
 641         case 0:
 642         case 1:
 643                 if (init == USB_INIT_DEVICE) {
 644                         ti_usb_phy_uboot_exit(index);
 645                         dwc3_uboot_exit(index);
 646                         dwc3_omap_uboot_exit(index);
 647                 }
 648                 break;
 649         default:
 650                 printf("Invalid Controller Index\n");
 651         }
 652 #endif
 653         disable_usb_clocks(index);
 654         return 0;
 655 }
 656 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 657
 658 #ifdef CONFIG_DRIVER_TI_CPSW
 659
 660 /* Delay value to add to calibrated value */
 661 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 662 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 663 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 664 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 665 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 666 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 667 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 668 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 669 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 670 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 671
 672 static void cpsw_control(int enabled)
 673 {
 674         /* VTP can be added here */
 675 }
 676
 677 static struct cpsw_slave_data cpsw_slaves[] = {
 678         {
 679                 .slave_reg_ofs  = 0x208,
 680                 .sliver_reg_ofs = 0xd80,
 681                 .phy_addr       = 1,
 682         },
 683         {
 684                 .slave_reg_ofs  = 0x308,
 685                 .sliver_reg_ofs = 0xdc0,
 686                 .phy_addr       = 2,
 687         },
 688 };
 689
 690 static struct cpsw_platform_data cpsw_data = {
 691         .mdio_base              = CPSW_MDIO_BASE,
 692         .cpsw_base              = CPSW_BASE,
 693         .mdio_div               = 0xff,
 694         .channels               = 8,
 695         .cpdma_reg_ofs          = 0x800,
 696         .slaves                 = 1,
 697         .slave_data             = cpsw_slaves,
 698         .ale_reg_ofs            = 0xd00,
 699         .ale_entries            = 1024,
 700         .host_port_reg_ofs      = 0x108,
 701         .hw_stats_reg_ofs       = 0x900,
 702         .bd_ram_ofs             = 0x2000,
 703         .mac_control            = (1 << 5),
 704         .control                = cpsw_control,
 705         .host_port_num          = 0,
 706         .version                = CPSW_CTRL_VERSION_2,
 707 };
 708
 709 static u64 mac_to_u64(u8 mac[6])
 710 {
 711         int i;
 712         u64 addr = 0;
 713
 714         for (i = 0; i < 6; i++) {
 715                 addr <<= 8;
 716                 addr |= mac[i];
 717         }
 718
 719         return addr;
 720 }
 721
 722 static void u64_to_mac(u64 addr, u8 mac[6])
 723 {
 724         mac[5] = addr;
 725         mac[4] = addr >> 8;
 726         mac[3] = addr >> 16;
 727         mac[2] = addr >> 24;
 728         mac[1] = addr >> 32;
 729         mac[0] = addr >> 40;
 730 }
 731
 732 int board_eth_init(bd_t *bis)
 733 {
 734         int ret;
 735         uint8_t mac_addr[6];
 736         uint32_t mac_hi, mac_lo;
 737         uint32_t ctrl_val;
 738         int i;
 739         u64 mac1, mac2;
 740         u8 mac_addr1[6], mac_addr2[6];
 741         int num_macs;
 742
 743         /* try reading mac address from efuse */
 744         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 745         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 746         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 747         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 748         mac_addr[2] = mac_hi & 0xFF;
 749         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 750         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 751         mac_addr[5] = mac_lo & 0xFF;
 752
 753         if (!getenv("ethaddr")) {
 754                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 755
 756                 if (is_valid_ethaddr(mac_addr))
 757                         eth_setenv_enetaddr("ethaddr", mac_addr);
 758         }
 759
 760         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 761         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 762         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 763         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 764         mac_addr[2] = mac_hi & 0xFF;
 765         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 766         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 767         mac_addr[5] = mac_lo & 0xFF;
 768
 769         if (!getenv("eth1addr")) {
 770                 if (is_valid_ethaddr(mac_addr))
 771                         eth_setenv_enetaddr("eth1addr", mac_addr);
 772         }
 773
 774         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 775         ctrl_val |= 0x22;
 776         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 777
 778         /* The phy address for the AM57xx IDK are different than x15 */
 779         if (board_is_am572x_idk() || board_is_am571x_idk()) {
 780                 cpsw_data.slave_data[0].phy_addr = 0;
 781                 cpsw_data.slave_data[1].phy_addr = 1;
 782         }
 783
 784         ret = cpsw_register(&cpsw_data);
 785         if (ret < 0)
 786                 printf("Error %d registering CPSW switch\n", ret);
 787
 788         /*
 789          * Export any Ethernet MAC addresses from EEPROM.
 790          * On AM57xx the 2 MAC addresses define the address range
 791          */
 792         board_ti_get_eth_mac_addr(0, mac_addr1);
 793         board_ti_get_eth_mac_addr(1, mac_addr2);
 794
 795         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
 796                 mac1 = mac_to_u64(mac_addr1);
 797                 mac2 = mac_to_u64(mac_addr2);
 798
 799                 /* must contain an address range */
 800                 num_macs = mac2 - mac1 + 1;
 801                 /* <= 50 to protect against user programming error */
 802                 if (num_macs > 0 && num_macs <= 50) {
 803                         for (i = 0; i < num_macs; i++) {
 804                                 u64_to_mac(mac1 + i, mac_addr);
 805                                 if (is_valid_ethaddr(mac_addr)) {
 806                                         eth_setenv_enetaddr_by_index("eth",
 807                                                                      i + 2,
 808                                                                      mac_addr);
 809                                 }
 810                         }
 811                 }
 812         }
 813
 814         return ret;
 815 }
 816 #endif
 817
 818 #ifdef CONFIG_BOARD_EARLY_INIT_F
 819 /* VTT regulator enable */
 820 static inline void vtt_regulator_enable(void)
 821 {
 822         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 823                 return;
 824
 825         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 826         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 827 }
 828
 829 int board_early_init_f(void)
 830 {
 831         vtt_regulator_enable();
 832         return 0;
 833 }
 834 #endif
 835
 836 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 837 int ft_board_setup(void *blob, bd_t *bd)
 838 {
 839         ft_cpu_setup(blob, bd);
 840
 841         return 0;
 842 }
 843 #endif
 844
 845 #ifdef CONFIG_SPL_LOAD_FIT
 846 int board_fit_config_name_match(const char *name)
 847 {
 848         if (board_is_x15()) {
 849                 if (board_is_x15_revb1()) {
 850                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
 851                                 return 0;
 852                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
 853                         return 0;
 854                 }
 855         } else if (board_is_am572x_evm() &&
 856                    !strcmp(name, "am57xx-beagle-x15")) {
 857                 return 0;
 858         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
 859                 return 0;
 860         }
 861
 862         return -1;
 863 }
 864 #endif
 865
 866 #ifdef CONFIG_TI_SECURE_DEVICE
 867 void board_fit_image_post_process(void **p_image, size_t *p_size)
 868 {
 869         secure_boot_verify_image(p_image, p_size);
 870 }
 871
 872 void board_tee_image_process(ulong tee_image, size_t tee_size)
 873 {
 874         secure_tee_install((u32)tee_image);
 875 }
 876
 877 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 878 #endif