board/ti/am57xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   4  *
   5  * Author: Felipe Balbi <balbi@ti.com>
   6  *
   7  * Based on board/ti/dra7xx/evm.c
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/emif.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sata.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/omap.h>
  27 #include <environment.h>
  28 #include <usb.h>
  29 #include <linux/usb/gadget.h>
  30 #include <dwc3-uboot.h>
  31 #include <dwc3-omap-uboot.h>
  32 #include <ti-usb-phy-uboot.h>
  33 #include <mmc.h>
  34
  35 #include "../common/board_detect.h"
  36 #include "mux_data.h"
  37
  38 #define board_is_x15()          board_ti_is("BBRDX15_")
  39 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  40                                  !strncmp("B.10", board_ti_get_rev(), 3))
  41 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  42                                  !strncmp("C.00", board_ti_get_rev(), 3))
  43 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  44 #define board_is_am572x_evm_reva3()     \
  45                                 (board_ti_is("AM572PM_") && \
  46                                  !strncmp("A.30", board_ti_get_rev(), 3))
  47 #define board_is_am574x_idk()   board_ti_is("AM574IDK")
  48 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  49 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  50
  51 #ifdef CONFIG_DRIVER_TI_CPSW
  52 #include <cpsw.h>
  53 #endif
  54
  55 DECLARE_GLOBAL_DATA_PTR;
  56
  57 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  58 /* GPIO 7_11 */
  59 #define GPIO_DDR_VTT_EN 203
  60
  61 /* Touch screen controller to identify the LCD */
  62 #define OSD_TS_FT_BUS_ADDRESS   0
  63 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  64 #define OSD_TS_FT_REG_ID        0xA3
  65 /*
  66  * Touchscreen IDs for various OSD panels
  67  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  68  */
  69 /* Used on newer osd101t2587 Panels */
  70 #define OSD_TS_FT_ID_5x46       0x54
  71 /* Used on older osd101t2045 Panels */
  72 #define OSD_TS_FT_ID_5606       0x08
  73
  74 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  75
  76 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  77 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  78
  79 const struct omap_sysinfo sysinfo = {
  80         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  81 };
  82
  83 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  84         .dmm_lisa_map_3 = 0x80740300,
  85         .is_ma_present  = 0x1
  86 };
  87
  88 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  89         .dmm_lisa_map_3 = 0x80640100,
  90         .is_ma_present  = 0x1
  91 };
  92
  93 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
  94         .dmm_lisa_map_2 = 0xc0600200,
  95         .dmm_lisa_map_3 = 0x80600100,
  96         .is_ma_present  = 0x1
  97 };
  98
  99 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 100 {
 101         if (board_is_am571x_idk())
 102                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
 103         else if (board_is_am574x_idk())
 104                 *dmm_lisa_regs = &am574x_idk_lisa_regs;
 105         else
 106                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
 107 }
 108
 109 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 110         .sdram_config_init              = 0x61851b32,
 111         .sdram_config                   = 0x61851b32,
 112         .sdram_config2                  = 0x08000000,
 113         .ref_ctrl                       = 0x000040F1,
 114         .ref_ctrl_final                 = 0x00001035,
 115         .sdram_tim1                     = 0xcccf36ab,
 116         .sdram_tim2                     = 0x308f7fda,
 117         .sdram_tim3                     = 0x409f88a8,
 118         .read_idle_ctrl                 = 0x00050000,
 119         .zq_config                      = 0x5007190b,
 120         .temp_alert_config              = 0x00000000,
 121         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 122         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 123         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 124         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 125         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 126         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 127         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 128         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 129         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 130         .emif_rd_wr_lvl_ctl             = 0x00000000,
 131         .emif_rd_wr_exec_thresh         = 0x00000305
 132 };
 133
 134 /* Ext phy ctrl regs 1-35 */
 135 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 136         0x10040100,
 137         0x00910091,
 138         0x00950095,
 139         0x009B009B,
 140         0x009E009E,
 141         0x00980098,
 142         0x00340034,
 143         0x00350035,
 144         0x00340034,
 145         0x00310031,
 146         0x00340034,
 147         0x007F007F,
 148         0x007F007F,
 149         0x007F007F,
 150         0x007F007F,
 151         0x007F007F,
 152         0x00480048,
 153         0x004A004A,
 154         0x00520052,
 155         0x00550055,
 156         0x00500050,
 157         0x00000000,
 158         0x00600020,
 159         0x40011080,
 160         0x08102040,
 161         0x0,
 162         0x0,
 163         0x0,
 164         0x0,
 165         0x0,
 166         0x0,
 167         0x0,
 168         0x0,
 169         0x0,
 170         0x0
 171 };
 172
 173 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 174         .sdram_config_init              = 0x61851b32,
 175         .sdram_config                   = 0x61851b32,
 176         .sdram_config2                  = 0x08000000,
 177         .ref_ctrl                       = 0x000040F1,
 178         .ref_ctrl_final                 = 0x00001035,
 179         .sdram_tim1                     = 0xcccf36b3,
 180         .sdram_tim2                     = 0x308f7fda,
 181         .sdram_tim3                     = 0x407f88a8,
 182         .read_idle_ctrl                 = 0x00050000,
 183         .zq_config                      = 0x5007190b,
 184         .temp_alert_config              = 0x00000000,
 185         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 186         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 187         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 188         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 189         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 190         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 191         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 192         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 193         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 194         .emif_rd_wr_lvl_ctl             = 0x00000000,
 195         .emif_rd_wr_exec_thresh         = 0x00000305
 196 };
 197
 198 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 199         0x10040100,
 200         0x00910091,
 201         0x00950095,
 202         0x009B009B,
 203         0x009E009E,
 204         0x00980098,
 205         0x00340034,
 206         0x00350035,
 207         0x00340034,
 208         0x00310031,
 209         0x00340034,
 210         0x007F007F,
 211         0x007F007F,
 212         0x007F007F,
 213         0x007F007F,
 214         0x007F007F,
 215         0x00480048,
 216         0x004A004A,
 217         0x00520052,
 218         0x00550055,
 219         0x00500050,
 220         0x00000000,
 221         0x00600020,
 222         0x40011080,
 223         0x08102040,
 224         0x0,
 225         0x0,
 226         0x0,
 227         0x0,
 228         0x0,
 229         0x0,
 230         0x0,
 231         0x0,
 232         0x0,
 233         0x0
 234 };
 235
 236 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 237         .sdram_config_init              = 0x61863332,
 238         .sdram_config                   = 0x61863332,
 239         .sdram_config2                  = 0x08000000,
 240         .ref_ctrl                       = 0x0000514d,
 241         .ref_ctrl_final                 = 0x0000144a,
 242         .sdram_tim1                     = 0xd333887c,
 243         .sdram_tim2                     = 0x30b37fe3,
 244         .sdram_tim3                     = 0x409f8ad8,
 245         .read_idle_ctrl                 = 0x00050000,
 246         .zq_config                      = 0x5007190b,
 247         .temp_alert_config              = 0x00000000,
 248         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 249         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 250         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 251         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 252         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 253         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 254         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 255         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 256         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 257         .emif_rd_wr_lvl_ctl             = 0x00000000,
 258         .emif_rd_wr_exec_thresh         = 0x00000305
 259 };
 260
 261 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
 262         .sdram_config_init              = 0x61863332,
 263         .sdram_config                   = 0x61863332,
 264         .sdram_config2                  = 0x08000000,
 265         .ref_ctrl                       = 0x0000514d,
 266         .ref_ctrl_final                 = 0x0000144a,
 267         .sdram_tim1                     = 0xd333887c,
 268         .sdram_tim2                     = 0x30b37fe3,
 269         .sdram_tim3                     = 0x409f8ad8,
 270         .read_idle_ctrl                 = 0x00050000,
 271         .zq_config                      = 0x5007190b,
 272         .temp_alert_config              = 0x00000000,
 273         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 274         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 275         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 276         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 277         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 278         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 279         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 280         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 281         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 282         .emif_rd_wr_lvl_ctl             = 0x00000000,
 283         .emif_rd_wr_exec_thresh         = 0x00000305,
 284         .emif_ecc_ctrl_reg              = 0xD0000001,
 285         .emif_ecc_address_range_1       = 0x3FFF0000,
 286         .emif_ecc_address_range_2       = 0x00000000
 287 };
 288
 289 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 290 {
 291         switch (emif_nr) {
 292         case 1:
 293                 if (board_is_am571x_idk())
 294                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 295                 else if (board_is_am574x_idk())
 296                         *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
 297                 else
 298                         *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 299                 break;
 300         case 2:
 301                 if (board_is_am574x_idk())
 302                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 303                 else
 304                         *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 305                 break;
 306         }
 307 }
 308
 309 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 310 {
 311         switch (emif_nr) {
 312         case 1:
 313                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 314                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 315                 break;
 316         case 2:
 317                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 318                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 319                 break;
 320         }
 321 }
 322
 323 struct vcores_data beagle_x15_volts = {
 324         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 325         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 326         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 327         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 328         .mpu.pmic               = &tps659038,
 329         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 330
 331         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 332         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 333         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 334         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 335         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 336         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 337         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 338         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 339         .eve.pmic               = &tps659038,
 340         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 341
 342         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 343         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 344         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 345         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 346         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 347         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 348         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 349         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 350         .gpu.pmic               = &tps659038,
 351         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 352
 353         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 354         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 355         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 356         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 357         .core.pmic              = &tps659038,
 358
 359         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 360         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 361         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 362         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 363         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 364         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 365         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 366         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 367         .iva.pmic               = &tps659038,
 368         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 369 };
 370
 371 struct vcores_data am572x_idk_volts = {
 372         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 373         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 374         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 375         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 376         .mpu.pmic               = &tps659038,
 377         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 378
 379         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 380         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 381         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 382         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 383         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 384         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 385         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 386         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 387         .eve.pmic               = &tps659038,
 388         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 389
 390         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 391         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 392         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 393         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 394         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 395         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 396         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 397         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 398         .gpu.pmic               = &tps659038,
 399         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 400
 401         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 402         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 403         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 404         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 405         .core.pmic              = &tps659038,
 406
 407         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 408         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 409         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 410         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 411         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 412         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 413         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 414         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 415         .iva.pmic               = &tps659038,
 416         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 417 };
 418
 419 struct vcores_data am571x_idk_volts = {
 420         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 421         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 422         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 423         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 424         .mpu.pmic               = &tps659038,
 425         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 426
 427         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 428         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 429         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 430         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 431         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 432         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 433         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 434         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 435         .eve.pmic               = &tps659038,
 436         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 437
 438         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 439         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 440         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 441         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 442         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 443         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 444         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 445         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 446         .gpu.pmic               = &tps659038,
 447         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 448
 449         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 450         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 451         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 452         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 453         .core.pmic              = &tps659038,
 454
 455         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 456         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 457         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 458         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 459         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 460         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 461         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 462         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 463         .iva.pmic               = &tps659038,
 464         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 465 };
 466
 467 int get_voltrail_opp(int rail_offset)
 468 {
 469         int opp;
 470
 471         switch (rail_offset) {
 472         case VOLT_MPU:
 473                 opp = DRA7_MPU_OPP;
 474                 break;
 475         case VOLT_CORE:
 476                 opp = DRA7_CORE_OPP;
 477                 break;
 478         case VOLT_GPU:
 479                 opp = DRA7_GPU_OPP;
 480                 break;
 481         case VOLT_EVE:
 482                 opp = DRA7_DSPEVE_OPP;
 483                 break;
 484         case VOLT_IVA:
 485                 opp = DRA7_IVA_OPP;
 486                 break;
 487         default:
 488                 opp = OPP_NOM;
 489         }
 490
 491         return opp;
 492 }
 493
 494
 495 #ifdef CONFIG_SPL_BUILD
 496 /* No env to setup for SPL */
 497 static inline void setup_board_eeprom_env(void) { }
 498
 499 /* Override function to read eeprom information */
 500 void do_board_detect(void)
 501 {
 502         int rc;
 503
 504         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 505                                   CONFIG_EEPROM_CHIP_ADDRESS);
 506         if (rc)
 507                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 508 }
 509
 510 #else   /* CONFIG_SPL_BUILD */
 511
 512 /* Override function to read eeprom information: actual i2c read done by SPL*/
 513 void do_board_detect(void)
 514 {
 515         char *bname = NULL;
 516         int rc;
 517
 518         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 519                                   CONFIG_EEPROM_CHIP_ADDRESS);
 520         if (rc)
 521                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 522
 523         if (board_is_x15())
 524                 bname = "BeagleBoard X15";
 525         else if (board_is_am572x_evm())
 526                 bname = "AM572x EVM";
 527         else if (board_is_am574x_idk())
 528                 bname = "AM574x IDK";
 529         else if (board_is_am572x_idk())
 530                 bname = "AM572x IDK";
 531         else if (board_is_am571x_idk())
 532                 bname = "AM571x IDK";
 533
 534         if (bname)
 535                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 536                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 537 }
 538
 539 static void setup_board_eeprom_env(void)
 540 {
 541         char *name = "beagle_x15";
 542         int rc;
 543
 544         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 545                                   CONFIG_EEPROM_CHIP_ADDRESS);
 546         if (rc)
 547                 goto invalid_eeprom;
 548
 549         if (board_is_x15()) {
 550                 if (board_is_x15_revb1())
 551                         name = "beagle_x15_revb1";
 552                 else if (board_is_x15_revc())
 553                         name = "beagle_x15_revc";
 554                 else
 555                         name = "beagle_x15";
 556         } else if (board_is_am572x_evm()) {
 557                 if (board_is_am572x_evm_reva3())
 558                         name = "am57xx_evm_reva3";
 559                 else
 560                         name = "am57xx_evm";
 561         } else if (board_is_am574x_idk()) {
 562                 name = "am574x_idk";
 563         } else if (board_is_am572x_idk()) {
 564                 name = "am572x_idk";
 565         } else if (board_is_am571x_idk()) {
 566                 name = "am571x_idk";
 567         } else {
 568                 printf("Unidentified board claims %s in eeprom header\n",
 569                        board_ti_get_name());
 570         }
 571
 572 invalid_eeprom:
 573         set_board_info_env(name);
 574 }
 575
 576 #endif  /* CONFIG_SPL_BUILD */
 577
 578 void vcores_init(void)
 579 {
 580         if (board_is_am572x_idk() || board_is_am574x_idk())
 581                 *omap_vcores = &am572x_idk_volts;
 582         else if (board_is_am571x_idk())
 583                 *omap_vcores = &am571x_idk_volts;
 584         else
 585                 *omap_vcores = &beagle_x15_volts;
 586 }
 587
 588 void hw_data_init(void)
 589 {
 590         *prcm = &dra7xx_prcm;
 591         if (is_dra72x())
 592                 *dplls_data = &dra72x_dplls;
 593         else if (is_dra76x())
 594                 *dplls_data = &dra76x_dplls;
 595         else
 596                 *dplls_data = &dra7xx_dplls;
 597         *ctrl = &dra7xx_ctrl;
 598 }
 599
 600 bool am571x_idk_needs_lcd(void)
 601 {
 602         bool needs_lcd;
 603
 604         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 605         if (gpio_get_value(GPIO_ETH_LCD))
 606                 needs_lcd = false;
 607         else
 608                 needs_lcd = true;
 609
 610         gpio_free(GPIO_ETH_LCD);
 611
 612         return needs_lcd;
 613 }
 614
 615 int board_init(void)
 616 {
 617         gpmc_init();
 618         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 619
 620         return 0;
 621 }
 622
 623 void am57x_idk_lcd_detect(void)
 624 {
 625         int r = -ENODEV;
 626         char *idk_lcd = "no";
 627         struct udevice *dev;
 628
 629         /* Only valid for IDKs */
 630         if (board_is_x15() || board_is_am572x_evm())
 631                 return;
 632
 633         /* Only AM571x IDK has gpio control detect.. so check that */
 634         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 635                 goto out;
 636
 637         r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
 638                                     OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
 639         if (r) {
 640                 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
 641                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 642                        r);
 643                 /* AM572x IDK has no explicit settings for optional LCD kit */
 644                 if (board_is_am571x_idk())
 645                         printf("%s: Touch screen detect failed: %d!\n",
 646                                __func__, r);
 647                 goto out;
 648         }
 649
 650         /* Read FT ID */
 651         r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
 652         if (r < 0) {
 653                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 654                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 655                        OSD_TS_FT_REG_ID, r);
 656                 goto out;
 657         }
 658
 659         switch (r) {
 660         case OSD_TS_FT_ID_5606:
 661                 idk_lcd = "osd101t2045";
 662                 break;
 663         case OSD_TS_FT_ID_5x46:
 664                 idk_lcd = "osd101t2587";
 665                 break;
 666         default:
 667                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 668                        __func__, r);
 669                 /* we will let default be "no lcd" */
 670         }
 671 out:
 672         env_set("idk_lcd", idk_lcd);
 673         return;
 674 }
 675
 676 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 677 static int device_okay(const char *path)
 678 {
 679         int node;
 680
 681         node = fdt_path_offset(gd->fdt_blob, path);
 682         if (node < 0)
 683                 return 0;
 684
 685         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 686 }
 687 #endif
 688
 689 int board_late_init(void)
 690 {
 691         setup_board_eeprom_env();
 692         u8 val;
 693
 694         /*
 695          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 696          * This is the POWERHOLD-in-Low behavior.
 697          */
 698         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 699
 700         /*
 701          * Default FIT boot on HS devices. Non FIT images are not allowed
 702          * on HS devices.
 703          */
 704         if (get_device_type() == HS_DEVICE)
 705                 env_set("boot_fit", "1");
 706
 707         /*
 708          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 709          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 710          * PMIC Power off. So to be on the safer side set it back
 711          * to POWERHOLD mode irrespective of the current state.
 712          */
 713         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 714                            &val);
 715         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 716         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 717                             val);
 718
 719         omap_die_id_serial();
 720         omap_set_fastboot_vars();
 721
 722         am57x_idk_lcd_detect();
 723
 724 #if !defined(CONFIG_SPL_BUILD)
 725         board_ti_set_ethaddr(2);
 726 #endif
 727
 728 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 729         if (device_okay("/ocp/omap_dwc3_1@48880000"))
 730                 enable_usb_clocks(0);
 731         if (device_okay("/ocp/omap_dwc3_2@488c0000"))
 732                 enable_usb_clocks(1);
 733 #endif
 734         return 0;
 735 }
 736
 737 void set_muxconf_regs(void)
 738 {
 739         do_set_mux32((*ctrl)->control_padconf_core_base,
 740                      early_padconf, ARRAY_SIZE(early_padconf));
 741 }
 742
 743 #ifdef CONFIG_IODELAY_RECALIBRATION
 744 void recalibrate_iodelay(void)
 745 {
 746         const struct pad_conf_entry *pconf;
 747         const struct iodelay_cfg_entry *iod, *delta_iod;
 748         int pconf_sz, iod_sz, delta_iod_sz = 0;
 749         int ret;
 750
 751         if (board_is_am572x_idk()) {
 752                 pconf = core_padconf_array_essential_am572x_idk;
 753                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 754                 iod = iodelay_cfg_array_am572x_idk;
 755                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 756         } else if (board_is_am574x_idk()) {
 757                 pconf = core_padconf_array_essential_am574x_idk;
 758                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
 759                 iod = iodelay_cfg_array_am574x_idk;
 760                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
 761         } else if (board_is_am571x_idk()) {
 762                 pconf = core_padconf_array_essential_am571x_idk;
 763                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 764                 iod = iodelay_cfg_array_am571x_idk;
 765                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 766         } else {
 767                 /* Common for X15/GPEVM */
 768                 pconf = core_padconf_array_essential_x15;
 769                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 770                 /* There never was an SR1.0 X15.. So.. */
 771                 if (omap_revision() == DRA752_ES1_1) {
 772                         iod = iodelay_cfg_array_x15_sr1_1;
 773                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 774                 } else {
 775                         /* Since full production should switch to SR2.0  */
 776                         iod = iodelay_cfg_array_x15_sr2_0;
 777                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 778                 }
 779         }
 780
 781         /* Setup I/O isolation */
 782         ret = __recalibrate_iodelay_start();
 783         if (ret)
 784                 goto err;
 785
 786         /* Do the muxing here */
 787         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 788
 789         /* Now do the weird minor deltas that should be safe */
 790         if (board_is_x15() || board_is_am572x_evm()) {
 791                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 792                     board_is_x15_revc()) {
 793                         pconf = core_padconf_array_delta_x15_sr2_0;
 794                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 795                 } else {
 796                         pconf = core_padconf_array_delta_x15_sr1_1;
 797                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 798                 }
 799                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 800         }
 801
 802         if (board_is_am571x_idk()) {
 803                 if (am571x_idk_needs_lcd()) {
 804                         pconf = core_padconf_array_vout_am571x_idk;
 805                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 806                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 807                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 808
 809                 } else {
 810                         pconf = core_padconf_array_icss1eth_am571x_idk;
 811                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 812                 }
 813                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 814         }
 815
 816         /* Setup IOdelay configuration */
 817         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 818         if (delta_iod_sz)
 819                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 820                                      delta_iod_sz);
 821
 822 err:
 823         /* Closeup.. remove isolation */
 824         __recalibrate_iodelay_end(ret);
 825 }
 826 #endif
 827
 828 #if defined(CONFIG_MMC)
 829 int board_mmc_init(bd_t *bis)
 830 {
 831         omap_mmc_init(0, 0, 0, -1, -1);
 832         omap_mmc_init(1, 0, 0, -1, -1);
 833         return 0;
 834 }
 835
 836 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
 837         .hw_rev = "rev11",
 838         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 839                             MMC_CAP(UHS_SDR104),
 840         .max_freq = 96000000,
 841 };
 842
 843 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
 844         .hw_rev = "rev11",
 845         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 846                             MMC_CAP(UHS_SDR104) |
 847                             MMC_CAP(UHS_SDR50),
 848         .max_freq = 48000000,
 849 };
 850
 851 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 852 {
 853         switch (omap_revision()) {
 854         case DRA752_ES1_0:
 855         case DRA752_ES1_1:
 856                 if (addr == OMAP_HSMMC1_BASE)
 857                         return &am57x_es1_1_mmc1_fixups;
 858                 else
 859                         return &am57x_es1_1_mmc23_fixups;
 860         default:
 861                 return NULL;
 862         }
 863 }
 864 #endif
 865
 866 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 867 int spl_start_uboot(void)
 868 {
 869         /* break into full u-boot on 'c' */
 870         if (serial_tstc() && serial_getc() == 'c')
 871                 return 1;
 872
 873 #ifdef CONFIG_SPL_ENV_SUPPORT
 874         env_init();
 875         env_load();
 876         if (env_get_yesno("boot_os") != 1)
 877                 return 1;
 878 #endif
 879
 880         return 0;
 881 }
 882 #endif
 883
 884 #ifdef CONFIG_DRIVER_TI_CPSW
 885
 886 /* Delay value to add to calibrated value */
 887 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 888 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 889 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 890 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 891 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 892 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 893 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 894 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 895 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 896 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 897
 898 static void cpsw_control(int enabled)
 899 {
 900         /* VTP can be added here */
 901 }
 902
 903 static struct cpsw_slave_data cpsw_slaves[] = {
 904         {
 905                 .slave_reg_ofs  = 0x208,
 906                 .sliver_reg_ofs = 0xd80,
 907                 .phy_addr       = 1,
 908         },
 909         {
 910                 .slave_reg_ofs  = 0x308,
 911                 .sliver_reg_ofs = 0xdc0,
 912                 .phy_addr       = 2,
 913         },
 914 };
 915
 916 static struct cpsw_platform_data cpsw_data = {
 917         .mdio_base              = CPSW_MDIO_BASE,
 918         .cpsw_base              = CPSW_BASE,
 919         .mdio_div               = 0xff,
 920         .channels               = 8,
 921         .cpdma_reg_ofs          = 0x800,
 922         .slaves                 = 1,
 923         .slave_data             = cpsw_slaves,
 924         .ale_reg_ofs            = 0xd00,
 925         .ale_entries            = 1024,
 926         .host_port_reg_ofs      = 0x108,
 927         .hw_stats_reg_ofs       = 0x900,
 928         .bd_ram_ofs             = 0x2000,
 929         .mac_control            = (1 << 5),
 930         .control                = cpsw_control,
 931         .host_port_num          = 0,
 932         .version                = CPSW_CTRL_VERSION_2,
 933 };
 934
 935 static u64 mac_to_u64(u8 mac[6])
 936 {
 937         int i;
 938         u64 addr = 0;
 939
 940         for (i = 0; i < 6; i++) {
 941                 addr <<= 8;
 942                 addr |= mac[i];
 943         }
 944
 945         return addr;
 946 }
 947
 948 static void u64_to_mac(u64 addr, u8 mac[6])
 949 {
 950         mac[5] = addr;
 951         mac[4] = addr >> 8;
 952         mac[3] = addr >> 16;
 953         mac[2] = addr >> 24;
 954         mac[1] = addr >> 32;
 955         mac[0] = addr >> 40;
 956 }
 957
 958 int board_eth_init(bd_t *bis)
 959 {
 960         int ret;
 961         uint8_t mac_addr[6];
 962         uint32_t mac_hi, mac_lo;
 963         uint32_t ctrl_val;
 964         int i;
 965         u64 mac1, mac2;
 966         u8 mac_addr1[6], mac_addr2[6];
 967         int num_macs;
 968
 969         /* try reading mac address from efuse */
 970         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 971         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 972         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 973         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 974         mac_addr[2] = mac_hi & 0xFF;
 975         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 976         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 977         mac_addr[5] = mac_lo & 0xFF;
 978
 979         if (!env_get("ethaddr")) {
 980                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 981
 982                 if (is_valid_ethaddr(mac_addr))
 983                         eth_env_set_enetaddr("ethaddr", mac_addr);
 984         }
 985
 986         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 987         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 988         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 989         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 990         mac_addr[2] = mac_hi & 0xFF;
 991         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 992         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 993         mac_addr[5] = mac_lo & 0xFF;
 994
 995         if (!env_get("eth1addr")) {
 996                 if (is_valid_ethaddr(mac_addr))
 997                         eth_env_set_enetaddr("eth1addr", mac_addr);
 998         }
 999
1000         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1001         ctrl_val |= 0x22;
1002         writel(ctrl_val, (*ctrl)->control_core_control_io1);
1003
1004         /* The phy address for the AM57xx IDK are different than x15 */
1005         if (board_is_am572x_idk() || board_is_am571x_idk() ||
1006             board_is_am574x_idk()) {
1007                 cpsw_data.slave_data[0].phy_addr = 0;
1008                 cpsw_data.slave_data[1].phy_addr = 1;
1009         }
1010
1011         ret = cpsw_register(&cpsw_data);
1012         if (ret < 0)
1013                 printf("Error %d registering CPSW switch\n", ret);
1014
1015         /*
1016          * Export any Ethernet MAC addresses from EEPROM.
1017          * On AM57xx the 2 MAC addresses define the address range
1018          */
1019         board_ti_get_eth_mac_addr(0, mac_addr1);
1020         board_ti_get_eth_mac_addr(1, mac_addr2);
1021
1022         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1023                 mac1 = mac_to_u64(mac_addr1);
1024                 mac2 = mac_to_u64(mac_addr2);
1025
1026                 /* must contain an address range */
1027                 num_macs = mac2 - mac1 + 1;
1028                 /* <= 50 to protect against user programming error */
1029                 if (num_macs > 0 && num_macs <= 50) {
1030                         for (i = 0; i < num_macs; i++) {
1031                                 u64_to_mac(mac1 + i, mac_addr);
1032                                 if (is_valid_ethaddr(mac_addr)) {
1033                                         eth_env_set_enetaddr_by_index("eth",
1034                                                                       i + 2,
1035                                                                       mac_addr);
1036                                 }
1037                         }
1038                 }
1039         }
1040
1041         return ret;
1042 }
1043 #endif
1044
1045 #ifdef CONFIG_BOARD_EARLY_INIT_F
1046 /* VTT regulator enable */
1047 static inline void vtt_regulator_enable(void)
1048 {
1049         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1050                 return;
1051
1052         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1053         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1054 }
1055
1056 int board_early_init_f(void)
1057 {
1058         vtt_regulator_enable();
1059         return 0;
1060 }
1061 #endif
1062
1063 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1064 int ft_board_setup(void *blob, bd_t *bd)
1065 {
1066         ft_cpu_setup(blob, bd);
1067
1068         return 0;
1069 }
1070 #endif
1071
1072 #ifdef CONFIG_SPL_LOAD_FIT
1073 int board_fit_config_name_match(const char *name)
1074 {
1075         if (board_is_x15()) {
1076                 if (board_is_x15_revb1()) {
1077                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1078                                 return 0;
1079                 } else if (board_is_x15_revc()) {
1080                         if (!strcmp(name, "am57xx-beagle-x15-revc"))
1081                                 return 0;
1082                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1083                         return 0;
1084                 }
1085         } else if (board_is_am572x_evm() &&
1086                    !strcmp(name, "am57xx-beagle-x15")) {
1087                 return 0;
1088         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1089                 return 0;
1090         } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1091                 return 0;
1092         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1093                 return 0;
1094         }
1095
1096         return -1;
1097 }
1098 #endif
1099
1100 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1101 int fastboot_set_reboot_flag(void)
1102 {
1103         printf("Setting reboot to fastboot flag ...\n");
1104         env_set("dofastboot", "1");
1105         env_save();
1106         return 0;
1107 }
1108 #endif
1109
1110 #ifdef CONFIG_TI_SECURE_DEVICE
1111 void board_fit_image_post_process(void **p_image, size_t *p_size)
1112 {
1113         secure_boot_verify_image(p_image, p_size);
1114 }
1115
1116 void board_tee_image_process(ulong tee_image, size_t tee_size)
1117 {
1118         secure_tee_install((u32)tee_image);
1119 }
1120
1121 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1122 #endif