board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/emif.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sata.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/omap.h>
  27 #include <environment.h>
  28 #include <usb.h>
  29 #include <linux/usb/gadget.h>
  30 #include <dwc3-uboot.h>
  31 #include <dwc3-omap-uboot.h>
  32 #include <ti-usb-phy-uboot.h>
  33
  34 #include "../common/board_detect.h"
  35 #include "mux_data.h"
  36
  37 #define board_is_x15()          board_ti_is("BBRDX15_")
  38 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  39                                  (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
  40 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  41 #define board_is_am572x_evm_reva3()     \
  42                                 (board_ti_is("AM572PM_") && \
  43                                  (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
  44 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  45 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  46
  47 #ifdef CONFIG_DRIVER_TI_CPSW
  48 #include <cpsw.h>
  49 #endif
  50
  51 DECLARE_GLOBAL_DATA_PTR;
  52
  53 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  54 /* GPIO 7_11 */
  55 #define GPIO_DDR_VTT_EN 203
  56
  57 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  58
  59 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  60 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  61
  62 const struct omap_sysinfo sysinfo = {
  63         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  64 };
  65
  66 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  67         .dmm_lisa_map_3 = 0x80740300,
  68         .is_ma_present  = 0x1
  69 };
  70
  71 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  72         .dmm_lisa_map_3 = 0x80640100,
  73         .is_ma_present  = 0x1
  74 };
  75
  76 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  77 {
  78         if (board_is_am571x_idk())
  79                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
  80         else
  81                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
  82 }
  83
  84 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  85         .sdram_config_init              = 0x61851b32,
  86         .sdram_config                   = 0x61851b32,
  87         .sdram_config2                  = 0x08000000,
  88         .ref_ctrl                       = 0x000040F1,
  89         .ref_ctrl_final                 = 0x00001035,
  90         .sdram_tim1                     = 0xcccf36ab,
  91         .sdram_tim2                     = 0x308f7fda,
  92         .sdram_tim3                     = 0x409f88a8,
  93         .read_idle_ctrl                 = 0x00050000,
  94         .zq_config                      = 0x5007190b,
  95         .temp_alert_config              = 0x00000000,
  96         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
  97         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
  98         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  99         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 100         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 101         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 102         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 103         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 104         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 105         .emif_rd_wr_lvl_ctl             = 0x00000000,
 106         .emif_rd_wr_exec_thresh         = 0x00000305
 107 };
 108
 109 /* Ext phy ctrl regs 1-35 */
 110 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 111         0x10040100,
 112         0x00910091,
 113         0x00950095,
 114         0x009B009B,
 115         0x009E009E,
 116         0x00980098,
 117         0x00340034,
 118         0x00350035,
 119         0x00340034,
 120         0x00310031,
 121         0x00340034,
 122         0x007F007F,
 123         0x007F007F,
 124         0x007F007F,
 125         0x007F007F,
 126         0x007F007F,
 127         0x00480048,
 128         0x004A004A,
 129         0x00520052,
 130         0x00550055,
 131         0x00500050,
 132         0x00000000,
 133         0x00600020,
 134         0x40011080,
 135         0x08102040,
 136         0x0,
 137         0x0,
 138         0x0,
 139         0x0,
 140         0x0,
 141         0x0,
 142         0x0,
 143         0x0,
 144         0x0,
 145         0x0
 146 };
 147
 148 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 149         .sdram_config_init              = 0x61851b32,
 150         .sdram_config                   = 0x61851b32,
 151         .sdram_config2                  = 0x08000000,
 152         .ref_ctrl                       = 0x000040F1,
 153         .ref_ctrl_final                 = 0x00001035,
 154         .sdram_tim1                     = 0xcccf36b3,
 155         .sdram_tim2                     = 0x308f7fda,
 156         .sdram_tim3                     = 0x407f88a8,
 157         .read_idle_ctrl                 = 0x00050000,
 158         .zq_config                      = 0x5007190b,
 159         .temp_alert_config              = 0x00000000,
 160         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 161         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 162         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 163         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 164         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 165         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 166         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 167         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 168         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 169         .emif_rd_wr_lvl_ctl             = 0x00000000,
 170         .emif_rd_wr_exec_thresh         = 0x00000305
 171 };
 172
 173 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 174         0x10040100,
 175         0x00910091,
 176         0x00950095,
 177         0x009B009B,
 178         0x009E009E,
 179         0x00980098,
 180         0x00340034,
 181         0x00350035,
 182         0x00340034,
 183         0x00310031,
 184         0x00340034,
 185         0x007F007F,
 186         0x007F007F,
 187         0x007F007F,
 188         0x007F007F,
 189         0x007F007F,
 190         0x00480048,
 191         0x004A004A,
 192         0x00520052,
 193         0x00550055,
 194         0x00500050,
 195         0x00000000,
 196         0x00600020,
 197         0x40011080,
 198         0x08102040,
 199         0x0,
 200         0x0,
 201         0x0,
 202         0x0,
 203         0x0,
 204         0x0,
 205         0x0,
 206         0x0,
 207         0x0,
 208         0x0
 209 };
 210
 211 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 212 {
 213         switch (emif_nr) {
 214         case 1:
 215                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 216                 break;
 217         case 2:
 218                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 219                 break;
 220         }
 221 }
 222
 223 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 224 {
 225         switch (emif_nr) {
 226         case 1:
 227                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 228                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 229                 break;
 230         case 2:
 231                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 232                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 233                 break;
 234         }
 235 }
 236
 237 struct vcores_data beagle_x15_volts = {
 238         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 239         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 240         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 241         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 242         .mpu.pmic               = &tps659038,
 243         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 244
 245         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 246         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 247         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 248         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 249         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 250         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 251         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 252         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 253         .eve.pmic               = &tps659038,
 254         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 255
 256         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 257         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 258         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 259         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 260         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 261         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 262         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 263         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 264         .gpu.pmic               = &tps659038,
 265         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 266
 267         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 268         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 269         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 270         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 271         .core.pmic              = &tps659038,
 272
 273         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 274         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 275         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 276         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 277         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 278         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 279         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 280         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 281         .iva.pmic               = &tps659038,
 282         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 283 };
 284
 285 struct vcores_data am572x_idk_volts = {
 286         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 287         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 288         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 289         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 290         .mpu.pmic               = &tps659038,
 291         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 292
 293         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 294         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 295         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 296         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 297         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 298         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 299         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 300         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 301         .eve.pmic               = &tps659038,
 302         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 303
 304         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 305         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 306         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 307         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 308         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 309         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 310         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 311         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 312         .gpu.pmic               = &tps659038,
 313         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 314
 315         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 316         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 317         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 318         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 319         .core.pmic              = &tps659038,
 320
 321         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 322         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 323         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 324         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 325         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 326         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 327         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 328         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 329         .iva.pmic               = &tps659038,
 330         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 331 };
 332
 333 int get_voltrail_opp(int rail_offset)
 334 {
 335         int opp;
 336
 337         switch (rail_offset) {
 338         case VOLT_MPU:
 339                 opp = DRA7_MPU_OPP;
 340                 break;
 341         case VOLT_CORE:
 342                 opp = DRA7_CORE_OPP;
 343                 break;
 344         case VOLT_GPU:
 345                 opp = DRA7_GPU_OPP;
 346                 break;
 347         case VOLT_EVE:
 348                 opp = DRA7_DSPEVE_OPP;
 349                 break;
 350         case VOLT_IVA:
 351                 opp = DRA7_IVA_OPP;
 352                 break;
 353         default:
 354                 opp = OPP_NOM;
 355         }
 356
 357         return opp;
 358 }
 359
 360
 361 #ifdef CONFIG_SPL_BUILD
 362 /* No env to setup for SPL */
 363 static inline void setup_board_eeprom_env(void) { }
 364
 365 /* Override function to read eeprom information */
 366 void do_board_detect(void)
 367 {
 368         int rc;
 369
 370         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 371                                   CONFIG_EEPROM_CHIP_ADDRESS);
 372         if (rc)
 373                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 374 }
 375
 376 #else   /* CONFIG_SPL_BUILD */
 377
 378 /* Override function to read eeprom information: actual i2c read done by SPL*/
 379 void do_board_detect(void)
 380 {
 381         char *bname = NULL;
 382         int rc;
 383
 384         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 385                                   CONFIG_EEPROM_CHIP_ADDRESS);
 386         if (rc)
 387                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 388
 389         if (board_is_x15())
 390                 bname = "BeagleBoard X15";
 391         else if (board_is_am572x_evm())
 392                 bname = "AM572x EVM";
 393         else if (board_is_am572x_idk())
 394                 bname = "AM572x IDK";
 395         else if (board_is_am571x_idk())
 396                 bname = "AM571x IDK";
 397
 398         if (bname)
 399                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 400                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 401 }
 402
 403 static void setup_board_eeprom_env(void)
 404 {
 405         char *name = "beagle_x15";
 406         int rc;
 407
 408         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 409                                   CONFIG_EEPROM_CHIP_ADDRESS);
 410         if (rc)
 411                 goto invalid_eeprom;
 412
 413         if (board_is_x15()) {
 414                 if (board_is_x15_revb1())
 415                         name = "beagle_x15_revb1";
 416                 else
 417                         name = "beagle_x15";
 418         } else if (board_is_am572x_evm()) {
 419                 if (board_is_am572x_evm_reva3())
 420                         name = "am57xx_evm_reva3";
 421                 else
 422                         name = "am57xx_evm";
 423         } else if (board_is_am572x_idk()) {
 424                 name = "am572x_idk";
 425         } else if (board_is_am571x_idk()) {
 426                 name = "am571x_idk";
 427         } else {
 428                 printf("Unidentified board claims %s in eeprom header\n",
 429                        board_ti_get_name());
 430         }
 431
 432 invalid_eeprom:
 433         set_board_info_env(name);
 434 }
 435
 436 #endif  /* CONFIG_SPL_BUILD */
 437
 438 void vcores_init(void)
 439 {
 440         if (board_is_am572x_idk())
 441                 *omap_vcores = &am572x_idk_volts;
 442         else
 443                 *omap_vcores = &beagle_x15_volts;
 444 }
 445
 446 void hw_data_init(void)
 447 {
 448         *prcm = &dra7xx_prcm;
 449         *dplls_data = &dra7xx_dplls;
 450         *ctrl = &dra7xx_ctrl;
 451 }
 452
 453 bool am571x_idk_needs_lcd(void)
 454 {
 455         bool needs_lcd;
 456
 457         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 458         if (gpio_get_value(GPIO_ETH_LCD))
 459                 needs_lcd = false;
 460         else
 461                 needs_lcd = true;
 462
 463         gpio_free(GPIO_ETH_LCD);
 464
 465         return needs_lcd;
 466 }
 467
 468 int board_init(void)
 469 {
 470         gpmc_init();
 471         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 472
 473         return 0;
 474 }
 475
 476 int board_late_init(void)
 477 {
 478         char *idk_lcd;
 479
 480         setup_board_eeprom_env();
 481         u8 val;
 482
 483         /*
 484          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 485          * This is the POWERHOLD-in-Low behavior.
 486          */
 487         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 488
 489         /*
 490          * Default FIT boot on HS devices. Non FIT images are not allowed
 491          * on HS devices.
 492          */
 493         if (get_device_type() == HS_DEVICE)
 494                 setenv("boot_fit", "1");
 495
 496         /*
 497          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 498          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 499          * PMIC Power off. So to be on the safer side set it back
 500          * to POWERHOLD mode irrespective of the current state.
 501          */
 502         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 503                            &val);
 504         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 505         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 506                             val);
 507
 508         omap_die_id_serial();
 509
 510         /* TBD: Add LCD panel detection once information is available */
 511         if (am571x_idk_needs_lcd())
 512                 idk_lcd = "osd101t2045"; /* Default to legacy LCD */
 513         else
 514                 idk_lcd = "no";
 515         setenv("idk_lcd", idk_lcd);
 516
 517 #if !defined(CONFIG_SPL_BUILD)
 518         board_ti_set_ethaddr(2);
 519 #endif
 520
 521         return 0;
 522 }
 523
 524 void set_muxconf_regs(void)
 525 {
 526         do_set_mux32((*ctrl)->control_padconf_core_base,
 527                      early_padconf, ARRAY_SIZE(early_padconf));
 528 }
 529
 530 #ifdef CONFIG_IODELAY_RECALIBRATION
 531 void recalibrate_iodelay(void)
 532 {
 533         const struct pad_conf_entry *pconf;
 534         const struct iodelay_cfg_entry *iod;
 535         int pconf_sz, iod_sz;
 536         int ret;
 537
 538         if (board_is_am572x_idk()) {
 539                 pconf = core_padconf_array_essential_am572x_idk;
 540                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 541                 iod = iodelay_cfg_array_am572x_idk;
 542                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 543         } else if (board_is_am571x_idk()) {
 544                 pconf = core_padconf_array_essential_am571x_idk;
 545                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 546                 iod = iodelay_cfg_array_am571x_idk;
 547                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 548         } else {
 549                 /* Common for X15/GPEVM */
 550                 pconf = core_padconf_array_essential_x15;
 551                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 552                 /* There never was an SR1.0 X15.. So.. */
 553                 if (omap_revision() == DRA752_ES1_1) {
 554                         iod = iodelay_cfg_array_x15_sr1_1;
 555                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 556                 } else {
 557                         /* Since full production should switch to SR2.0  */
 558                         iod = iodelay_cfg_array_x15_sr2_0;
 559                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 560                 }
 561         }
 562
 563         /* Setup I/O isolation */
 564         ret = __recalibrate_iodelay_start();
 565         if (ret)
 566                 goto err;
 567
 568         /* Do the muxing here */
 569         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 570
 571         /* Now do the weird minor deltas that should be safe */
 572         if (board_is_x15() || board_is_am572x_evm()) {
 573                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
 574                         pconf = core_padconf_array_delta_x15_sr2_0;
 575                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 576                 } else {
 577                         pconf = core_padconf_array_delta_x15_sr1_1;
 578                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 579                 }
 580                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 581         }
 582
 583         if (board_is_am571x_idk()) {
 584                 if (am571x_idk_needs_lcd()) {
 585                         pconf = core_padconf_array_vout_am571x_idk;
 586                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 587                 } else {
 588                         pconf = core_padconf_array_icss1eth_am571x_idk;
 589                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 590                 }
 591                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 592         }
 593
 594         /* Setup IOdelay configuration */
 595         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 596 err:
 597         /* Closeup.. remove isolation */
 598         __recalibrate_iodelay_end(ret);
 599 }
 600 #endif
 601
 602 #if defined(CONFIG_GENERIC_MMC)
 603 int board_mmc_init(bd_t *bis)
 604 {
 605         omap_mmc_init(0, 0, 0, -1, -1);
 606         omap_mmc_init(1, 0, 0, -1, -1);
 607         return 0;
 608 }
 609 #endif
 610
 611 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 612 int spl_start_uboot(void)
 613 {
 614         /* break into full u-boot on 'c' */
 615         if (serial_tstc() && serial_getc() == 'c')
 616                 return 1;
 617
 618 #ifdef CONFIG_SPL_ENV_SUPPORT
 619         env_init();
 620         env_relocate_spec();
 621         if (getenv_yesno("boot_os") != 1)
 622                 return 1;
 623 #endif
 624
 625         return 0;
 626 }
 627 #endif
 628
 629 #ifdef CONFIG_USB_DWC3
 630 static struct dwc3_device usb_otg_ss2 = {
 631         .maximum_speed = USB_SPEED_HIGH,
 632         .base = DRA7_USB_OTG_SS2_BASE,
 633         .tx_fifo_resize = false,
 634         .index = 1,
 635 };
 636
 637 static struct dwc3_omap_device usb_otg_ss2_glue = {
 638         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 639         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 640         .index = 1,
 641 };
 642
 643 static struct ti_usb_phy_device usb_phy2_device = {
 644         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 645         .index = 1,
 646 };
 647
 648 int usb_gadget_handle_interrupts(int index)
 649 {
 650         u32 status;
 651
 652         status = dwc3_omap_uboot_interrupt_status(index);
 653         if (status)
 654                 dwc3_uboot_handle_interrupt(index);
 655
 656         return 0;
 657 }
 658 #endif /* CONFIG_USB_DWC3 */
 659
 660 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 661 int board_usb_init(int index, enum usb_init_type init)
 662 {
 663         enable_usb_clocks(index);
 664         switch (index) {
 665         case 0:
 666                 if (init == USB_INIT_DEVICE) {
 667                         printf("port %d can't be used as device\n", index);
 668                         disable_usb_clocks(index);
 669                         return -EINVAL;
 670                 }
 671                 break;
 672         case 1:
 673                 if (init == USB_INIT_DEVICE) {
 674 #ifdef CONFIG_USB_DWC3
 675                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 676                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 677                         ti_usb_phy_uboot_init(&usb_phy2_device);
 678                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 679                         dwc3_uboot_init(&usb_otg_ss2);
 680 #endif
 681                 } else {
 682                         printf("port %d can't be used as host\n", index);
 683                         disable_usb_clocks(index);
 684                         return -EINVAL;
 685                 }
 686
 687                 break;
 688         default:
 689                 printf("Invalid Controller Index\n");
 690         }
 691
 692         return 0;
 693 }
 694
 695 int board_usb_cleanup(int index, enum usb_init_type init)
 696 {
 697 #ifdef CONFIG_USB_DWC3
 698         switch (index) {
 699         case 0:
 700         case 1:
 701                 if (init == USB_INIT_DEVICE) {
 702                         ti_usb_phy_uboot_exit(index);
 703                         dwc3_uboot_exit(index);
 704                         dwc3_omap_uboot_exit(index);
 705                 }
 706                 break;
 707         default:
 708                 printf("Invalid Controller Index\n");
 709         }
 710 #endif
 711         disable_usb_clocks(index);
 712         return 0;
 713 }
 714 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 715
 716 #ifdef CONFIG_DRIVER_TI_CPSW
 717
 718 /* Delay value to add to calibrated value */
 719 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 720 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 721 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 722 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 723 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 724 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 725 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 726 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 727 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 728 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 729
 730 static void cpsw_control(int enabled)
 731 {
 732         /* VTP can be added here */
 733 }
 734
 735 static struct cpsw_slave_data cpsw_slaves[] = {
 736         {
 737                 .slave_reg_ofs  = 0x208,
 738                 .sliver_reg_ofs = 0xd80,
 739                 .phy_addr       = 1,
 740         },
 741         {
 742                 .slave_reg_ofs  = 0x308,
 743                 .sliver_reg_ofs = 0xdc0,
 744                 .phy_addr       = 2,
 745         },
 746 };
 747
 748 static struct cpsw_platform_data cpsw_data = {
 749         .mdio_base              = CPSW_MDIO_BASE,
 750         .cpsw_base              = CPSW_BASE,
 751         .mdio_div               = 0xff,
 752         .channels               = 8,
 753         .cpdma_reg_ofs          = 0x800,
 754         .slaves                 = 1,
 755         .slave_data             = cpsw_slaves,
 756         .ale_reg_ofs            = 0xd00,
 757         .ale_entries            = 1024,
 758         .host_port_reg_ofs      = 0x108,
 759         .hw_stats_reg_ofs       = 0x900,
 760         .bd_ram_ofs             = 0x2000,
 761         .mac_control            = (1 << 5),
 762         .control                = cpsw_control,
 763         .host_port_num          = 0,
 764         .version                = CPSW_CTRL_VERSION_2,
 765 };
 766
 767 static u64 mac_to_u64(u8 mac[6])
 768 {
 769         int i;
 770         u64 addr = 0;
 771
 772         for (i = 0; i < 6; i++) {
 773                 addr <<= 8;
 774                 addr |= mac[i];
 775         }
 776
 777         return addr;
 778 }
 779
 780 static void u64_to_mac(u64 addr, u8 mac[6])
 781 {
 782         mac[5] = addr;
 783         mac[4] = addr >> 8;
 784         mac[3] = addr >> 16;
 785         mac[2] = addr >> 24;
 786         mac[1] = addr >> 32;
 787         mac[0] = addr >> 40;
 788 }
 789
 790 int board_eth_init(bd_t *bis)
 791 {
 792         int ret;
 793         uint8_t mac_addr[6];
 794         uint32_t mac_hi, mac_lo;
 795         uint32_t ctrl_val;
 796         int i;
 797         u64 mac1, mac2;
 798         u8 mac_addr1[6], mac_addr2[6];
 799         int num_macs;
 800
 801         /* try reading mac address from efuse */
 802         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 803         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 804         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 805         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 806         mac_addr[2] = mac_hi & 0xFF;
 807         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 808         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 809         mac_addr[5] = mac_lo & 0xFF;
 810
 811         if (!getenv("ethaddr")) {
 812                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 813
 814                 if (is_valid_ethaddr(mac_addr))
 815                         eth_setenv_enetaddr("ethaddr", mac_addr);
 816         }
 817
 818         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 819         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 820         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 821         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 822         mac_addr[2] = mac_hi & 0xFF;
 823         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 824         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 825         mac_addr[5] = mac_lo & 0xFF;
 826
 827         if (!getenv("eth1addr")) {
 828                 if (is_valid_ethaddr(mac_addr))
 829                         eth_setenv_enetaddr("eth1addr", mac_addr);
 830         }
 831
 832         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 833         ctrl_val |= 0x22;
 834         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 835
 836         /* The phy address for the AM57xx IDK are different than x15 */
 837         if (board_is_am572x_idk() || board_is_am571x_idk()) {
 838                 cpsw_data.slave_data[0].phy_addr = 0;
 839                 cpsw_data.slave_data[1].phy_addr = 1;
 840         }
 841
 842         ret = cpsw_register(&cpsw_data);
 843         if (ret < 0)
 844                 printf("Error %d registering CPSW switch\n", ret);
 845
 846         /*
 847          * Export any Ethernet MAC addresses from EEPROM.
 848          * On AM57xx the 2 MAC addresses define the address range
 849          */
 850         board_ti_get_eth_mac_addr(0, mac_addr1);
 851         board_ti_get_eth_mac_addr(1, mac_addr2);
 852
 853         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
 854                 mac1 = mac_to_u64(mac_addr1);
 855                 mac2 = mac_to_u64(mac_addr2);
 856
 857                 /* must contain an address range */
 858                 num_macs = mac2 - mac1 + 1;
 859                 /* <= 50 to protect against user programming error */
 860                 if (num_macs > 0 && num_macs <= 50) {
 861                         for (i = 0; i < num_macs; i++) {
 862                                 u64_to_mac(mac1 + i, mac_addr);
 863                                 if (is_valid_ethaddr(mac_addr)) {
 864                                         eth_setenv_enetaddr_by_index("eth",
 865                                                                      i + 2,
 866                                                                      mac_addr);
 867                                 }
 868                         }
 869                 }
 870         }
 871
 872         return ret;
 873 }
 874 #endif
 875
 876 #ifdef CONFIG_BOARD_EARLY_INIT_F
 877 /* VTT regulator enable */
 878 static inline void vtt_regulator_enable(void)
 879 {
 880         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 881                 return;
 882
 883         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 884         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 885 }
 886
 887 int board_early_init_f(void)
 888 {
 889         vtt_regulator_enable();
 890         return 0;
 891 }
 892 #endif
 893
 894 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 895 int ft_board_setup(void *blob, bd_t *bd)
 896 {
 897         ft_cpu_setup(blob, bd);
 898
 899         return 0;
 900 }
 901 #endif
 902
 903 #ifdef CONFIG_SPL_LOAD_FIT
 904 int board_fit_config_name_match(const char *name)
 905 {
 906         if (board_is_x15()) {
 907                 if (board_is_x15_revb1()) {
 908                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
 909                                 return 0;
 910                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
 911                         return 0;
 912                 }
 913         } else if (board_is_am572x_evm() &&
 914                    !strcmp(name, "am57xx-beagle-x15")) {
 915                 return 0;
 916         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
 917                 return 0;
 918         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
 919                 return 0;
 920         }
 921
 922         return -1;
 923 }
 924 #endif
 925
 926 #ifdef CONFIG_TI_SECURE_DEVICE
 927 void board_fit_image_post_process(void **p_image, size_t *p_size)
 928 {
 929         secure_boot_verify_image(p_image, p_size);
 930 }
 931
 932 void board_tee_image_process(ulong tee_image, size_t tee_size)
 933 {
 934         secure_tee_install((u32)tee_image);
 935 }
 936
 937 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 938 #endif