board/ti/am57xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   4  *
   5  * Author: Felipe Balbi <balbi@ti.com>
   6  *
   7  * Based on board/ti/dra7xx/evm.c
   8  */
   9
  10 #include <common.h>
  11 #include <palmas.h>
  12 #include <sata.h>
  13 #include <usb.h>
  14 #include <asm/omap_common.h>
  15 #include <asm/omap_sec_common.h>
  16 #include <asm/emif.h>
  17 #include <asm/gpio.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/dra7xx_iodelay.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sata.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/omap.h>
  26 #include <environment.h>
  27 #include <usb.h>
  28 #include <linux/usb/gadget.h>
  29 #include <dwc3-uboot.h>
  30 #include <dwc3-omap-uboot.h>
  31 #include <ti-usb-phy-uboot.h>
  32 #include <mmc.h>
  33
  34 #include "../common/board_detect.h"
  35 #include "mux_data.h"
  36
  37 #define board_is_x15()          board_ti_is("BBRDX15_")
  38 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  39                                  !strncmp("B.10", board_ti_get_rev(), 3))
  40 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  41                                  !strncmp("C.00", board_ti_get_rev(), 3))
  42 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  43 #define board_is_am572x_evm_reva3()     \
  44                                 (board_ti_is("AM572PM_") && \
  45                                  !strncmp("A.30", board_ti_get_rev(), 3))
  46 #define board_is_am574x_idk()   board_ti_is("AM574IDK")
  47 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  48 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  49
  50 #ifdef CONFIG_DRIVER_TI_CPSW
  51 #include <cpsw.h>
  52 #endif
  53
  54 DECLARE_GLOBAL_DATA_PTR;
  55
  56 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  57 /* GPIO 7_11 */
  58 #define GPIO_DDR_VTT_EN 203
  59
  60 /* Touch screen controller to identify the LCD */
  61 #define OSD_TS_FT_BUS_ADDRESS   0
  62 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  63 #define OSD_TS_FT_REG_ID        0xA3
  64 /*
  65  * Touchscreen IDs for various OSD panels
  66  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  67  */
  68 /* Used on newer osd101t2587 Panels */
  69 #define OSD_TS_FT_ID_5x46       0x54
  70 /* Used on older osd101t2045 Panels */
  71 #define OSD_TS_FT_ID_5606       0x08
  72
  73 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  74
  75 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  76 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  77
  78 const struct omap_sysinfo sysinfo = {
  79         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  80 };
  81
  82 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  83         .dmm_lisa_map_3 = 0x80740300,
  84         .is_ma_present  = 0x1
  85 };
  86
  87 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  88         .dmm_lisa_map_3 = 0x80640100,
  89         .is_ma_present  = 0x1
  90 };
  91
  92 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
  93         .dmm_lisa_map_2 = 0xc0600200,
  94         .dmm_lisa_map_3 = 0x80600100,
  95         .is_ma_present  = 0x1
  96 };
  97
  98 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  99 {
 100         if (board_is_am571x_idk())
 101                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
 102         else if (board_is_am574x_idk())
 103                 *dmm_lisa_regs = &am574x_idk_lisa_regs;
 104         else
 105                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
 106 }
 107
 108 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 109         .sdram_config_init              = 0x61851b32,
 110         .sdram_config                   = 0x61851b32,
 111         .sdram_config2                  = 0x08000000,
 112         .ref_ctrl                       = 0x000040F1,
 113         .ref_ctrl_final                 = 0x00001035,
 114         .sdram_tim1                     = 0xcccf36ab,
 115         .sdram_tim2                     = 0x308f7fda,
 116         .sdram_tim3                     = 0x409f88a8,
 117         .read_idle_ctrl                 = 0x00050000,
 118         .zq_config                      = 0x5007190b,
 119         .temp_alert_config              = 0x00000000,
 120         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 121         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 122         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 123         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 124         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 125         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 126         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 127         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 128         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 129         .emif_rd_wr_lvl_ctl             = 0x00000000,
 130         .emif_rd_wr_exec_thresh         = 0x00000305
 131 };
 132
 133 /* Ext phy ctrl regs 1-35 */
 134 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 135         0x10040100,
 136         0x00910091,
 137         0x00950095,
 138         0x009B009B,
 139         0x009E009E,
 140         0x00980098,
 141         0x00340034,
 142         0x00350035,
 143         0x00340034,
 144         0x00310031,
 145         0x00340034,
 146         0x007F007F,
 147         0x007F007F,
 148         0x007F007F,
 149         0x007F007F,
 150         0x007F007F,
 151         0x00480048,
 152         0x004A004A,
 153         0x00520052,
 154         0x00550055,
 155         0x00500050,
 156         0x00000000,
 157         0x00600020,
 158         0x40011080,
 159         0x08102040,
 160         0x0,
 161         0x0,
 162         0x0,
 163         0x0,
 164         0x0,
 165         0x0,
 166         0x0,
 167         0x0,
 168         0x0,
 169         0x0
 170 };
 171
 172 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 173         .sdram_config_init              = 0x61851b32,
 174         .sdram_config                   = 0x61851b32,
 175         .sdram_config2                  = 0x08000000,
 176         .ref_ctrl                       = 0x000040F1,
 177         .ref_ctrl_final                 = 0x00001035,
 178         .sdram_tim1                     = 0xcccf36b3,
 179         .sdram_tim2                     = 0x308f7fda,
 180         .sdram_tim3                     = 0x407f88a8,
 181         .read_idle_ctrl                 = 0x00050000,
 182         .zq_config                      = 0x5007190b,
 183         .temp_alert_config              = 0x00000000,
 184         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 185         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 186         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 187         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 188         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 189         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 190         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 191         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 192         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 193         .emif_rd_wr_lvl_ctl             = 0x00000000,
 194         .emif_rd_wr_exec_thresh         = 0x00000305
 195 };
 196
 197 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 198         0x10040100,
 199         0x00910091,
 200         0x00950095,
 201         0x009B009B,
 202         0x009E009E,
 203         0x00980098,
 204         0x00340034,
 205         0x00350035,
 206         0x00340034,
 207         0x00310031,
 208         0x00340034,
 209         0x007F007F,
 210         0x007F007F,
 211         0x007F007F,
 212         0x007F007F,
 213         0x007F007F,
 214         0x00480048,
 215         0x004A004A,
 216         0x00520052,
 217         0x00550055,
 218         0x00500050,
 219         0x00000000,
 220         0x00600020,
 221         0x40011080,
 222         0x08102040,
 223         0x0,
 224         0x0,
 225         0x0,
 226         0x0,
 227         0x0,
 228         0x0,
 229         0x0,
 230         0x0,
 231         0x0,
 232         0x0
 233 };
 234
 235 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 236         .sdram_config_init              = 0x61863332,
 237         .sdram_config                   = 0x61863332,
 238         .sdram_config2                  = 0x08000000,
 239         .ref_ctrl                       = 0x0000514d,
 240         .ref_ctrl_final                 = 0x0000144a,
 241         .sdram_tim1                     = 0xd333887c,
 242         .sdram_tim2                     = 0x30b37fe3,
 243         .sdram_tim3                     = 0x409f8ad8,
 244         .read_idle_ctrl                 = 0x00050000,
 245         .zq_config                      = 0x5007190b,
 246         .temp_alert_config              = 0x00000000,
 247         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 248         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 249         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 250         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 251         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 252         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 253         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 254         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 255         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 256         .emif_rd_wr_lvl_ctl             = 0x00000000,
 257         .emif_rd_wr_exec_thresh         = 0x00000305
 258 };
 259
 260 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
 261         .sdram_config_init              = 0x61863332,
 262         .sdram_config                   = 0x61863332,
 263         .sdram_config2                  = 0x08000000,
 264         .ref_ctrl                       = 0x0000514d,
 265         .ref_ctrl_final                 = 0x0000144a,
 266         .sdram_tim1                     = 0xd333887c,
 267         .sdram_tim2                     = 0x30b37fe3,
 268         .sdram_tim3                     = 0x409f8ad8,
 269         .read_idle_ctrl                 = 0x00050000,
 270         .zq_config                      = 0x5007190b,
 271         .temp_alert_config              = 0x00000000,
 272         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 273         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 274         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 275         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 276         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 277         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 278         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 279         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 280         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 281         .emif_rd_wr_lvl_ctl             = 0x00000000,
 282         .emif_rd_wr_exec_thresh         = 0x00000305,
 283         .emif_ecc_ctrl_reg              = 0xD0000001,
 284         .emif_ecc_address_range_1       = 0x3FFF0000,
 285         .emif_ecc_address_range_2       = 0x00000000
 286 };
 287
 288 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 289 {
 290         switch (emif_nr) {
 291         case 1:
 292                 if (board_is_am571x_idk())
 293                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 294                 else if (board_is_am574x_idk())
 295                         *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
 296                 else
 297                         *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 298                 break;
 299         case 2:
 300                 if (board_is_am574x_idk())
 301                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 302                 else
 303                         *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 304                 break;
 305         }
 306 }
 307
 308 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 309 {
 310         switch (emif_nr) {
 311         case 1:
 312                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 313                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 314                 break;
 315         case 2:
 316                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 317                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 318                 break;
 319         }
 320 }
 321
 322 struct vcores_data beagle_x15_volts = {
 323         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 324         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 325         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 326         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 327         .mpu.pmic               = &tps659038,
 328         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 329
 330         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 331         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 332         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 333         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 334         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 335         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 336         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 337         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 338         .eve.pmic               = &tps659038,
 339         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 340
 341         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 342         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 343         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 344         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 345         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 346         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 347         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 348         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 349         .gpu.pmic               = &tps659038,
 350         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 351
 352         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 353         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 354         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 355         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 356         .core.pmic              = &tps659038,
 357
 358         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 359         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 360         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 361         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 362         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 363         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 364         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 365         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 366         .iva.pmic               = &tps659038,
 367         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 368 };
 369
 370 struct vcores_data am572x_idk_volts = {
 371         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 372         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 373         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 374         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 375         .mpu.pmic               = &tps659038,
 376         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 377
 378         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 379         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 380         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 381         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 382         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 383         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 384         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 385         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 386         .eve.pmic               = &tps659038,
 387         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 388
 389         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 390         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 391         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 392         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 393         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 394         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 395         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 396         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 397         .gpu.pmic               = &tps659038,
 398         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 399
 400         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 401         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 402         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 403         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 404         .core.pmic              = &tps659038,
 405
 406         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 407         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 408         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 409         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 410         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 411         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 412         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 413         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 414         .iva.pmic               = &tps659038,
 415         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 416 };
 417
 418 struct vcores_data am571x_idk_volts = {
 419         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 420         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 421         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 422         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 423         .mpu.pmic               = &tps659038,
 424         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 425
 426         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 427         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 428         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 429         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 430         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 431         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 432         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 433         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 434         .eve.pmic               = &tps659038,
 435         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 436
 437         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 438         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 439         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 440         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 441         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 442         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 443         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 444         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 445         .gpu.pmic               = &tps659038,
 446         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 447
 448         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 449         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 450         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 451         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 452         .core.pmic              = &tps659038,
 453
 454         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 455         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 456         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 457         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 458         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 459         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 460         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 461         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 462         .iva.pmic               = &tps659038,
 463         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 464 };
 465
 466 int get_voltrail_opp(int rail_offset)
 467 {
 468         int opp;
 469
 470         switch (rail_offset) {
 471         case VOLT_MPU:
 472                 opp = DRA7_MPU_OPP;
 473                 break;
 474         case VOLT_CORE:
 475                 opp = DRA7_CORE_OPP;
 476                 break;
 477         case VOLT_GPU:
 478                 opp = DRA7_GPU_OPP;
 479                 break;
 480         case VOLT_EVE:
 481                 opp = DRA7_DSPEVE_OPP;
 482                 break;
 483         case VOLT_IVA:
 484                 opp = DRA7_IVA_OPP;
 485                 break;
 486         default:
 487                 opp = OPP_NOM;
 488         }
 489
 490         return opp;
 491 }
 492
 493
 494 #ifdef CONFIG_SPL_BUILD
 495 /* No env to setup for SPL */
 496 static inline void setup_board_eeprom_env(void) { }
 497
 498 /* Override function to read eeprom information */
 499 void do_board_detect(void)
 500 {
 501         int rc;
 502
 503         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 504                                   CONFIG_EEPROM_CHIP_ADDRESS);
 505         if (rc)
 506                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 507 }
 508
 509 #else   /* CONFIG_SPL_BUILD */
 510
 511 /* Override function to read eeprom information: actual i2c read done by SPL*/
 512 void do_board_detect(void)
 513 {
 514         char *bname = NULL;
 515         int rc;
 516
 517         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 518                                   CONFIG_EEPROM_CHIP_ADDRESS);
 519         if (rc)
 520                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 521
 522         if (board_is_x15())
 523                 bname = "BeagleBoard X15";
 524         else if (board_is_am572x_evm())
 525                 bname = "AM572x EVM";
 526         else if (board_is_am574x_idk())
 527                 bname = "AM574x IDK";
 528         else if (board_is_am572x_idk())
 529                 bname = "AM572x IDK";
 530         else if (board_is_am571x_idk())
 531                 bname = "AM571x IDK";
 532
 533         if (bname)
 534                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 535                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 536 }
 537
 538 static void setup_board_eeprom_env(void)
 539 {
 540         char *name = "beagle_x15";
 541         int rc;
 542
 543         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 544                                   CONFIG_EEPROM_CHIP_ADDRESS);
 545         if (rc)
 546                 goto invalid_eeprom;
 547
 548         if (board_is_x15()) {
 549                 if (board_is_x15_revb1())
 550                         name = "beagle_x15_revb1";
 551                 else if (board_is_x15_revc())
 552                         name = "beagle_x15_revc";
 553                 else
 554                         name = "beagle_x15";
 555         } else if (board_is_am572x_evm()) {
 556                 if (board_is_am572x_evm_reva3())
 557                         name = "am57xx_evm_reva3";
 558                 else
 559                         name = "am57xx_evm";
 560         } else if (board_is_am574x_idk()) {
 561                 name = "am574x_idk";
 562         } else if (board_is_am572x_idk()) {
 563                 name = "am572x_idk";
 564         } else if (board_is_am571x_idk()) {
 565                 name = "am571x_idk";
 566         } else {
 567                 printf("Unidentified board claims %s in eeprom header\n",
 568                        board_ti_get_name());
 569         }
 570
 571 invalid_eeprom:
 572         set_board_info_env(name);
 573 }
 574
 575 #endif  /* CONFIG_SPL_BUILD */
 576
 577 void vcores_init(void)
 578 {
 579         if (board_is_am572x_idk() || board_is_am574x_idk())
 580                 *omap_vcores = &am572x_idk_volts;
 581         else if (board_is_am571x_idk())
 582                 *omap_vcores = &am571x_idk_volts;
 583         else
 584                 *omap_vcores = &beagle_x15_volts;
 585 }
 586
 587 void hw_data_init(void)
 588 {
 589         *prcm = &dra7xx_prcm;
 590         if (is_dra72x())
 591                 *dplls_data = &dra72x_dplls;
 592         else if (is_dra76x())
 593                 *dplls_data = &dra76x_dplls;
 594         else
 595                 *dplls_data = &dra7xx_dplls;
 596         *ctrl = &dra7xx_ctrl;
 597 }
 598
 599 bool am571x_idk_needs_lcd(void)
 600 {
 601         bool needs_lcd;
 602
 603         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 604         if (gpio_get_value(GPIO_ETH_LCD))
 605                 needs_lcd = false;
 606         else
 607                 needs_lcd = true;
 608
 609         gpio_free(GPIO_ETH_LCD);
 610
 611         return needs_lcd;
 612 }
 613
 614 int board_init(void)
 615 {
 616         gpmc_init();
 617         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 618
 619         return 0;
 620 }
 621
 622 void am57x_idk_lcd_detect(void)
 623 {
 624         int r = -ENODEV;
 625         char *idk_lcd = "no";
 626         u8 buf = 0;
 627
 628         /* Only valid for IDKs */
 629         if (board_is_x15() || board_is_am572x_evm())
 630                 return;
 631
 632         /* Only AM571x IDK has gpio control detect.. so check that */
 633         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 634                 goto out;
 635
 636 #ifndef CONFIG_DM_I2C
 637         r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
 638         if (r) {
 639                 printf("%s: Failed to set bus address to %d: %d\n",
 640                        __func__, OSD_TS_FT_BUS_ADDRESS, r);
 641                 goto out;
 642         }
 643         r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
 644         if (r) {
 645                 /* AM572x IDK has no explicit settings for optional LCD kit */
 646                 if (board_is_am571x_idk()) {
 647                         printf("%s: Touch screen detect failed: %d!\n",
 648                                __func__, r);
 649                 }
 650                 goto out;
 651         }
 652
 653         /* Read FT ID */
 654         r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
 655         if (r) {
 656                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 657                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 658                        OSD_TS_FT_REG_ID, r);
 659                 goto out;
 660         }
 661 #else
 662         struct udevice *dev;
 663
 664         r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
 665                                     OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
 666         if (r) {
 667                 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
 668                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 669                        r);
 670                 /* AM572x IDK has no explicit settings for optional LCD kit */
 671                 if (board_is_am571x_idk())
 672                         printf("%s: Touch screen detect failed: %d!\n",
 673                                __func__, r);
 674                 goto out;
 675         }
 676
 677         /* Read FT ID */
 678         r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
 679         if (r < 0) {
 680                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 681                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 682                        OSD_TS_FT_REG_ID, r);
 683                 goto out;
 684         }
 685         buf = (u8)r;
 686 #endif
 687
 688         switch (buf) {
 689         case OSD_TS_FT_ID_5606:
 690                 idk_lcd = "osd101t2045";
 691                 break;
 692         case OSD_TS_FT_ID_5x46:
 693                 idk_lcd = "osd101t2587";
 694                 break;
 695         default:
 696                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 697                        __func__, buf);
 698                 /* we will let default be "no lcd" */
 699         }
 700 out:
 701         env_set("idk_lcd", idk_lcd);
 702         return;
 703 }
 704
 705 int board_late_init(void)
 706 {
 707         setup_board_eeprom_env();
 708         u8 val;
 709
 710         /*
 711          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 712          * This is the POWERHOLD-in-Low behavior.
 713          */
 714         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 715
 716         /*
 717          * Default FIT boot on HS devices. Non FIT images are not allowed
 718          * on HS devices.
 719          */
 720         if (get_device_type() == HS_DEVICE)
 721                 env_set("boot_fit", "1");
 722
 723         /*
 724          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 725          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 726          * PMIC Power off. So to be on the safer side set it back
 727          * to POWERHOLD mode irrespective of the current state.
 728          */
 729         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 730                            &val);
 731         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 732         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 733                             val);
 734
 735         omap_die_id_serial();
 736         omap_set_fastboot_vars();
 737
 738         am57x_idk_lcd_detect();
 739
 740 #if !defined(CONFIG_SPL_BUILD)
 741         board_ti_set_ethaddr(2);
 742 #endif
 743
 744         return 0;
 745 }
 746
 747 void set_muxconf_regs(void)
 748 {
 749         do_set_mux32((*ctrl)->control_padconf_core_base,
 750                      early_padconf, ARRAY_SIZE(early_padconf));
 751 }
 752
 753 #ifdef CONFIG_IODELAY_RECALIBRATION
 754 void recalibrate_iodelay(void)
 755 {
 756         const struct pad_conf_entry *pconf;
 757         const struct iodelay_cfg_entry *iod, *delta_iod;
 758         int pconf_sz, iod_sz, delta_iod_sz = 0;
 759         int ret;
 760
 761         if (board_is_am572x_idk()) {
 762                 pconf = core_padconf_array_essential_am572x_idk;
 763                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 764                 iod = iodelay_cfg_array_am572x_idk;
 765                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 766         } else if (board_is_am574x_idk()) {
 767                 pconf = core_padconf_array_essential_am574x_idk;
 768                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
 769                 iod = iodelay_cfg_array_am574x_idk;
 770                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
 771         } else if (board_is_am571x_idk()) {
 772                 pconf = core_padconf_array_essential_am571x_idk;
 773                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 774                 iod = iodelay_cfg_array_am571x_idk;
 775                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 776         } else {
 777                 /* Common for X15/GPEVM */
 778                 pconf = core_padconf_array_essential_x15;
 779                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 780                 /* There never was an SR1.0 X15.. So.. */
 781                 if (omap_revision() == DRA752_ES1_1) {
 782                         iod = iodelay_cfg_array_x15_sr1_1;
 783                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 784                 } else {
 785                         /* Since full production should switch to SR2.0  */
 786                         iod = iodelay_cfg_array_x15_sr2_0;
 787                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 788                 }
 789         }
 790
 791         /* Setup I/O isolation */
 792         ret = __recalibrate_iodelay_start();
 793         if (ret)
 794                 goto err;
 795
 796         /* Do the muxing here */
 797         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 798
 799         /* Now do the weird minor deltas that should be safe */
 800         if (board_is_x15() || board_is_am572x_evm()) {
 801                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 802                     board_is_x15_revc()) {
 803                         pconf = core_padconf_array_delta_x15_sr2_0;
 804                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 805                 } else {
 806                         pconf = core_padconf_array_delta_x15_sr1_1;
 807                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 808                 }
 809                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 810         }
 811
 812         if (board_is_am571x_idk()) {
 813                 if (am571x_idk_needs_lcd()) {
 814                         pconf = core_padconf_array_vout_am571x_idk;
 815                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 816                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 817                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 818
 819                 } else {
 820                         pconf = core_padconf_array_icss1eth_am571x_idk;
 821                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 822                 }
 823                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 824         }
 825
 826         /* Setup IOdelay configuration */
 827         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 828         if (delta_iod_sz)
 829                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 830                                      delta_iod_sz);
 831
 832 err:
 833         /* Closeup.. remove isolation */
 834         __recalibrate_iodelay_end(ret);
 835 }
 836 #endif
 837
 838 #if defined(CONFIG_MMC)
 839 int board_mmc_init(bd_t *bis)
 840 {
 841         omap_mmc_init(0, 0, 0, -1, -1);
 842         omap_mmc_init(1, 0, 0, -1, -1);
 843         return 0;
 844 }
 845
 846 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
 847         .hw_rev = "rev11",
 848         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 849                             MMC_CAP(UHS_SDR104),
 850         .max_freq = 96000000,
 851 };
 852
 853 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
 854         .hw_rev = "rev11",
 855         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 856                             MMC_CAP(UHS_SDR104) |
 857                             MMC_CAP(UHS_SDR50),
 858         .max_freq = 48000000,
 859 };
 860
 861 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 862 {
 863         switch (omap_revision()) {
 864         case DRA752_ES1_0:
 865         case DRA752_ES1_1:
 866                 if (addr == OMAP_HSMMC1_BASE)
 867                         return &am57x_es1_1_mmc1_fixups;
 868                 else
 869                         return &am57x_es1_1_mmc23_fixups;
 870         default:
 871                 return NULL;
 872         }
 873 }
 874 #endif
 875
 876 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 877 int spl_start_uboot(void)
 878 {
 879         /* break into full u-boot on 'c' */
 880         if (serial_tstc() && serial_getc() == 'c')
 881                 return 1;
 882
 883 #ifdef CONFIG_SPL_ENV_SUPPORT
 884         env_init();
 885         env_load();
 886         if (env_get_yesno("boot_os") != 1)
 887                 return 1;
 888 #endif
 889
 890         return 0;
 891 }
 892 #endif
 893
 894 #ifdef CONFIG_USB_DWC3
 895 static struct dwc3_device usb_otg_ss2 = {
 896         .maximum_speed = USB_SPEED_HIGH,
 897         .base = DRA7_USB_OTG_SS2_BASE,
 898         .tx_fifo_resize = false,
 899         .index = 1,
 900 };
 901
 902 static struct dwc3_omap_device usb_otg_ss2_glue = {
 903         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 904         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 905         .index = 1,
 906 };
 907
 908 static struct ti_usb_phy_device usb_phy2_device = {
 909         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 910         .index = 1,
 911 };
 912
 913 int usb_gadget_handle_interrupts(int index)
 914 {
 915         u32 status;
 916
 917         status = dwc3_omap_uboot_interrupt_status(index);
 918         if (status)
 919                 dwc3_uboot_handle_interrupt(index);
 920
 921         return 0;
 922 }
 923 #endif /* CONFIG_USB_DWC3 */
 924
 925 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 926 int board_usb_init(int index, enum usb_init_type init)
 927 {
 928         enable_usb_clocks(index);
 929         switch (index) {
 930         case 0:
 931                 if (init == USB_INIT_DEVICE) {
 932                         printf("port %d can't be used as device\n", index);
 933                         disable_usb_clocks(index);
 934                         return -EINVAL;
 935                 }
 936                 break;
 937         case 1:
 938                 if (init == USB_INIT_DEVICE) {
 939 #ifdef CONFIG_USB_DWC3
 940                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 941                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 942                         ti_usb_phy_uboot_init(&usb_phy2_device);
 943                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 944                         dwc3_uboot_init(&usb_otg_ss2);
 945 #endif
 946                 } else {
 947                         printf("port %d can't be used as host\n", index);
 948                         disable_usb_clocks(index);
 949                         return -EINVAL;
 950                 }
 951
 952                 break;
 953         default:
 954                 printf("Invalid Controller Index\n");
 955         }
 956
 957         return 0;
 958 }
 959
 960 int board_usb_cleanup(int index, enum usb_init_type init)
 961 {
 962 #ifdef CONFIG_USB_DWC3
 963         switch (index) {
 964         case 0:
 965         case 1:
 966                 if (init == USB_INIT_DEVICE) {
 967                         ti_usb_phy_uboot_exit(index);
 968                         dwc3_uboot_exit(index);
 969                         dwc3_omap_uboot_exit(index);
 970                 }
 971                 break;
 972         default:
 973                 printf("Invalid Controller Index\n");
 974         }
 975 #endif
 976         disable_usb_clocks(index);
 977         return 0;
 978 }
 979 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 980
 981 #ifdef CONFIG_DRIVER_TI_CPSW
 982
 983 /* Delay value to add to calibrated value */
 984 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 985 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 986 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 987 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 988 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 989 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 990 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 991 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 992 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 993 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 994
 995 static void cpsw_control(int enabled)
 996 {
 997         /* VTP can be added here */
 998 }
 999
1000 static struct cpsw_slave_data cpsw_slaves[] = {
1001         {
1002                 .slave_reg_ofs  = 0x208,
1003                 .sliver_reg_ofs = 0xd80,
1004                 .phy_addr       = 1,
1005         },
1006         {
1007                 .slave_reg_ofs  = 0x308,
1008                 .sliver_reg_ofs = 0xdc0,
1009                 .phy_addr       = 2,
1010         },
1011 };
1012
1013 static struct cpsw_platform_data cpsw_data = {
1014         .mdio_base              = CPSW_MDIO_BASE,
1015         .cpsw_base              = CPSW_BASE,
1016         .mdio_div               = 0xff,
1017         .channels               = 8,
1018         .cpdma_reg_ofs          = 0x800,
1019         .slaves                 = 1,
1020         .slave_data             = cpsw_slaves,
1021         .ale_reg_ofs            = 0xd00,
1022         .ale_entries            = 1024,
1023         .host_port_reg_ofs      = 0x108,
1024         .hw_stats_reg_ofs       = 0x900,
1025         .bd_ram_ofs             = 0x2000,
1026         .mac_control            = (1 << 5),
1027         .control                = cpsw_control,
1028         .host_port_num          = 0,
1029         .version                = CPSW_CTRL_VERSION_2,
1030 };
1031
1032 static u64 mac_to_u64(u8 mac[6])
1033 {
1034         int i;
1035         u64 addr = 0;
1036
1037         for (i = 0; i < 6; i++) {
1038                 addr <<= 8;
1039                 addr |= mac[i];
1040         }
1041
1042         return addr;
1043 }
1044
1045 static void u64_to_mac(u64 addr, u8 mac[6])
1046 {
1047         mac[5] = addr;
1048         mac[4] = addr >> 8;
1049         mac[3] = addr >> 16;
1050         mac[2] = addr >> 24;
1051         mac[1] = addr >> 32;
1052         mac[0] = addr >> 40;
1053 }
1054
1055 int board_eth_init(bd_t *bis)
1056 {
1057         int ret;
1058         uint8_t mac_addr[6];
1059         uint32_t mac_hi, mac_lo;
1060         uint32_t ctrl_val;
1061         int i;
1062         u64 mac1, mac2;
1063         u8 mac_addr1[6], mac_addr2[6];
1064         int num_macs;
1065
1066         /* try reading mac address from efuse */
1067         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1068         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1069         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1070         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1071         mac_addr[2] = mac_hi & 0xFF;
1072         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1073         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1074         mac_addr[5] = mac_lo & 0xFF;
1075
1076         if (!env_get("ethaddr")) {
1077                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1078
1079                 if (is_valid_ethaddr(mac_addr))
1080                         eth_env_set_enetaddr("ethaddr", mac_addr);
1081         }
1082
1083         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1084         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1085         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1086         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1087         mac_addr[2] = mac_hi & 0xFF;
1088         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1089         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1090         mac_addr[5] = mac_lo & 0xFF;
1091
1092         if (!env_get("eth1addr")) {
1093                 if (is_valid_ethaddr(mac_addr))
1094                         eth_env_set_enetaddr("eth1addr", mac_addr);
1095         }
1096
1097         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1098         ctrl_val |= 0x22;
1099         writel(ctrl_val, (*ctrl)->control_core_control_io1);
1100
1101         /* The phy address for the AM57xx IDK are different than x15 */
1102         if (board_is_am572x_idk() || board_is_am571x_idk() ||
1103             board_is_am574x_idk()) {
1104                 cpsw_data.slave_data[0].phy_addr = 0;
1105                 cpsw_data.slave_data[1].phy_addr = 1;
1106         }
1107
1108         ret = cpsw_register(&cpsw_data);
1109         if (ret < 0)
1110                 printf("Error %d registering CPSW switch\n", ret);
1111
1112         /*
1113          * Export any Ethernet MAC addresses from EEPROM.
1114          * On AM57xx the 2 MAC addresses define the address range
1115          */
1116         board_ti_get_eth_mac_addr(0, mac_addr1);
1117         board_ti_get_eth_mac_addr(1, mac_addr2);
1118
1119         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1120                 mac1 = mac_to_u64(mac_addr1);
1121                 mac2 = mac_to_u64(mac_addr2);
1122
1123                 /* must contain an address range */
1124                 num_macs = mac2 - mac1 + 1;
1125                 /* <= 50 to protect against user programming error */
1126                 if (num_macs > 0 && num_macs <= 50) {
1127                         for (i = 0; i < num_macs; i++) {
1128                                 u64_to_mac(mac1 + i, mac_addr);
1129                                 if (is_valid_ethaddr(mac_addr)) {
1130                                         eth_env_set_enetaddr_by_index("eth",
1131                                                                       i + 2,
1132                                                                       mac_addr);
1133                                 }
1134                         }
1135                 }
1136         }
1137
1138         return ret;
1139 }
1140 #endif
1141
1142 #ifdef CONFIG_BOARD_EARLY_INIT_F
1143 /* VTT regulator enable */
1144 static inline void vtt_regulator_enable(void)
1145 {
1146         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1147                 return;
1148
1149         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1150         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1151 }
1152
1153 int board_early_init_f(void)
1154 {
1155         vtt_regulator_enable();
1156         return 0;
1157 }
1158 #endif
1159
1160 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1161 int ft_board_setup(void *blob, bd_t *bd)
1162 {
1163         ft_cpu_setup(blob, bd);
1164
1165         return 0;
1166 }
1167 #endif
1168
1169 #ifdef CONFIG_SPL_LOAD_FIT
1170 int board_fit_config_name_match(const char *name)
1171 {
1172         if (board_is_x15()) {
1173                 if (board_is_x15_revb1()) {
1174                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1175                                 return 0;
1176                 } else if (board_is_x15_revc()) {
1177                         if (!strcmp(name, "am57xx-beagle-x15-revc"))
1178                                 return 0;
1179                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1180                         return 0;
1181                 }
1182         } else if (board_is_am572x_evm() &&
1183                    !strcmp(name, "am57xx-beagle-x15")) {
1184                 return 0;
1185         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1186                 return 0;
1187         } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1188                 return 0;
1189         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1190                 return 0;
1191         }
1192
1193         return -1;
1194 }
1195 #endif
1196
1197 #ifdef CONFIG_TI_SECURE_DEVICE
1198 void board_fit_image_post_process(void **p_image, size_t *p_size)
1199 {
1200         secure_boot_verify_image(p_image, p_size);
1201 }
1202
1203 void board_tee_image_process(ulong tee_image, size_t tee_size)
1204 {
1205         secure_tee_install((u32)tee_image);
1206 }
1207
1208 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1209 int fastboot_set_reboot_flag(void)
1210 {
1211         printf("Setting reboot to fastboot flag ...\n");
1212         env_set("dofastboot", "1");
1213         env_save();
1214         return 0;
1215 }
1216 #endif
1217
1218 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1219 #endif