1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Felipe Balbi <balbi@ti.com>
7 * Based on board/ti/dra7xx/evm.c
17 #include <asm/omap_common.h>
18 #include <asm/omap_sec_common.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/dra7xx_iodelay.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/mmc_host_def.h>
26 #include <asm/arch/sata.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/omap.h>
30 #include <linux/usb/gadget.h>
31 #include <dwc3-uboot.h>
32 #include <dwc3-omap-uboot.h>
33 #include <ti-usb-phy-uboot.h>
35 #include <dm/uclass.h>
37 #include "../common/board_detect.h"
40 #define board_is_x15() board_ti_is("BBRDX15_")
41 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
42 !strncmp("B.10", board_ti_get_rev(), 3))
43 #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
44 !strncmp("C.00", board_ti_get_rev(), 3))
45 #define board_is_am572x_evm() board_ti_is("AM572PM_")
46 #define board_is_am572x_evm_reva3() \
47 (board_ti_is("AM572PM_") && \
48 !strncmp("A.30", board_ti_get_rev(), 3))
49 #define board_is_am574x_idk() board_ti_is("AM574IDK")
50 #define board_is_am572x_idk() board_ti_is("AM572IDK")
51 #define board_is_am571x_idk() board_ti_is("AM571IDK")
53 #ifdef CONFIG_DRIVER_TI_CPSW
57 DECLARE_GLOBAL_DATA_PTR;
59 #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
61 #define GPIO_DDR_VTT_EN 203
63 /* Touch screen controller to identify the LCD */
64 #define OSD_TS_FT_BUS_ADDRESS 0
65 #define OSD_TS_FT_CHIP_ADDRESS 0x38
66 #define OSD_TS_FT_REG_ID 0xA3
68 * Touchscreen IDs for various OSD panels
69 * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
71 /* Used on newer osd101t2587 Panels */
72 #define OSD_TS_FT_ID_5x46 0x54
73 /* Used on older osd101t2045 Panels */
74 #define OSD_TS_FT_ID_5606 0x08
76 #define SYSINFO_BOARD_NAME_MAX_LEN 45
78 #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
79 #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
81 const struct omap_sysinfo sysinfo = {
82 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
85 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
86 .dmm_lisa_map_3 = 0x80740300,
90 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
91 .dmm_lisa_map_3 = 0x80640100,
95 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
96 .dmm_lisa_map_2 = 0xc0600200,
97 .dmm_lisa_map_3 = 0x80600100,
101 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
103 if (board_is_am571x_idk())
104 *dmm_lisa_regs = &am571x_idk_lisa_regs;
105 else if (board_is_am574x_idk())
106 *dmm_lisa_regs = &am574x_idk_lisa_regs;
108 *dmm_lisa_regs = &beagle_x15_lisa_regs;
111 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
112 .sdram_config_init = 0x61851b32,
113 .sdram_config = 0x61851b32,
114 .sdram_config2 = 0x08000000,
115 .ref_ctrl = 0x000040F1,
116 .ref_ctrl_final = 0x00001035,
117 .sdram_tim1 = 0xcccf36ab,
118 .sdram_tim2 = 0x308f7fda,
119 .sdram_tim3 = 0x409f88a8,
120 .read_idle_ctrl = 0x00050000,
121 .zq_config = 0x5007190b,
122 .temp_alert_config = 0x00000000,
123 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
124 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
125 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
126 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
127 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
128 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
129 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
130 .emif_rd_wr_lvl_rmp_win = 0x00000000,
131 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
132 .emif_rd_wr_lvl_ctl = 0x00000000,
133 .emif_rd_wr_exec_thresh = 0x00000305
136 /* Ext phy ctrl regs 1-35 */
137 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
175 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
176 .sdram_config_init = 0x61851b32,
177 .sdram_config = 0x61851b32,
178 .sdram_config2 = 0x08000000,
179 .ref_ctrl = 0x000040F1,
180 .ref_ctrl_final = 0x00001035,
181 .sdram_tim1 = 0xcccf36b3,
182 .sdram_tim2 = 0x308f7fda,
183 .sdram_tim3 = 0x407f88a8,
184 .read_idle_ctrl = 0x00050000,
185 .zq_config = 0x5007190b,
186 .temp_alert_config = 0x00000000,
187 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
188 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
189 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
190 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
191 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
192 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
193 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
194 .emif_rd_wr_lvl_rmp_win = 0x00000000,
195 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
196 .emif_rd_wr_lvl_ctl = 0x00000000,
197 .emif_rd_wr_exec_thresh = 0x00000305
200 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
238 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
239 .sdram_config_init = 0x61863332,
240 .sdram_config = 0x61863332,
241 .sdram_config2 = 0x08000000,
242 .ref_ctrl = 0x0000514d,
243 .ref_ctrl_final = 0x0000144a,
244 .sdram_tim1 = 0xd333887c,
245 .sdram_tim2 = 0x30b37fe3,
246 .sdram_tim3 = 0x409f8ad8,
247 .read_idle_ctrl = 0x00050000,
248 .zq_config = 0x5007190b,
249 .temp_alert_config = 0x00000000,
250 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
251 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
252 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
253 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
254 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
255 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
256 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
257 .emif_rd_wr_lvl_rmp_win = 0x00000000,
258 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
259 .emif_rd_wr_lvl_ctl = 0x00000000,
260 .emif_rd_wr_exec_thresh = 0x00000305
263 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
264 .sdram_config_init = 0x61863332,
265 .sdram_config = 0x61863332,
266 .sdram_config2 = 0x08000000,
267 .ref_ctrl = 0x0000514d,
268 .ref_ctrl_final = 0x0000144a,
269 .sdram_tim1 = 0xd333887c,
270 .sdram_tim2 = 0x30b37fe3,
271 .sdram_tim3 = 0x409f8ad8,
272 .read_idle_ctrl = 0x00050000,
273 .zq_config = 0x5007190b,
274 .temp_alert_config = 0x00000000,
275 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
276 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
277 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
278 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
279 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
280 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
281 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
282 .emif_rd_wr_lvl_rmp_win = 0x00000000,
283 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
284 .emif_rd_wr_lvl_ctl = 0x00000000,
285 .emif_rd_wr_exec_thresh = 0x00000305,
286 .emif_ecc_ctrl_reg = 0xD0000001,
287 .emif_ecc_address_range_1 = 0x3FFF0000,
288 .emif_ecc_address_range_2 = 0x00000000
291 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
295 if (board_is_am571x_idk())
296 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
297 else if (board_is_am574x_idk())
298 *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
300 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
303 if (board_is_am574x_idk())
304 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
306 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
311 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
315 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
316 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
319 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
320 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
325 struct vcores_data beagle_x15_volts = {
326 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
327 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
328 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
329 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
330 .mpu.pmic = &tps659038,
331 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
333 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
334 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
335 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
336 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
337 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
338 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
339 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
340 .eve.addr = TPS659038_REG_ADDR_SMPS45,
341 .eve.pmic = &tps659038,
342 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
344 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
345 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
346 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
347 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
348 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
349 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
350 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
351 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
352 .gpu.pmic = &tps659038,
353 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
355 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
356 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
357 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
358 .core.addr = TPS659038_REG_ADDR_SMPS6,
359 .core.pmic = &tps659038,
361 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
362 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
363 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
364 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
365 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
366 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
367 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
368 .iva.addr = TPS659038_REG_ADDR_SMPS45,
369 .iva.pmic = &tps659038,
370 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
373 struct vcores_data am572x_idk_volts = {
374 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
375 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
376 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
377 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
378 .mpu.pmic = &tps659038,
379 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
381 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
382 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
383 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
384 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
385 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
386 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
387 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
388 .eve.addr = TPS659038_REG_ADDR_SMPS45,
389 .eve.pmic = &tps659038,
390 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
392 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
393 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
394 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
395 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
396 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
397 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
398 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
399 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
400 .gpu.pmic = &tps659038,
401 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
403 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
404 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
405 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
406 .core.addr = TPS659038_REG_ADDR_SMPS7,
407 .core.pmic = &tps659038,
409 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
410 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
411 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
412 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
413 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
414 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
415 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
416 .iva.addr = TPS659038_REG_ADDR_SMPS8,
417 .iva.pmic = &tps659038,
418 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
421 struct vcores_data am571x_idk_volts = {
422 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
423 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
424 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
425 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
426 .mpu.pmic = &tps659038,
427 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
429 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
430 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
431 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
432 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
433 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
434 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
435 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
436 .eve.addr = TPS659038_REG_ADDR_SMPS45,
437 .eve.pmic = &tps659038,
438 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
440 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
441 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
442 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
443 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
444 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
445 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
446 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
447 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
448 .gpu.pmic = &tps659038,
449 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
451 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
452 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
453 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
454 .core.addr = TPS659038_REG_ADDR_SMPS7,
455 .core.pmic = &tps659038,
457 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
458 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
459 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
460 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
461 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
462 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
463 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
464 .iva.addr = TPS659038_REG_ADDR_SMPS45,
465 .iva.pmic = &tps659038,
466 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
469 int get_voltrail_opp(int rail_offset)
473 switch (rail_offset) {
484 opp = DRA7_DSPEVE_OPP;
497 #ifdef CONFIG_SPL_BUILD
498 /* No env to setup for SPL */
499 static inline void setup_board_eeprom_env(void) { }
501 /* Override function to read eeprom information */
502 void do_board_detect(void)
506 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
507 CONFIG_EEPROM_CHIP_ADDRESS);
509 printf("ti_i2c_eeprom_init failed %d\n", rc);
512 #else /* CONFIG_SPL_BUILD */
514 /* Override function to read eeprom information: actual i2c read done by SPL*/
515 void do_board_detect(void)
520 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
521 CONFIG_EEPROM_CHIP_ADDRESS);
523 printf("ti_i2c_eeprom_init failed %d\n", rc);
526 bname = "BeagleBoard X15";
527 else if (board_is_am572x_evm())
528 bname = "AM572x EVM";
529 else if (board_is_am574x_idk())
530 bname = "AM574x IDK";
531 else if (board_is_am572x_idk())
532 bname = "AM572x IDK";
533 else if (board_is_am571x_idk())
534 bname = "AM571x IDK";
537 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
538 "Board: %s REV %s\n", bname, board_ti_get_rev());
541 static void setup_board_eeprom_env(void)
543 char *name = "beagle_x15";
546 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
547 CONFIG_EEPROM_CHIP_ADDRESS);
551 if (board_is_x15()) {
552 if (board_is_x15_revb1())
553 name = "beagle_x15_revb1";
554 else if (board_is_x15_revc())
555 name = "beagle_x15_revc";
558 } else if (board_is_am572x_evm()) {
559 if (board_is_am572x_evm_reva3())
560 name = "am57xx_evm_reva3";
563 } else if (board_is_am574x_idk()) {
565 } else if (board_is_am572x_idk()) {
567 } else if (board_is_am571x_idk()) {
570 printf("Unidentified board claims %s in eeprom header\n",
571 board_ti_get_name());
575 set_board_info_env(name);
578 #endif /* CONFIG_SPL_BUILD */
580 void vcores_init(void)
582 if (board_is_am572x_idk() || board_is_am574x_idk())
583 *omap_vcores = &am572x_idk_volts;
584 else if (board_is_am571x_idk())
585 *omap_vcores = &am571x_idk_volts;
587 *omap_vcores = &beagle_x15_volts;
590 void hw_data_init(void)
592 *prcm = &dra7xx_prcm;
594 *dplls_data = &dra72x_dplls;
595 else if (is_dra76x())
596 *dplls_data = &dra76x_dplls;
598 *dplls_data = &dra7xx_dplls;
599 *ctrl = &dra7xx_ctrl;
602 bool am571x_idk_needs_lcd(void)
606 gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
607 if (gpio_get_value(GPIO_ETH_LCD))
612 gpio_free(GPIO_ETH_LCD);
620 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
625 void am57x_idk_lcd_detect(void)
628 char *idk_lcd = "no";
631 /* Only valid for IDKs */
632 if (board_is_x15() || board_is_am572x_evm())
635 /* Only AM571x IDK has gpio control detect.. so check that */
636 if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
639 r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
640 OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
642 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
643 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
645 /* AM572x IDK has no explicit settings for optional LCD kit */
646 if (board_is_am571x_idk())
647 printf("%s: Touch screen detect failed: %d!\n",
653 r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
655 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
656 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
657 OSD_TS_FT_REG_ID, r);
662 case OSD_TS_FT_ID_5606:
663 idk_lcd = "osd101t2045";
665 case OSD_TS_FT_ID_5x46:
666 idk_lcd = "osd101t2587";
669 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
671 /* we will let default be "no lcd" */
674 env_set("idk_lcd", idk_lcd);
678 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
679 static int device_okay(const char *path)
683 node = fdt_path_offset(gd->fdt_blob, path);
687 return fdtdec_get_is_enabled(gd->fdt_blob, node);
691 int board_late_init(void)
693 setup_board_eeprom_env();
698 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
699 * This is the POWERHOLD-in-Low behavior.
701 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
704 * Default FIT boot on HS devices. Non FIT images are not allowed
707 if (get_device_type() == HS_DEVICE)
708 env_set("boot_fit", "1");
711 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
712 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
713 * PMIC Power off. So to be on the safer side set it back
714 * to POWERHOLD mode irrespective of the current state.
716 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
718 val = val | TPS65903X_PAD2_POWERHOLD_MASK;
719 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
722 omap_die_id_serial();
723 omap_set_fastboot_vars();
725 am57x_idk_lcd_detect();
727 /* Just probe the potentially supported cdce913 device */
728 uclass_get_device(UCLASS_CLK, 0, &dev);
730 #if !defined(CONFIG_SPL_BUILD)
731 board_ti_set_ethaddr(2);
734 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
735 if (device_okay("/ocp/omap_dwc3_1@48880000"))
736 enable_usb_clocks(0);
737 if (device_okay("/ocp/omap_dwc3_2@488c0000"))
738 enable_usb_clocks(1);
743 void set_muxconf_regs(void)
745 do_set_mux32((*ctrl)->control_padconf_core_base,
746 early_padconf, ARRAY_SIZE(early_padconf));
749 #ifdef CONFIG_IODELAY_RECALIBRATION
750 void recalibrate_iodelay(void)
752 const struct pad_conf_entry *pconf;
753 const struct iodelay_cfg_entry *iod, *delta_iod;
754 int pconf_sz, iod_sz, delta_iod_sz = 0;
757 if (board_is_am572x_idk()) {
758 pconf = core_padconf_array_essential_am572x_idk;
759 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
760 iod = iodelay_cfg_array_am572x_idk;
761 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
762 } else if (board_is_am574x_idk()) {
763 pconf = core_padconf_array_essential_am574x_idk;
764 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
765 iod = iodelay_cfg_array_am574x_idk;
766 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
767 } else if (board_is_am571x_idk()) {
768 pconf = core_padconf_array_essential_am571x_idk;
769 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
770 iod = iodelay_cfg_array_am571x_idk;
771 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
773 /* Common for X15/GPEVM */
774 pconf = core_padconf_array_essential_x15;
775 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
776 /* There never was an SR1.0 X15.. So.. */
777 if (omap_revision() == DRA752_ES1_1) {
778 iod = iodelay_cfg_array_x15_sr1_1;
779 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
781 /* Since full production should switch to SR2.0 */
782 iod = iodelay_cfg_array_x15_sr2_0;
783 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
787 /* Setup I/O isolation */
788 ret = __recalibrate_iodelay_start();
792 /* Do the muxing here */
793 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
795 /* Now do the weird minor deltas that should be safe */
796 if (board_is_x15() || board_is_am572x_evm()) {
797 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
798 board_is_x15_revc()) {
799 pconf = core_padconf_array_delta_x15_sr2_0;
800 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
802 pconf = core_padconf_array_delta_x15_sr1_1;
803 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
805 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
808 if (board_is_am571x_idk()) {
809 if (am571x_idk_needs_lcd()) {
810 pconf = core_padconf_array_vout_am571x_idk;
811 pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
812 delta_iod = iodelay_cfg_array_am571x_idk_4port;
813 delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
816 pconf = core_padconf_array_icss1eth_am571x_idk;
817 pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
819 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
822 /* Setup IOdelay configuration */
823 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
825 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
829 /* Closeup.. remove isolation */
830 __recalibrate_iodelay_end(ret);
834 #if defined(CONFIG_MMC)
835 int board_mmc_init(bd_t *bis)
837 omap_mmc_init(0, 0, 0, -1, -1);
838 omap_mmc_init(1, 0, 0, -1, -1);
842 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
844 .unsupported_caps = MMC_CAP(MMC_HS_200) |
846 .max_freq = 96000000,
849 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
851 .unsupported_caps = MMC_CAP(MMC_HS_200) |
852 MMC_CAP(UHS_SDR104) |
854 .max_freq = 48000000,
857 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
859 switch (omap_revision()) {
862 if (addr == OMAP_HSMMC1_BASE)
863 return &am57x_es1_1_mmc1_fixups;
865 return &am57x_es1_1_mmc23_fixups;
872 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
873 int spl_start_uboot(void)
875 /* break into full u-boot on 'c' */
876 if (serial_tstc() && serial_getc() == 'c')
879 #ifdef CONFIG_SPL_ENV_SUPPORT
882 if (env_get_yesno("boot_os") != 1)
890 #ifdef CONFIG_DRIVER_TI_CPSW
892 /* Delay value to add to calibrated value */
893 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
894 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
895 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
896 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
897 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
898 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
899 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
900 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
901 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
902 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
904 static void cpsw_control(int enabled)
906 /* VTP can be added here */
909 static struct cpsw_slave_data cpsw_slaves[] = {
911 .slave_reg_ofs = 0x208,
912 .sliver_reg_ofs = 0xd80,
916 .slave_reg_ofs = 0x308,
917 .sliver_reg_ofs = 0xdc0,
922 static struct cpsw_platform_data cpsw_data = {
923 .mdio_base = CPSW_MDIO_BASE,
924 .cpsw_base = CPSW_BASE,
927 .cpdma_reg_ofs = 0x800,
929 .slave_data = cpsw_slaves,
930 .ale_reg_ofs = 0xd00,
932 .host_port_reg_ofs = 0x108,
933 .hw_stats_reg_ofs = 0x900,
934 .bd_ram_ofs = 0x2000,
935 .mac_control = (1 << 5),
936 .control = cpsw_control,
938 .version = CPSW_CTRL_VERSION_2,
941 static u64 mac_to_u64(u8 mac[6])
946 for (i = 0; i < 6; i++) {
954 static void u64_to_mac(u64 addr, u8 mac[6])
964 int board_eth_init(bd_t *bis)
968 uint32_t mac_hi, mac_lo;
972 u8 mac_addr1[6], mac_addr2[6];
975 /* try reading mac address from efuse */
976 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
977 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
978 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
979 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
980 mac_addr[2] = mac_hi & 0xFF;
981 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
982 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
983 mac_addr[5] = mac_lo & 0xFF;
985 if (!env_get("ethaddr")) {
986 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
988 if (is_valid_ethaddr(mac_addr))
989 eth_env_set_enetaddr("ethaddr", mac_addr);
992 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
993 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
994 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
995 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
996 mac_addr[2] = mac_hi & 0xFF;
997 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
998 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
999 mac_addr[5] = mac_lo & 0xFF;
1001 if (!env_get("eth1addr")) {
1002 if (is_valid_ethaddr(mac_addr))
1003 eth_env_set_enetaddr("eth1addr", mac_addr);
1006 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1008 writel(ctrl_val, (*ctrl)->control_core_control_io1);
1010 /* The phy address for the AM57xx IDK are different than x15 */
1011 if (board_is_am572x_idk() || board_is_am571x_idk() ||
1012 board_is_am574x_idk()) {
1013 cpsw_data.slave_data[0].phy_addr = 0;
1014 cpsw_data.slave_data[1].phy_addr = 1;
1017 ret = cpsw_register(&cpsw_data);
1019 printf("Error %d registering CPSW switch\n", ret);
1022 * Export any Ethernet MAC addresses from EEPROM.
1023 * On AM57xx the 2 MAC addresses define the address range
1025 board_ti_get_eth_mac_addr(0, mac_addr1);
1026 board_ti_get_eth_mac_addr(1, mac_addr2);
1028 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1029 mac1 = mac_to_u64(mac_addr1);
1030 mac2 = mac_to_u64(mac_addr2);
1032 /* must contain an address range */
1033 num_macs = mac2 - mac1 + 1;
1034 /* <= 50 to protect against user programming error */
1035 if (num_macs > 0 && num_macs <= 50) {
1036 for (i = 0; i < num_macs; i++) {
1037 u64_to_mac(mac1 + i, mac_addr);
1038 if (is_valid_ethaddr(mac_addr)) {
1039 eth_env_set_enetaddr_by_index("eth",
1051 #ifdef CONFIG_BOARD_EARLY_INIT_F
1052 /* VTT regulator enable */
1053 static inline void vtt_regulator_enable(void)
1055 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1058 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1059 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1062 int board_early_init_f(void)
1064 vtt_regulator_enable();
1069 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1070 int ft_board_setup(void *blob, bd_t *bd)
1072 ft_cpu_setup(blob, bd);
1078 #ifdef CONFIG_SPL_LOAD_FIT
1079 int board_fit_config_name_match(const char *name)
1081 if (board_is_x15()) {
1082 if (board_is_x15_revb1()) {
1083 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1085 } else if (board_is_x15_revc()) {
1086 if (!strcmp(name, "am57xx-beagle-x15-revc"))
1088 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1091 } else if (board_is_am572x_evm() &&
1092 !strcmp(name, "am57xx-beagle-x15")) {
1094 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1096 } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1098 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1106 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1107 int fastboot_set_reboot_flag(void)
1109 printf("Setting reboot to fastboot flag ...\n");
1110 env_set("dofastboot", "1");
1116 #ifdef CONFIG_TI_SECURE_DEVICE
1117 void board_fit_image_post_process(void **p_image, size_t *p_size)
1119 secure_boot_verify_image(p_image, p_size);
1122 void board_tee_image_process(ulong tee_image, size_t tee_size)
1124 secure_tee_install((u32)tee_image);
1127 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);