1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Felipe Balbi <balbi@ti.com>
7 * Based on board/ti/dra7xx/evm.c
12 #include <fdt_support.h>
22 #include <asm/omap_common.h>
23 #include <asm/omap_sec_common.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/dra7xx_iodelay.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/mmc_host_def.h>
31 #include <asm/arch/sata.h>
32 #include <asm/arch/gpio.h>
33 #include <asm/arch/omap.h>
35 #include <linux/usb/gadget.h>
36 #include <dwc3-uboot.h>
37 #include <dwc3-omap-uboot.h>
38 #include <ti-usb-phy-uboot.h>
40 #include <dm/uclass.h>
43 #include "../common/board_detect.h"
46 #ifdef CONFIG_SUPPORT_EMMC_BOOT
47 static int board_bootmode_has_emmc(void);
50 #define board_is_x15() board_ti_is("BBRDX15_")
51 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
52 !strncmp("B.10", board_ti_get_rev(), 3))
53 #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
54 !strncmp("C.00", board_ti_get_rev(), 3))
55 #define board_is_am572x_evm() board_ti_is("AM572PM_")
56 #define board_is_am572x_evm_reva3() \
57 (board_ti_is("AM572PM_") && \
58 !strncmp("A.30", board_ti_get_rev(), 3))
59 #define board_is_am574x_idk() board_ti_is("AM574IDK")
60 #define board_is_am572x_idk() board_ti_is("AM572IDK")
61 #define board_is_am571x_idk() board_ti_is("AM571IDK")
62 #define board_is_bbai() board_ti_is("BBONE-AI")
64 #ifdef CONFIG_DRIVER_TI_CPSW
68 DECLARE_GLOBAL_DATA_PTR;
70 #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
72 #define GPIO_DDR_VTT_EN 203
74 /* Touch screen controller to identify the LCD */
75 #define OSD_TS_FT_BUS_ADDRESS 0
76 #define OSD_TS_FT_CHIP_ADDRESS 0x38
77 #define OSD_TS_FT_REG_ID 0xA3
79 * Touchscreen IDs for various OSD panels
80 * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
82 /* Used on newer osd101t2587 Panels */
83 #define OSD_TS_FT_ID_5x46 0x54
84 /* Used on older osd101t2045 Panels */
85 #define OSD_TS_FT_ID_5606 0x08
87 #define SYSINFO_BOARD_NAME_MAX_LEN 45
89 #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
90 #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
92 const struct omap_sysinfo sysinfo = {
93 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
96 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
97 .dmm_lisa_map_3 = 0x80740300,
101 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
102 .dmm_lisa_map_3 = 0x80640100,
106 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
107 .dmm_lisa_map_2 = 0xc0600200,
108 .dmm_lisa_map_3 = 0x80600100,
112 static const struct dmm_lisa_map_regs bbai_lisa_regs = {
113 .dmm_lisa_map_3 = 0x80640100,
117 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
119 if (board_is_am571x_idk())
120 *dmm_lisa_regs = &am571x_idk_lisa_regs;
121 else if (board_is_am574x_idk())
122 *dmm_lisa_regs = &am574x_idk_lisa_regs;
123 else if (board_is_bbai())
124 *dmm_lisa_regs = &bbai_lisa_regs;
126 *dmm_lisa_regs = &beagle_x15_lisa_regs;
129 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
130 .sdram_config_init = 0x61851b32,
131 .sdram_config = 0x61851b32,
132 .sdram_config2 = 0x08000000,
133 .ref_ctrl = 0x000040F1,
134 .ref_ctrl_final = 0x00001035,
135 .sdram_tim1 = 0xcccf36ab,
136 .sdram_tim2 = 0x308f7fda,
137 .sdram_tim3 = 0x409f88a8,
138 .read_idle_ctrl = 0x00050000,
139 .zq_config = 0x5007190b,
140 .temp_alert_config = 0x00000000,
141 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
142 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
143 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
144 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
145 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
146 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
147 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
148 .emif_rd_wr_lvl_rmp_win = 0x00000000,
149 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
150 .emif_rd_wr_lvl_ctl = 0x00000000,
151 .emif_rd_wr_exec_thresh = 0x00000305
154 /* Ext phy ctrl regs 1-35 */
155 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
193 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
194 .sdram_config_init = 0x61851b32,
195 .sdram_config = 0x61851b32,
196 .sdram_config2 = 0x08000000,
197 .ref_ctrl = 0x000040F1,
198 .ref_ctrl_final = 0x00001035,
199 .sdram_tim1 = 0xcccf36b3,
200 .sdram_tim2 = 0x308f7fda,
201 .sdram_tim3 = 0x407f88a8,
202 .read_idle_ctrl = 0x00050000,
203 .zq_config = 0x5007190b,
204 .temp_alert_config = 0x00000000,
205 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
206 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
207 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
208 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
209 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
210 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
211 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
212 .emif_rd_wr_lvl_rmp_win = 0x00000000,
213 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
214 .emif_rd_wr_lvl_ctl = 0x00000000,
215 .emif_rd_wr_exec_thresh = 0x00000305
218 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
256 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
257 .sdram_config_init = 0x61863332,
258 .sdram_config = 0x61863332,
259 .sdram_config2 = 0x08000000,
260 .ref_ctrl = 0x0000514d,
261 .ref_ctrl_final = 0x0000144a,
262 .sdram_tim1 = 0xd333887c,
263 .sdram_tim2 = 0x30b37fe3,
264 .sdram_tim3 = 0x409f8ad8,
265 .read_idle_ctrl = 0x00050000,
266 .zq_config = 0x5007190b,
267 .temp_alert_config = 0x00000000,
268 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
269 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
270 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
271 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
272 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
273 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
274 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
275 .emif_rd_wr_lvl_rmp_win = 0x00000000,
276 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
277 .emif_rd_wr_lvl_ctl = 0x00000000,
278 .emif_rd_wr_exec_thresh = 0x00000305
281 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
282 .sdram_config_init = 0x61863332,
283 .sdram_config = 0x61863332,
284 .sdram_config2 = 0x08000000,
285 .ref_ctrl = 0x0000514d,
286 .ref_ctrl_final = 0x0000144a,
287 .sdram_tim1 = 0xd333887c,
288 .sdram_tim2 = 0x30b37fe3,
289 .sdram_tim3 = 0x409f8ad8,
290 .read_idle_ctrl = 0x00050000,
291 .zq_config = 0x5007190b,
292 .temp_alert_config = 0x00000000,
293 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
294 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
295 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
296 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
297 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
298 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
299 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
300 .emif_rd_wr_lvl_rmp_win = 0x00000000,
301 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
302 .emif_rd_wr_lvl_ctl = 0x00000000,
303 .emif_rd_wr_exec_thresh = 0x00000305,
304 .emif_ecc_ctrl_reg = 0xD0000001,
305 .emif_ecc_address_range_1 = 0x3FFF0000,
306 .emif_ecc_address_range_2 = 0x00000000
309 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
313 if (board_is_am571x_idk())
314 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
315 else if (board_is_am574x_idk())
316 *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
318 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
321 if (board_is_am574x_idk())
322 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
324 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
329 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
333 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
334 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
337 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
338 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
343 struct vcores_data beagle_x15_volts = {
344 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
345 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
346 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
347 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
348 .mpu.pmic = &tps659038,
349 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
351 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
352 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
353 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
354 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
355 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
356 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
357 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
358 .eve.addr = TPS659038_REG_ADDR_SMPS45,
359 .eve.pmic = &tps659038,
360 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
362 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
363 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
364 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
365 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
366 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
367 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
368 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
369 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
370 .gpu.pmic = &tps659038,
371 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
373 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
374 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
375 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
376 .core.addr = TPS659038_REG_ADDR_SMPS6,
377 .core.pmic = &tps659038,
379 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
380 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
381 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
382 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
383 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
384 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
385 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
386 .iva.addr = TPS659038_REG_ADDR_SMPS45,
387 .iva.pmic = &tps659038,
388 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
391 struct vcores_data am572x_idk_volts = {
392 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
393 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
394 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
395 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
396 .mpu.pmic = &tps659038,
397 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
399 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
400 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
401 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
402 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
403 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
404 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
405 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
406 .eve.addr = TPS659038_REG_ADDR_SMPS45,
407 .eve.pmic = &tps659038,
408 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
410 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
411 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
412 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
413 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
414 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
415 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
416 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
417 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
418 .gpu.pmic = &tps659038,
419 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
421 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
422 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
423 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
424 .core.addr = TPS659038_REG_ADDR_SMPS7,
425 .core.pmic = &tps659038,
427 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
428 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
429 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
430 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
431 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
432 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
433 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
434 .iva.addr = TPS659038_REG_ADDR_SMPS8,
435 .iva.pmic = &tps659038,
436 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
439 struct vcores_data am571x_idk_volts = {
440 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
441 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
442 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
443 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
444 .mpu.pmic = &tps659038,
445 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
447 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
448 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
449 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
450 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
451 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
452 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
453 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
454 .eve.addr = TPS659038_REG_ADDR_SMPS45,
455 .eve.pmic = &tps659038,
456 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
458 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
459 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
460 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
461 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
462 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
463 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
464 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
465 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
466 .gpu.pmic = &tps659038,
467 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
469 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
470 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
471 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
472 .core.addr = TPS659038_REG_ADDR_SMPS7,
473 .core.pmic = &tps659038,
475 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
476 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
477 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
478 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
479 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
480 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
481 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
482 .iva.addr = TPS659038_REG_ADDR_SMPS45,
483 .iva.pmic = &tps659038,
484 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
487 int get_voltrail_opp(int rail_offset)
491 switch (rail_offset) {
502 opp = DRA7_DSPEVE_OPP;
515 #ifdef CONFIG_SPL_BUILD
516 /* No env to setup for SPL */
517 static inline void setup_board_eeprom_env(void) { }
519 /* Override function to read eeprom information */
520 void do_board_detect(void)
524 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
525 CONFIG_EEPROM_CHIP_ADDRESS);
527 printf("ti_i2c_eeprom_init failed %d\n", rc);
529 #ifdef CONFIG_SUPPORT_EMMC_BOOT
530 rc = board_bootmode_has_emmc();
532 rc = ti_emmc_boardid_get();
534 printf("ti_emmc_boardid_get failed %d\n", rc);
538 #else /* CONFIG_SPL_BUILD */
540 /* Override function to read eeprom information: actual i2c read done by SPL*/
541 void do_board_detect(void)
546 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
547 CONFIG_EEPROM_CHIP_ADDRESS);
549 printf("ti_i2c_eeprom_init failed %d\n", rc);
551 #ifdef CONFIG_SUPPORT_EMMC_BOOT
552 rc = board_bootmode_has_emmc();
554 rc = ti_emmc_boardid_get();
556 printf("ti_emmc_boardid_get failed %d\n", rc);
560 bname = "BeagleBoard X15";
561 else if (board_is_am572x_evm())
562 bname = "AM572x EVM";
563 else if (board_is_am574x_idk())
564 bname = "AM574x IDK";
565 else if (board_is_am572x_idk())
566 bname = "AM572x IDK";
567 else if (board_is_am571x_idk())
568 bname = "AM571x IDK";
569 else if (board_is_bbai())
570 bname = "BeagleBone AI";
573 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
574 "Board: %s REV %s\n", bname, board_ti_get_rev());
577 static void setup_board_eeprom_env(void)
579 char *name = "beagle_x15";
582 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
583 CONFIG_EEPROM_CHIP_ADDRESS);
587 if (board_is_x15()) {
588 if (board_is_x15_revb1())
589 name = "beagle_x15_revb1";
590 else if (board_is_x15_revc())
591 name = "beagle_x15_revc";
594 } else if (board_is_am572x_evm()) {
595 if (board_is_am572x_evm_reva3())
596 name = "am57xx_evm_reva3";
599 } else if (board_is_am574x_idk()) {
601 } else if (board_is_am572x_idk()) {
603 } else if (board_is_am571x_idk()) {
605 } else if (board_is_bbai()) {
606 name = "am5729_beagleboneai";
608 printf("Unidentified board claims %s in eeprom header\n",
609 board_ti_get_name());
613 set_board_info_env(name);
616 #endif /* CONFIG_SPL_BUILD */
618 void vcores_init(void)
620 if (board_is_am572x_idk() || board_is_am574x_idk())
621 *omap_vcores = &am572x_idk_volts;
622 else if (board_is_am571x_idk())
623 *omap_vcores = &am571x_idk_volts;
625 *omap_vcores = &beagle_x15_volts;
628 void hw_data_init(void)
630 *prcm = &dra7xx_prcm;
632 *dplls_data = &dra72x_dplls;
633 else if (is_dra76x())
634 *dplls_data = &dra76x_dplls;
636 *dplls_data = &dra7xx_dplls;
637 *ctrl = &dra7xx_ctrl;
640 bool am571x_idk_needs_lcd(void)
644 gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
645 if (gpio_get_value(GPIO_ETH_LCD))
650 gpio_free(GPIO_ETH_LCD);
658 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
663 void am57x_idk_lcd_detect(void)
666 char *idk_lcd = "no";
669 /* Only valid for IDKs */
670 if (board_is_x15() || board_is_am572x_evm() || board_is_bbai())
673 /* Only AM571x IDK has gpio control detect.. so check that */
674 if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
677 r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
678 OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
680 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
681 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
683 /* AM572x IDK has no explicit settings for optional LCD kit */
684 if (board_is_am571x_idk())
685 printf("%s: Touch screen detect failed: %d!\n",
691 r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
693 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
694 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
695 OSD_TS_FT_REG_ID, r);
700 case OSD_TS_FT_ID_5606:
701 idk_lcd = "osd101t2045";
703 case OSD_TS_FT_ID_5x46:
704 idk_lcd = "osd101t2587";
707 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
709 /* we will let default be "no lcd" */
712 env_set("idk_lcd", idk_lcd);
715 * On AM571x_IDK, no Display with J51 set to LCD is considered as an
716 * invalid configuration and we prevent boot to get user attention.
718 if (board_is_am571x_idk() && am571x_idk_needs_lcd() &&
719 !strncmp(idk_lcd, "no", 2)) {
720 printf("%s: Invalid HW configuration: display not detected/supported but J51 is set. Remove J51 to boot without display.\n",
728 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
729 static int device_okay(const char *path)
733 node = fdt_path_offset(gd->fdt_blob, path);
737 return fdtdec_get_is_enabled(gd->fdt_blob, node);
741 int board_late_init(void)
743 setup_board_eeprom_env();
748 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
749 * This is the POWERHOLD-in-Low behavior.
751 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
754 * Default FIT boot on HS devices. Non FIT images are not allowed
757 if (get_device_type() == HS_DEVICE)
758 env_set("boot_fit", "1");
761 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
762 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
763 * PMIC Power off. So to be on the safer side set it back
764 * to POWERHOLD mode irrespective of the current state.
766 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
768 val = val | TPS65903X_PAD2_POWERHOLD_MASK;
769 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
772 omap_die_id_serial();
773 omap_set_fastboot_vars();
775 am57x_idk_lcd_detect();
777 /* Just probe the potentially supported cdce913 device */
778 uclass_get_device(UCLASS_CLK, 0, &dev);
781 env_set("console", "ttyS0,115200n8");
783 #if !defined(CONFIG_SPL_BUILD)
784 board_ti_set_ethaddr(2);
787 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
788 if (device_okay("/ocp/omap_dwc3_1@48880000"))
789 enable_usb_clocks(0);
790 if (device_okay("/ocp/omap_dwc3_2@488c0000"))
791 enable_usb_clocks(1);
796 void set_muxconf_regs(void)
798 do_set_mux32((*ctrl)->control_padconf_core_base,
799 early_padconf, ARRAY_SIZE(early_padconf));
801 #ifdef CONFIG_SUPPORT_EMMC_BOOT
802 do_set_mux32((*ctrl)->control_padconf_core_base,
803 emmc_padconf, ARRAY_SIZE(emmc_padconf));
807 #ifdef CONFIG_IODELAY_RECALIBRATION
808 void recalibrate_iodelay(void)
810 const struct pad_conf_entry *pconf;
811 const struct iodelay_cfg_entry *iod, *delta_iod;
812 int pconf_sz, iod_sz, delta_iod_sz = 0;
815 if (board_is_am572x_idk()) {
816 pconf = core_padconf_array_essential_am572x_idk;
817 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
818 iod = iodelay_cfg_array_am572x_idk;
819 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
820 } else if (board_is_am574x_idk()) {
821 pconf = core_padconf_array_essential_am574x_idk;
822 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
823 iod = iodelay_cfg_array_am574x_idk;
824 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
825 } else if (board_is_am571x_idk()) {
826 pconf = core_padconf_array_essential_am571x_idk;
827 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
828 iod = iodelay_cfg_array_am571x_idk;
829 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
830 } else if (board_is_bbai()) {
831 pconf = core_padconf_array_essential_bbai;
832 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_bbai);
833 iod = iodelay_cfg_array_bbai;
834 iod_sz = ARRAY_SIZE(iodelay_cfg_array_bbai);
836 /* Common for X15/GPEVM */
837 pconf = core_padconf_array_essential_x15;
838 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
839 /* There never was an SR1.0 X15.. So.. */
840 if (omap_revision() == DRA752_ES1_1) {
841 iod = iodelay_cfg_array_x15_sr1_1;
842 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
844 /* Since full production should switch to SR2.0 */
845 iod = iodelay_cfg_array_x15_sr2_0;
846 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
850 /* Setup I/O isolation */
851 ret = __recalibrate_iodelay_start();
855 /* Do the muxing here */
856 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
858 /* Now do the weird minor deltas that should be safe */
859 if (board_is_x15() || board_is_am572x_evm()) {
860 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
861 board_is_x15_revc()) {
862 pconf = core_padconf_array_delta_x15_sr2_0;
863 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
865 pconf = core_padconf_array_delta_x15_sr1_1;
866 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
868 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
871 if (board_is_am571x_idk()) {
872 if (am571x_idk_needs_lcd()) {
873 pconf = core_padconf_array_vout_am571x_idk;
874 pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
875 delta_iod = iodelay_cfg_array_am571x_idk_4port;
876 delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
879 pconf = core_padconf_array_icss1eth_am571x_idk;
880 pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
882 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
885 /* Setup IOdelay configuration */
886 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
888 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
892 /* Closeup.. remove isolation */
893 __recalibrate_iodelay_end(ret);
897 #if defined(CONFIG_MMC)
898 int board_mmc_init(bd_t *bis)
900 omap_mmc_init(0, 0, 0, -1, -1);
901 omap_mmc_init(1, 0, 0, -1, -1);
905 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
907 .unsupported_caps = MMC_CAP(MMC_HS_200) |
909 .max_freq = 96000000,
912 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
914 .unsupported_caps = MMC_CAP(MMC_HS_200) |
915 MMC_CAP(UHS_SDR104) |
917 .max_freq = 48000000,
920 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
922 switch (omap_revision()) {
925 if (addr == OMAP_HSMMC1_BASE)
926 return &am57x_es1_1_mmc1_fixups;
928 return &am57x_es1_1_mmc23_fixups;
935 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
936 int spl_start_uboot(void)
938 /* break into full u-boot on 'c' */
939 if (serial_tstc() && serial_getc() == 'c')
942 #ifdef CONFIG_SPL_ENV_SUPPORT
945 if (env_get_yesno("boot_os") != 1)
953 #ifdef CONFIG_DRIVER_TI_CPSW
955 /* Delay value to add to calibrated value */
956 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
957 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
958 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
959 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
960 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
961 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
962 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
963 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
964 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
965 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
967 static void cpsw_control(int enabled)
969 /* VTP can be added here */
972 static struct cpsw_slave_data cpsw_slaves[] = {
974 .slave_reg_ofs = 0x208,
975 .sliver_reg_ofs = 0xd80,
979 .slave_reg_ofs = 0x308,
980 .sliver_reg_ofs = 0xdc0,
985 static struct cpsw_platform_data cpsw_data = {
986 .mdio_base = CPSW_MDIO_BASE,
987 .cpsw_base = CPSW_BASE,
990 .cpdma_reg_ofs = 0x800,
992 .slave_data = cpsw_slaves,
993 .ale_reg_ofs = 0xd00,
995 .host_port_reg_ofs = 0x108,
996 .hw_stats_reg_ofs = 0x900,
997 .bd_ram_ofs = 0x2000,
998 .mac_control = (1 << 5),
999 .control = cpsw_control,
1001 .version = CPSW_CTRL_VERSION_2,
1004 static u64 mac_to_u64(u8 mac[6])
1009 for (i = 0; i < 6; i++) {
1017 static void u64_to_mac(u64 addr, u8 mac[6])
1021 mac[3] = addr >> 16;
1022 mac[2] = addr >> 24;
1023 mac[1] = addr >> 32;
1024 mac[0] = addr >> 40;
1027 int board_eth_init(bd_t *bis)
1030 uint8_t mac_addr[6];
1031 uint32_t mac_hi, mac_lo;
1035 u8 mac_addr1[6], mac_addr2[6];
1038 /* try reading mac address from efuse */
1039 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1040 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1041 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1042 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1043 mac_addr[2] = mac_hi & 0xFF;
1044 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1045 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1046 mac_addr[5] = mac_lo & 0xFF;
1048 if (!env_get("ethaddr")) {
1049 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1051 if (is_valid_ethaddr(mac_addr))
1052 eth_env_set_enetaddr("ethaddr", mac_addr);
1055 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1056 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1057 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1058 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1059 mac_addr[2] = mac_hi & 0xFF;
1060 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1061 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1062 mac_addr[5] = mac_lo & 0xFF;
1064 if (!env_get("eth1addr")) {
1065 if (is_valid_ethaddr(mac_addr))
1066 eth_env_set_enetaddr("eth1addr", mac_addr);
1069 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1071 writel(ctrl_val, (*ctrl)->control_core_control_io1);
1073 /* The phy address for the AM57xx IDK are different than x15 */
1074 if (board_is_am572x_idk() || board_is_am571x_idk() ||
1075 board_is_am574x_idk()) {
1076 cpsw_data.slave_data[0].phy_addr = 0;
1077 cpsw_data.slave_data[1].phy_addr = 1;
1080 ret = cpsw_register(&cpsw_data);
1082 printf("Error %d registering CPSW switch\n", ret);
1085 * Export any Ethernet MAC addresses from EEPROM.
1086 * On AM57xx the 2 MAC addresses define the address range
1088 board_ti_get_eth_mac_addr(0, mac_addr1);
1089 board_ti_get_eth_mac_addr(1, mac_addr2);
1091 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1092 mac1 = mac_to_u64(mac_addr1);
1093 mac2 = mac_to_u64(mac_addr2);
1095 /* must contain an address range */
1096 num_macs = mac2 - mac1 + 1;
1097 /* <= 50 to protect against user programming error */
1098 if (num_macs > 0 && num_macs <= 50) {
1099 for (i = 0; i < num_macs; i++) {
1100 u64_to_mac(mac1 + i, mac_addr);
1101 if (is_valid_ethaddr(mac_addr)) {
1102 eth_env_set_enetaddr_by_index("eth",
1114 #ifdef CONFIG_BOARD_EARLY_INIT_F
1115 /* VTT regulator enable */
1116 static inline void vtt_regulator_enable(void)
1118 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1121 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1122 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1125 int board_early_init_f(void)
1127 vtt_regulator_enable();
1132 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1133 int ft_board_setup(void *blob, bd_t *bd)
1135 ft_cpu_setup(blob, bd);
1141 #ifdef CONFIG_SPL_LOAD_FIT
1142 int board_fit_config_name_match(const char *name)
1144 if (board_is_x15()) {
1145 if (board_is_x15_revb1()) {
1146 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1148 } else if (board_is_x15_revc()) {
1149 if (!strcmp(name, "am57xx-beagle-x15-revc"))
1151 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1154 } else if (board_is_am572x_evm() &&
1155 !strcmp(name, "am57xx-beagle-x15")) {
1157 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1159 } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1161 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1163 } else if (board_is_bbai() && !strcmp(name, "am5729-beagleboneai")) {
1171 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1172 int fastboot_set_reboot_flag(void)
1174 printf("Setting reboot to fastboot flag ...\n");
1175 env_set("dofastboot", "1");
1181 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1182 static int board_bootmode_has_emmc(void)
1184 /* Check that boot mode is same as BBAI */
1185 if (gd->arch.omap_boot_mode != 2)
1192 #ifdef CONFIG_TI_SECURE_DEVICE
1193 void board_fit_image_post_process(void **p_image, size_t *p_size)
1195 secure_boot_verify_image(p_image, p_size);
1198 void board_tee_image_process(ulong tee_image, size_t tee_size)
1200 secure_tee_install((u32)tee_image);
1203 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);