board/ti/am57xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   4  *
   5  * Author: Felipe Balbi <balbi@ti.com>
   6  *
   7  * Based on board/ti/dra7xx/evm.c
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <fdt_support.h>
  13 #include <image.h>
  14 #include <init.h>
  15 #include <malloc.h>
  16 #include <net.h>
  17 #include <palmas.h>
  18 #include <sata.h>
  19 #include <serial.h>
  20 #include <usb.h>
  21 #include <errno.h>
  22 #include <asm/omap_common.h>
  23 #include <asm/omap_sec_common.h>
  24 #include <asm/emif.h>
  25 #include <asm/gpio.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/dra7xx_iodelay.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/arch/mmc_host_def.h>
  31 #include <asm/arch/sata.h>
  32 #include <asm/arch/gpio.h>
  33 #include <asm/arch/omap.h>
  34 #include <usb.h>
  35 #include <linux/usb/gadget.h>
  36 #include <dwc3-uboot.h>
  37 #include <dwc3-omap-uboot.h>
  38 #include <ti-usb-phy-uboot.h>
  39 #include <mmc.h>
  40 #include <dm/uclass.h>
  41 #include <hang.h>
  42
  43 #include "../common/board_detect.h"
  44 #include "mux_data.h"
  45
  46 #ifdef CONFIG_SUPPORT_EMMC_BOOT
  47 static int board_bootmode_has_emmc(void);
  48 #endif
  49
  50 #define board_is_x15()          board_ti_is("BBRDX15_")
  51 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  52                                  !strncmp("B.10", board_ti_get_rev(), 3))
  53 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  54                                  !strncmp("C.00", board_ti_get_rev(), 3))
  55 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  56 #define board_is_am572x_evm_reva3()     \
  57                                 (board_ti_is("AM572PM_") && \
  58                                  !strncmp("A.30", board_ti_get_rev(), 3))
  59 #define board_is_am574x_idk()   board_ti_is("AM574IDK")
  60 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  61 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  62 #define board_is_bbai()         board_ti_is("BBONE-AI")
  63
  64 #define board_is_ti_idk()       board_is_am574x_idk() || \
  65                                 board_is_am572x_idk() || \
  66                                 board_is_am571x_idk()
  67
  68 #ifdef CONFIG_DRIVER_TI_CPSW
  69 #include <cpsw.h>
  70 #endif
  71
  72 DECLARE_GLOBAL_DATA_PTR;
  73
  74 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  75 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(7, 11)
  76
  77 /* Touch screen controller to identify the LCD */
  78 #define OSD_TS_FT_BUS_ADDRESS   0
  79 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  80 #define OSD_TS_FT_REG_ID        0xA3
  81 /*
  82  * Touchscreen IDs for various OSD panels
  83  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  84  */
  85 /* Used on newer osd101t2587 Panels */
  86 #define OSD_TS_FT_ID_5x46       0x54
  87 /* Used on older osd101t2045 Panels */
  88 #define OSD_TS_FT_ID_5606       0x08
  89
  90 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  91
  92 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  93 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  94
  95 const struct omap_sysinfo sysinfo = {
  96         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  97 };
  98
  99 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
 100         .dmm_lisa_map_3 = 0x80740300,
 101         .is_ma_present  = 0x1
 102 };
 103
 104 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
 105         .dmm_lisa_map_3 = 0x80640100,
 106         .is_ma_present  = 0x1
 107 };
 108
 109 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
 110         .dmm_lisa_map_2 = 0xc0600200,
 111         .dmm_lisa_map_3 = 0x80600100,
 112         .is_ma_present  = 0x1
 113 };
 114
 115 static const struct dmm_lisa_map_regs bbai_lisa_regs = {
 116         .dmm_lisa_map_3 = 0x80640100,
 117         .is_ma_present  = 0x1
 118 };
 119
 120 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 121 {
 122         if (board_is_am571x_idk())
 123                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
 124         else if (board_is_am574x_idk())
 125                 *dmm_lisa_regs = &am574x_idk_lisa_regs;
 126         else if (board_is_bbai())
 127                 *dmm_lisa_regs = &bbai_lisa_regs;
 128         else
 129                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
 130 }
 131
 132 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 133         .sdram_config_init              = 0x61851b32,
 134         .sdram_config                   = 0x61851b32,
 135         .sdram_config2                  = 0x08000000,
 136         .ref_ctrl                       = 0x000040F1,
 137         .ref_ctrl_final                 = 0x00001035,
 138         .sdram_tim1                     = 0xcccf36ab,
 139         .sdram_tim2                     = 0x308f7fda,
 140         .sdram_tim3                     = 0x409f88a8,
 141         .read_idle_ctrl                 = 0x00050000,
 142         .zq_config                      = 0x5007190b,
 143         .temp_alert_config              = 0x00000000,
 144         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 145         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 146         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 147         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 148         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 149         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 150         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 151         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 152         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 153         .emif_rd_wr_lvl_ctl             = 0x00000000,
 154         .emif_rd_wr_exec_thresh         = 0x00000305
 155 };
 156
 157 /* Ext phy ctrl regs 1-35 */
 158 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 159         0x10040100,
 160         0x00910091,
 161         0x00950095,
 162         0x009B009B,
 163         0x009E009E,
 164         0x00980098,
 165         0x00340034,
 166         0x00350035,
 167         0x00340034,
 168         0x00310031,
 169         0x00340034,
 170         0x007F007F,
 171         0x007F007F,
 172         0x007F007F,
 173         0x007F007F,
 174         0x007F007F,
 175         0x00480048,
 176         0x004A004A,
 177         0x00520052,
 178         0x00550055,
 179         0x00500050,
 180         0x00000000,
 181         0x00600020,
 182         0x40011080,
 183         0x08102040,
 184         0x0,
 185         0x0,
 186         0x0,
 187         0x0,
 188         0x0,
 189         0x0,
 190         0x0,
 191         0x0,
 192         0x0,
 193         0x0
 194 };
 195
 196 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 197         .sdram_config_init              = 0x61851b32,
 198         .sdram_config                   = 0x61851b32,
 199         .sdram_config2                  = 0x08000000,
 200         .ref_ctrl                       = 0x000040F1,
 201         .ref_ctrl_final                 = 0x00001035,
 202         .sdram_tim1                     = 0xcccf36b3,
 203         .sdram_tim2                     = 0x308f7fda,
 204         .sdram_tim3                     = 0x407f88a8,
 205         .read_idle_ctrl                 = 0x00050000,
 206         .zq_config                      = 0x5007190b,
 207         .temp_alert_config              = 0x00000000,
 208         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 209         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 210         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 211         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 212         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 213         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 214         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 215         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 216         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 217         .emif_rd_wr_lvl_ctl             = 0x00000000,
 218         .emif_rd_wr_exec_thresh         = 0x00000305
 219 };
 220
 221 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 222         0x10040100,
 223         0x00910091,
 224         0x00950095,
 225         0x009B009B,
 226         0x009E009E,
 227         0x00980098,
 228         0x00340034,
 229         0x00350035,
 230         0x00340034,
 231         0x00310031,
 232         0x00340034,
 233         0x007F007F,
 234         0x007F007F,
 235         0x007F007F,
 236         0x007F007F,
 237         0x007F007F,
 238         0x00480048,
 239         0x004A004A,
 240         0x00520052,
 241         0x00550055,
 242         0x00500050,
 243         0x00000000,
 244         0x00600020,
 245         0x40011080,
 246         0x08102040,
 247         0x0,
 248         0x0,
 249         0x0,
 250         0x0,
 251         0x0,
 252         0x0,
 253         0x0,
 254         0x0,
 255         0x0,
 256         0x0
 257 };
 258
 259 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 260         .sdram_config_init              = 0x61863332,
 261         .sdram_config                   = 0x61863332,
 262         .sdram_config2                  = 0x08000000,
 263         .ref_ctrl                       = 0x0000514d,
 264         .ref_ctrl_final                 = 0x0000144a,
 265         .sdram_tim1                     = 0xd333887c,
 266         .sdram_tim2                     = 0x30b37fe3,
 267         .sdram_tim3                     = 0x409f8ad8,
 268         .read_idle_ctrl                 = 0x00050000,
 269         .zq_config                      = 0x5007190b,
 270         .temp_alert_config              = 0x00000000,
 271         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 272         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 273         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 274         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 275         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 276         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 277         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 278         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 279         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 280         .emif_rd_wr_lvl_ctl             = 0x00000000,
 281         .emif_rd_wr_exec_thresh         = 0x00000305
 282 };
 283
 284 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
 285         .sdram_config_init              = 0x61863332,
 286         .sdram_config                   = 0x61863332,
 287         .sdram_config2                  = 0x08000000,
 288         .ref_ctrl                       = 0x0000514d,
 289         .ref_ctrl_final                 = 0x0000144a,
 290         .sdram_tim1                     = 0xd333887c,
 291         .sdram_tim2                     = 0x30b37fe3,
 292         .sdram_tim3                     = 0x409f8ad8,
 293         .read_idle_ctrl                 = 0x00050000,
 294         .zq_config                      = 0x5007190b,
 295         .temp_alert_config              = 0x00000000,
 296         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 297         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 298         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 299         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 300         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 301         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 302         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 303         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 304         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 305         .emif_rd_wr_lvl_ctl             = 0x00000000,
 306         .emif_rd_wr_exec_thresh         = 0x00000305,
 307         .emif_ecc_ctrl_reg              = 0xD0000001,
 308         .emif_ecc_address_range_1       = 0x3FFF0000,
 309         .emif_ecc_address_range_2       = 0x00000000
 310 };
 311
 312 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 313 {
 314         switch (emif_nr) {
 315         case 1:
 316                 if (board_is_am571x_idk())
 317                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 318                 else if (board_is_am574x_idk())
 319                         *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
 320                 else
 321                         *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 322                 break;
 323         case 2:
 324                 if (board_is_am574x_idk())
 325                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 326                 else
 327                         *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 328                 break;
 329         }
 330 }
 331
 332 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 333 {
 334         switch (emif_nr) {
 335         case 1:
 336                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 337                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 338                 break;
 339         case 2:
 340                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 341                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 342                 break;
 343         }
 344 }
 345
 346 struct vcores_data beagle_x15_volts = {
 347         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 348         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 349         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 350         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 351         .mpu.pmic               = &tps659038,
 352         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 353
 354         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 355         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 356         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 357         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 358         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 359         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 360         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 361         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 362         .eve.pmic               = &tps659038,
 363         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 364
 365         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 366         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 367         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 368         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 369         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 370         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 371         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 372         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 373         .gpu.pmic               = &tps659038,
 374         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 375
 376         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 377         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 378         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 379         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 380         .core.pmic              = &tps659038,
 381
 382         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 383         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 384         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 385         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 386         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 387         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 388         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 389         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 390         .iva.pmic               = &tps659038,
 391         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 392 };
 393
 394 struct vcores_data am572x_idk_volts = {
 395         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 396         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 397         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 398         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 399         .mpu.pmic               = &tps659038,
 400         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 401
 402         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 403         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 404         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 405         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 406         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 407         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 408         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 409         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 410         .eve.pmic               = &tps659038,
 411         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 412
 413         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 414         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 415         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 416         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 417         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 418         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 419         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 420         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 421         .gpu.pmic               = &tps659038,
 422         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 423
 424         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 425         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 426         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 427         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 428         .core.pmic              = &tps659038,
 429
 430         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 431         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 432         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 433         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 434         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 435         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 436         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 437         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 438         .iva.pmic               = &tps659038,
 439         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 440 };
 441
 442 struct vcores_data am571x_idk_volts = {
 443         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 444         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 445         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 446         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 447         .mpu.pmic               = &tps659038,
 448         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 449
 450         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 451         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 452         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 453         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 454         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 455         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 456         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 457         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 458         .eve.pmic               = &tps659038,
 459         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 460
 461         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 462         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 463         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 464         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 465         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 466         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 467         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 468         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 469         .gpu.pmic               = &tps659038,
 470         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 471
 472         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 473         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 474         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 475         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 476         .core.pmic              = &tps659038,
 477
 478         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 479         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 480         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 481         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 482         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 483         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 484         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 485         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 486         .iva.pmic               = &tps659038,
 487         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 488 };
 489
 490 int get_voltrail_opp(int rail_offset)
 491 {
 492         int opp;
 493
 494         switch (rail_offset) {
 495         case VOLT_MPU:
 496                 opp = DRA7_MPU_OPP;
 497                 break;
 498         case VOLT_CORE:
 499                 opp = DRA7_CORE_OPP;
 500                 break;
 501         case VOLT_GPU:
 502                 opp = DRA7_GPU_OPP;
 503                 break;
 504         case VOLT_EVE:
 505                 opp = DRA7_DSPEVE_OPP;
 506                 break;
 507         case VOLT_IVA:
 508                 opp = DRA7_IVA_OPP;
 509                 break;
 510         default:
 511                 opp = OPP_NOM;
 512         }
 513
 514         return opp;
 515 }
 516
 517
 518 #ifdef CONFIG_SPL_BUILD
 519 /* No env to setup for SPL */
 520 static inline void setup_board_eeprom_env(void) { }
 521
 522 /* Override function to read eeprom information */
 523 void do_board_detect(void)
 524 {
 525         int rc;
 526
 527         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 528                                   CONFIG_EEPROM_CHIP_ADDRESS);
 529         if (rc)
 530                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 531
 532 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 533         rc = board_bootmode_has_emmc();
 534         if (!rc)
 535                 rc = ti_emmc_boardid_get();
 536         if (rc)
 537                 printf("ti_emmc_boardid_get failed %d\n", rc);
 538 #endif
 539 }
 540
 541 #else   /* CONFIG_SPL_BUILD */
 542
 543 /* Override function to read eeprom information: actual i2c read done by SPL*/
 544 void do_board_detect(void)
 545 {
 546         char *bname = NULL;
 547         int rc;
 548
 549         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 550                                   CONFIG_EEPROM_CHIP_ADDRESS);
 551         if (rc)
 552                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 553
 554 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 555         rc = board_bootmode_has_emmc();
 556         if (!rc)
 557                 rc = ti_emmc_boardid_get();
 558         if (rc)
 559                 printf("ti_emmc_boardid_get failed %d\n", rc);
 560 #endif
 561
 562         if (board_is_x15())
 563                 bname = "BeagleBoard X15";
 564         else if (board_is_am572x_evm())
 565                 bname = "AM572x EVM";
 566         else if (board_is_am574x_idk())
 567                 bname = "AM574x IDK";
 568         else if (board_is_am572x_idk())
 569                 bname = "AM572x IDK";
 570         else if (board_is_am571x_idk())
 571                 bname = "AM571x IDK";
 572         else if (board_is_bbai())
 573                 bname = "BeagleBone AI";
 574
 575         if (bname)
 576                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 577                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 578 }
 579
 580 static void setup_board_eeprom_env(void)
 581 {
 582         char *name = "beagle_x15";
 583         int rc;
 584
 585         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 586                                   CONFIG_EEPROM_CHIP_ADDRESS);
 587         if (rc)
 588                 goto invalid_eeprom;
 589
 590         if (board_is_x15()) {
 591                 if (board_is_x15_revb1())
 592                         name = "beagle_x15_revb1";
 593                 else if (board_is_x15_revc())
 594                         name = "beagle_x15_revc";
 595                 else
 596                         name = "beagle_x15";
 597         } else if (board_is_am572x_evm()) {
 598                 if (board_is_am572x_evm_reva3())
 599                         name = "am57xx_evm_reva3";
 600                 else
 601                         name = "am57xx_evm";
 602         } else if (board_is_am574x_idk()) {
 603                 name = "am574x_idk";
 604         } else if (board_is_am572x_idk()) {
 605                 name = "am572x_idk";
 606         } else if (board_is_am571x_idk()) {
 607                 name = "am571x_idk";
 608         } else if (board_is_bbai()) {
 609                 name = "am5729_beagleboneai";
 610         } else {
 611                 printf("Unidentified board claims %s in eeprom header\n",
 612                        board_ti_get_name());
 613         }
 614
 615 invalid_eeprom:
 616         set_board_info_env(name);
 617 }
 618
 619 #endif  /* CONFIG_SPL_BUILD */
 620
 621 void vcores_init(void)
 622 {
 623         if (board_is_am572x_idk() || board_is_am574x_idk())
 624                 *omap_vcores = &am572x_idk_volts;
 625         else if (board_is_am571x_idk())
 626                 *omap_vcores = &am571x_idk_volts;
 627         else
 628                 *omap_vcores = &beagle_x15_volts;
 629 }
 630
 631 void hw_data_init(void)
 632 {
 633         *prcm = &dra7xx_prcm;
 634         if (is_dra72x())
 635                 *dplls_data = &dra72x_dplls;
 636         else if (is_dra76x())
 637                 *dplls_data = &dra76x_dplls;
 638         else
 639                 *dplls_data = &dra7xx_dplls;
 640         *ctrl = &dra7xx_ctrl;
 641 }
 642
 643 bool am571x_idk_needs_lcd(void)
 644 {
 645         bool needs_lcd;
 646
 647         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 648         if (gpio_get_value(GPIO_ETH_LCD))
 649                 needs_lcd = false;
 650         else
 651                 needs_lcd = true;
 652
 653         gpio_free(GPIO_ETH_LCD);
 654
 655         return needs_lcd;
 656 }
 657
 658 int board_init(void)
 659 {
 660         gpmc_init();
 661         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 662
 663         return 0;
 664 }
 665
 666 void am57x_idk_lcd_detect(void)
 667 {
 668         int r = -ENODEV;
 669         char *idk_lcd = "no";
 670         struct udevice *dev;
 671
 672         /* Only valid for IDKs */
 673         if (!board_is_ti_idk())
 674                 return;
 675
 676         /* Only AM571x IDK has gpio control detect.. so check that */
 677         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 678                 goto out;
 679
 680         r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
 681                                     OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
 682         if (r) {
 683                 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
 684                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 685                        r);
 686                 /* AM572x IDK has no explicit settings for optional LCD kit */
 687                 if (board_is_am571x_idk())
 688                         printf("%s: Touch screen detect failed: %d!\n",
 689                                __func__, r);
 690                 goto out;
 691         }
 692
 693         /* Read FT ID */
 694         r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
 695         if (r < 0) {
 696                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 697                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 698                        OSD_TS_FT_REG_ID, r);
 699                 goto out;
 700         }
 701
 702         switch (r) {
 703         case OSD_TS_FT_ID_5606:
 704                 idk_lcd = "osd101t2045";
 705                 break;
 706         case OSD_TS_FT_ID_5x46:
 707                 idk_lcd = "osd101t2587";
 708                 break;
 709         default:
 710                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 711                        __func__, r);
 712                 /* we will let default be "no lcd" */
 713         }
 714 out:
 715         env_set("idk_lcd", idk_lcd);
 716
 717         /*
 718          * On AM571x_IDK, no Display with J51 set to LCD is considered as an
 719          * invalid configuration and we prevent boot to get user attention.
 720          */
 721         if (board_is_am571x_idk() && am571x_idk_needs_lcd() &&
 722             !strncmp(idk_lcd, "no", 2)) {
 723                 printf("%s: Invalid HW configuration: display not detected/supported but J51 is set. Remove J51 to boot without display.\n",
 724                        __func__);
 725                 hang();
 726         }
 727
 728         return;
 729 }
 730
 731 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 732 static int device_okay(const char *path)
 733 {
 734         int node;
 735
 736         node = fdt_path_offset(gd->fdt_blob, path);
 737         if (node < 0)
 738                 return 0;
 739
 740         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 741 }
 742 #endif
 743
 744 int board_late_init(void)
 745 {
 746         setup_board_eeprom_env();
 747         u8 val;
 748         struct udevice *dev;
 749
 750         /*
 751          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 752          * This is the POWERHOLD-in-Low behavior.
 753          */
 754         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 755
 756         /*
 757          * Default FIT boot on HS devices. Non FIT images are not allowed
 758          * on HS devices.
 759          */
 760         if (get_device_type() == HS_DEVICE)
 761                 env_set("boot_fit", "1");
 762
 763         /*
 764          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 765          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 766          * PMIC Power off. So to be on the safer side set it back
 767          * to POWERHOLD mode irrespective of the current state.
 768          */
 769         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 770                            &val);
 771         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 772         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 773                             val);
 774
 775         omap_die_id_serial();
 776         omap_set_fastboot_vars();
 777
 778         am57x_idk_lcd_detect();
 779
 780         /* Just probe the potentially supported cdce913 device */
 781         uclass_get_device(UCLASS_CLK, 0, &dev);
 782
 783         if (board_is_bbai())
 784                 env_set("console", "ttyS0,115200n8");
 785
 786 #if !defined(CONFIG_SPL_BUILD)
 787         board_ti_set_ethaddr(2);
 788 #endif
 789
 790 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 791         if (device_okay("/ocp/omap_dwc3_1@48880000"))
 792                 enable_usb_clocks(0);
 793         if (device_okay("/ocp/omap_dwc3_2@488c0000"))
 794                 enable_usb_clocks(1);
 795 #endif
 796         return 0;
 797 }
 798
 799 void set_muxconf_regs(void)
 800 {
 801         do_set_mux32((*ctrl)->control_padconf_core_base,
 802                      early_padconf, ARRAY_SIZE(early_padconf));
 803
 804 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 805         do_set_mux32((*ctrl)->control_padconf_core_base,
 806                      emmc_padconf, ARRAY_SIZE(emmc_padconf));
 807 #endif
 808 }
 809
 810 #ifdef CONFIG_IODELAY_RECALIBRATION
 811 void recalibrate_iodelay(void)
 812 {
 813         const struct pad_conf_entry *pconf;
 814         const struct iodelay_cfg_entry *iod, *delta_iod;
 815         int pconf_sz, iod_sz, delta_iod_sz = 0;
 816         int ret;
 817
 818         if (board_is_am572x_idk()) {
 819                 pconf = core_padconf_array_essential_am572x_idk;
 820                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 821                 iod = iodelay_cfg_array_am572x_idk;
 822                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 823         } else if (board_is_am574x_idk()) {
 824                 pconf = core_padconf_array_essential_am574x_idk;
 825                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
 826                 iod = iodelay_cfg_array_am574x_idk;
 827                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
 828         } else if (board_is_am571x_idk()) {
 829                 pconf = core_padconf_array_essential_am571x_idk;
 830                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 831                 iod = iodelay_cfg_array_am571x_idk;
 832                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 833         } else if (board_is_bbai()) {
 834                 pconf = core_padconf_array_essential_bbai;
 835                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_bbai);
 836                 iod = iodelay_cfg_array_bbai;
 837                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_bbai);
 838         } else {
 839                 /* Common for X15/GPEVM */
 840                 pconf = core_padconf_array_essential_x15;
 841                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 842                 /* There never was an SR1.0 X15.. So.. */
 843                 if (omap_revision() == DRA752_ES1_1) {
 844                         iod = iodelay_cfg_array_x15_sr1_1;
 845                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 846                 } else {
 847                         /* Since full production should switch to SR2.0  */
 848                         iod = iodelay_cfg_array_x15_sr2_0;
 849                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 850                 }
 851         }
 852
 853         /* Setup I/O isolation */
 854         ret = __recalibrate_iodelay_start();
 855         if (ret)
 856                 goto err;
 857
 858         /* Do the muxing here */
 859         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 860
 861         /* Now do the weird minor deltas that should be safe */
 862         if (board_is_x15() || board_is_am572x_evm()) {
 863                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 864                     board_is_x15_revc()) {
 865                         pconf = core_padconf_array_delta_x15_sr2_0;
 866                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 867                 } else {
 868                         pconf = core_padconf_array_delta_x15_sr1_1;
 869                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 870                 }
 871                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 872         }
 873
 874         if (board_is_am571x_idk()) {
 875                 if (am571x_idk_needs_lcd()) {
 876                         pconf = core_padconf_array_vout_am571x_idk;
 877                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 878                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 879                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 880
 881                 } else {
 882                         pconf = core_padconf_array_icss1eth_am571x_idk;
 883                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 884                 }
 885                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 886         }
 887
 888         /* Setup IOdelay configuration */
 889         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 890         if (delta_iod_sz)
 891                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 892                                      delta_iod_sz);
 893
 894 err:
 895         /* Closeup.. remove isolation */
 896         __recalibrate_iodelay_end(ret);
 897 }
 898 #endif
 899
 900 #if defined(CONFIG_MMC)
 901 int board_mmc_init(bd_t *bis)
 902 {
 903         omap_mmc_init(0, 0, 0, -1, -1);
 904         omap_mmc_init(1, 0, 0, -1, -1);
 905         return 0;
 906 }
 907
 908 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
 909         .hw_rev = "rev11",
 910         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 911                             MMC_CAP(UHS_SDR104),
 912         .max_freq = 96000000,
 913 };
 914
 915 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
 916         .hw_rev = "rev11",
 917         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 918                             MMC_CAP(UHS_SDR104) |
 919                             MMC_CAP(UHS_SDR50),
 920         .max_freq = 48000000,
 921 };
 922
 923 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 924 {
 925         switch (omap_revision()) {
 926         case DRA752_ES1_0:
 927         case DRA752_ES1_1:
 928                 if (addr == OMAP_HSMMC1_BASE)
 929                         return &am57x_es1_1_mmc1_fixups;
 930                 else
 931                         return &am57x_es1_1_mmc23_fixups;
 932         default:
 933                 return NULL;
 934         }
 935 }
 936 #endif
 937
 938 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 939 int spl_start_uboot(void)
 940 {
 941         /* break into full u-boot on 'c' */
 942         if (serial_tstc() && serial_getc() == 'c')
 943                 return 1;
 944
 945 #ifdef CONFIG_SPL_ENV_SUPPORT
 946         env_init();
 947         env_load();
 948         if (env_get_yesno("boot_os") != 1)
 949                 return 1;
 950 #endif
 951
 952         return 0;
 953 }
 954 #endif
 955
 956 #ifdef CONFIG_DRIVER_TI_CPSW
 957
 958 /* Delay value to add to calibrated value */
 959 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 960 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 961 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 962 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 963 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 964 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 965 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 966 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 967 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 968 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 969
 970 static void cpsw_control(int enabled)
 971 {
 972         /* VTP can be added here */
 973 }
 974
 975 static struct cpsw_slave_data cpsw_slaves[] = {
 976         {
 977                 .slave_reg_ofs  = 0x208,
 978                 .sliver_reg_ofs = 0xd80,
 979                 .phy_addr       = 1,
 980         },
 981         {
 982                 .slave_reg_ofs  = 0x308,
 983                 .sliver_reg_ofs = 0xdc0,
 984                 .phy_addr       = 2,
 985         },
 986 };
 987
 988 static struct cpsw_platform_data cpsw_data = {
 989         .mdio_base              = CPSW_MDIO_BASE,
 990         .cpsw_base              = CPSW_BASE,
 991         .mdio_div               = 0xff,
 992         .channels               = 8,
 993         .cpdma_reg_ofs          = 0x800,
 994         .slaves                 = 1,
 995         .slave_data             = cpsw_slaves,
 996         .ale_reg_ofs            = 0xd00,
 997         .ale_entries            = 1024,
 998         .host_port_reg_ofs      = 0x108,
 999         .hw_stats_reg_ofs       = 0x900,
1000         .bd_ram_ofs             = 0x2000,
1001         .mac_control            = (1 << 5),
1002         .control                = cpsw_control,
1003         .host_port_num          = 0,
1004         .version                = CPSW_CTRL_VERSION_2,
1005 };
1006
1007 static u64 mac_to_u64(u8 mac[6])
1008 {
1009         int i;
1010         u64 addr = 0;
1011
1012         for (i = 0; i < 6; i++) {
1013                 addr <<= 8;
1014                 addr |= mac[i];
1015         }
1016
1017         return addr;
1018 }
1019
1020 static void u64_to_mac(u64 addr, u8 mac[6])
1021 {
1022         mac[5] = addr;
1023         mac[4] = addr >> 8;
1024         mac[3] = addr >> 16;
1025         mac[2] = addr >> 24;
1026         mac[1] = addr >> 32;
1027         mac[0] = addr >> 40;
1028 }
1029
1030 int board_eth_init(bd_t *bis)
1031 {
1032         int ret;
1033         uint8_t mac_addr[6];
1034         uint32_t mac_hi, mac_lo;
1035         uint32_t ctrl_val;
1036         int i;
1037         u64 mac1, mac2;
1038         u8 mac_addr1[6], mac_addr2[6];
1039         int num_macs;
1040
1041         /* try reading mac address from efuse */
1042         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1043         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1044         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1045         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1046         mac_addr[2] = mac_hi & 0xFF;
1047         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1048         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1049         mac_addr[5] = mac_lo & 0xFF;
1050
1051         if (!env_get("ethaddr")) {
1052                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1053
1054                 if (is_valid_ethaddr(mac_addr))
1055                         eth_env_set_enetaddr("ethaddr", mac_addr);
1056         }
1057
1058         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1059         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1060         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1061         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1062         mac_addr[2] = mac_hi & 0xFF;
1063         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1064         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1065         mac_addr[5] = mac_lo & 0xFF;
1066
1067         if (!env_get("eth1addr")) {
1068                 if (is_valid_ethaddr(mac_addr))
1069                         eth_env_set_enetaddr("eth1addr", mac_addr);
1070         }
1071
1072         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1073         ctrl_val |= 0x22;
1074         writel(ctrl_val, (*ctrl)->control_core_control_io1);
1075
1076         /* The phy address for the AM57xx IDK are different than x15 */
1077         if (board_is_am572x_idk() || board_is_am571x_idk() ||
1078             board_is_am574x_idk()) {
1079                 cpsw_data.slave_data[0].phy_addr = 0;
1080                 cpsw_data.slave_data[1].phy_addr = 1;
1081         }
1082
1083         ret = cpsw_register(&cpsw_data);
1084         if (ret < 0)
1085                 printf("Error %d registering CPSW switch\n", ret);
1086
1087         /*
1088          * Export any Ethernet MAC addresses from EEPROM.
1089          * On AM57xx the 2 MAC addresses define the address range
1090          */
1091         board_ti_get_eth_mac_addr(0, mac_addr1);
1092         board_ti_get_eth_mac_addr(1, mac_addr2);
1093
1094         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1095                 mac1 = mac_to_u64(mac_addr1);
1096                 mac2 = mac_to_u64(mac_addr2);
1097
1098                 /* must contain an address range */
1099                 num_macs = mac2 - mac1 + 1;
1100                 /* <= 50 to protect against user programming error */
1101                 if (num_macs > 0 && num_macs <= 50) {
1102                         for (i = 0; i < num_macs; i++) {
1103                                 u64_to_mac(mac1 + i, mac_addr);
1104                                 if (is_valid_ethaddr(mac_addr)) {
1105                                         eth_env_set_enetaddr_by_index("eth",
1106                                                                       i + 2,
1107                                                                       mac_addr);
1108                                 }
1109                         }
1110                 }
1111         }
1112
1113         return ret;
1114 }
1115 #endif
1116
1117 #ifdef CONFIG_BOARD_EARLY_INIT_F
1118 /* VTT regulator enable */
1119 static inline void vtt_regulator_enable(void)
1120 {
1121         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1122                 return;
1123
1124         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1125         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1126 }
1127
1128 int board_early_init_f(void)
1129 {
1130         vtt_regulator_enable();
1131         return 0;
1132 }
1133 #endif
1134
1135 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1136 int ft_board_setup(void *blob, bd_t *bd)
1137 {
1138         ft_cpu_setup(blob, bd);
1139
1140         return 0;
1141 }
1142 #endif
1143
1144 #ifdef CONFIG_SPL_LOAD_FIT
1145 int board_fit_config_name_match(const char *name)
1146 {
1147         if (board_is_x15()) {
1148                 if (board_is_x15_revb1()) {
1149                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1150                                 return 0;
1151                 } else if (board_is_x15_revc()) {
1152                         if (!strcmp(name, "am57xx-beagle-x15-revc"))
1153                                 return 0;
1154                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1155                         return 0;
1156                 }
1157         } else if (board_is_am572x_evm() &&
1158                    !strcmp(name, "am57xx-beagle-x15")) {
1159                 return 0;
1160         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1161                 return 0;
1162         } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1163                 return 0;
1164         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1165                 return 0;
1166         } else if (board_is_bbai() && !strcmp(name, "am5729-beagleboneai")) {
1167                 return 0;
1168         }
1169
1170         return -1;
1171 }
1172 #endif
1173
1174 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1175 int fastboot_set_reboot_flag(void)
1176 {
1177         printf("Setting reboot to fastboot flag ...\n");
1178         env_set("dofastboot", "1");
1179         env_save();
1180         return 0;
1181 }
1182 #endif
1183
1184 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1185 static int board_bootmode_has_emmc(void)
1186 {
1187         /* Check that boot mode is same as BBAI */
1188         if (gd->arch.omap_boot_mode != 2)
1189                 return -EIO;
1190
1191         return 0;
1192 }
1193 #endif
1194
1195 #ifdef CONFIG_TI_SECURE_DEVICE
1196 void board_fit_image_post_process(void **p_image, size_t *p_size)
1197 {
1198         secure_boot_verify_image(p_image, p_size);
1199 }
1200
1201 void board_tee_image_process(ulong tee_image, size_t tee_size)
1202 {
1203         secure_tee_install((u32)tee_image);
1204 }
1205
1206 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1207 #endif