board/ti/am43xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TI AM43XX based boards
   6  *
   7  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <eeprom.h>
  12 #include <asm/global_data.h>
  13 #include <dm/uclass.h>
  14 #include <env.h>
  15 #include <fdt_support.h>
  16 #include <i2c.h>
  17 #include <init.h>
  18 #include <net.h>
  19 #include <linux/errno.h>
  20 #include <spl.h>
  21 #include <usb.h>
  22 #include <asm/arch/clock.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/mux.h>
  25 #include <asm/arch/ddr_defs.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/emif.h>
  28 #include <asm/omap_common.h>
  29 #include "../common/board_detect.h"
  30 #include "board.h"
  31 #include <power/pmic.h>
  32 #include <power/tps65218.h>
  33 #include <power/tps62362.h>
  34 #include <linux/usb/gadget.h>
  35 #include <dwc3-uboot.h>
  36 #include <dwc3-omap-uboot.h>
  37 #include <ti-usb-phy-uboot.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  42
  43 /*
  44  * Read header information from EEPROM into global structure.
  45  */
  46 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  47 void do_board_detect(void)
  48 {
  49         /* Ensure I2C is initialized for EEPROM access*/
  50         gpi2c_init();
  51         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  52                                  CONFIG_EEPROM_CHIP_ADDRESS))
  53                 printf("ti_i2c_eeprom_init failed\n");
  54 }
  55 #endif
  56
  57 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
  58
  59 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  60         {       /* 19.2 MHz */
  61                 {125, 3, 2, -1, -1, -1, -1},    /* OPP 50 */
  62                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  63                 {125, 3, 1, -1, -1, -1, -1},    /* OPP 100 */
  64                 {150, 3, 1, -1, -1, -1, -1},    /* OPP 120 */
  65                 {125, 2, 1, -1, -1, -1, -1},    /* OPP TB */
  66                 {625, 11, 1, -1, -1, -1, -1}    /* OPP NT */
  67         },
  68         {       /* 24 MHz */
  69                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  70                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  71                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  72                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  73                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  74                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  75         },
  76         {       /* 25 MHz */
  77                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
  78                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  79                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
  80                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
  81                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
  82                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
  83         },
  84         {       /* 26 MHz */
  85                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
  86                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  87                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
  88                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
  89                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
  90                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
  91         },
  92 };
  93
  94 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  95                 {625, 11, -1, -1, 10, 8, 4},    /* 19.2 MHz */
  96                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
  97                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
  98                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
  99 };
 100
 101 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
 102                 {400, 7, 5, -1, -1, -1, -1},    /* 19.2 MHz */
 103                 {400, 9, 5, -1, -1, -1, -1},    /* 24 MHz */
 104                 {384, 9, 5, -1, -1, -1, -1},    /* 25 MHz */
 105                 {480, 12, 5, -1, -1, -1, -1}    /* 26 MHz */
 106 };
 107
 108 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
 109                 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
 110                 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
 111                 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
 112                 {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
 113 };
 114
 115 const struct dpll_params gp_evm_dpll_ddr = {
 116                 50, 2, 1, -1, 2, -1, -1};
 117
 118 static const struct dpll_params idk_dpll_ddr = {
 119         400, 23, 1, -1, 2, -1, -1
 120 };
 121
 122 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 123         0x00500050,
 124         0x00350035,
 125         0x00350035,
 126         0x00350035,
 127         0x00350035,
 128         0x00350035,
 129         0x00000000,
 130         0x00000000,
 131         0x00000000,
 132         0x00000000,
 133         0x00000000,
 134         0x00000000,
 135         0x00000000,
 136         0x00000000,
 137         0x00000000,
 138         0x00000000,
 139         0x00000000,
 140         0x00000000,
 141         0x40001000,
 142         0x08102040
 143 };
 144
 145 const struct ctrl_ioregs ioregs_lpddr2 = {
 146         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 147         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 148         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 149         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 150         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 151         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 152         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 153         .emif_sdram_config_ext  = 0x1,
 154 };
 155
 156 const struct emif_regs emif_regs_lpddr2 = {
 157         .sdram_config                   = 0x808012BA,
 158         .ref_ctrl                       = 0x0000040D,
 159         .sdram_tim1                     = 0xEA86B411,
 160         .sdram_tim2                     = 0x103A094A,
 161         .sdram_tim3                     = 0x0F6BA37F,
 162         .read_idle_ctrl                 = 0x00050000,
 163         .zq_config                      = 0x50074BE4,
 164         .temp_alert_config              = 0x0,
 165         .emif_rd_wr_lvl_rmp_win         = 0x0,
 166         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 167         .emif_rd_wr_lvl_ctl             = 0x0,
 168         .emif_ddr_phy_ctlr_1            = 0x0E284006,
 169         .emif_rd_wr_exec_thresh         = 0x80000405,
 170         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 171         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 172         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 173         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 174         .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
 175         .emif_prio_class_serv_map       = 0x80000001,
 176         .emif_connect_id_serv_1_map     = 0x80000094,
 177         .emif_connect_id_serv_2_map     = 0x00000000,
 178         .emif_cos_config                        = 0x000FFFFF
 179 };
 180
 181 const struct ctrl_ioregs ioregs_ddr3 = {
 182         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 183         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 184         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 185         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 186         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 187         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 188         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 189         .emif_sdram_config_ext  = 0xc163,
 190 };
 191
 192 const struct emif_regs ddr3_emif_regs_400Mhz = {
 193         .sdram_config                   = 0x638413B2,
 194         .ref_ctrl                       = 0x00000C30,
 195         .sdram_tim1                     = 0xEAAAD4DB,
 196         .sdram_tim2                     = 0x266B7FDA,
 197         .sdram_tim3                     = 0x107F8678,
 198         .read_idle_ctrl                 = 0x00050000,
 199         .zq_config                      = 0x50074BE4,
 200         .temp_alert_config              = 0x0,
 201         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 202         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 203         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 204         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 205         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 206         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 207         .emif_rd_wr_lvl_rmp_win         = 0x0,
 208         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 209         .emif_rd_wr_lvl_ctl             = 0x0,
 210         .emif_rd_wr_exec_thresh         = 0x80000405,
 211         .emif_prio_class_serv_map       = 0x80000001,
 212         .emif_connect_id_serv_1_map     = 0x80000094,
 213         .emif_connect_id_serv_2_map     = 0x00000000,
 214         .emif_cos_config                = 0x000FFFFF
 215 };
 216
 217 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 218 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 219         .sdram_config                   = 0x638413B2,
 220         .ref_ctrl                       = 0x00000C30,
 221         .sdram_tim1                     = 0xEAAAD4DB,
 222         .sdram_tim2                     = 0x266B7FDA,
 223         .sdram_tim3                     = 0x107F8678,
 224         .read_idle_ctrl                 = 0x00050000,
 225         .zq_config                      = 0x50074BE4,
 226         .temp_alert_config              = 0x0,
 227         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 228         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 229         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 230         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 231         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 232         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 233         .emif_rd_wr_exec_thresh         = 0x80000405,
 234         .emif_prio_class_serv_map       = 0x80000001,
 235         .emif_connect_id_serv_1_map     = 0x80000094,
 236         .emif_connect_id_serv_2_map     = 0x00000000,
 237         .emif_cos_config                = 0x000FFFFF
 238 };
 239
 240 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 241 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 242         .sdram_config                   = 0x638413B2,
 243         .ref_ctrl                       = 0x00000C30,
 244         .sdram_tim1                     = 0xEAAAD4DB,
 245         .sdram_tim2                     = 0x266B7FDA,
 246         .sdram_tim3                     = 0x107F8678,
 247         .read_idle_ctrl                 = 0x00050000,
 248         .zq_config                      = 0x50074BE4,
 249         .temp_alert_config              = 0x0,
 250         .emif_ddr_phy_ctlr_1            = 0x00048008,
 251         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 252         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 253         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 254         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 255         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 256         .emif_rd_wr_exec_thresh         = 0x80000405,
 257         .emif_prio_class_serv_map       = 0x80000001,
 258         .emif_connect_id_serv_1_map     = 0x80000094,
 259         .emif_connect_id_serv_2_map     = 0x00000000,
 260         .emif_cos_config                = 0x000FFFFF
 261 };
 262
 263 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 264         .sdram_config                   = 0x638413b2,
 265         .sdram_config2                  = 0x00000000,
 266         .ref_ctrl                       = 0x00000c30,
 267         .sdram_tim1                     = 0xeaaad4db,
 268         .sdram_tim2                     = 0x266b7fda,
 269         .sdram_tim3                     = 0x107f8678,
 270         .read_idle_ctrl                 = 0x00050000,
 271         .zq_config                      = 0x50074be4,
 272         .temp_alert_config              = 0x0,
 273         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 274         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 275         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 276         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 277         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 278         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 279         .emif_rd_wr_lvl_rmp_win         = 0x0,
 280         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 281         .emif_rd_wr_lvl_ctl             = 0x00000000,
 282         .emif_rd_wr_exec_thresh         = 0x80000000,
 283         .emif_prio_class_serv_map       = 0x80000001,
 284         .emif_connect_id_serv_1_map     = 0x80000094,
 285         .emif_connect_id_serv_2_map     = 0x00000000,
 286         .emif_cos_config                = 0x000FFFFF
 287 };
 288
 289 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
 290         .sdram_config                   = 0x61a11b32,
 291         .sdram_config2                  = 0x00000000,
 292         .ref_ctrl                       = 0x00000c30,
 293         .sdram_tim1                     = 0xeaaad4db,
 294         .sdram_tim2                     = 0x266b7fda,
 295         .sdram_tim3                     = 0x107f8678,
 296         .read_idle_ctrl                 = 0x00050000,
 297         .zq_config                      = 0x50074be4,
 298         .temp_alert_config              = 0x00000000,
 299         .emif_ddr_phy_ctlr_1            = 0x00008009,
 300         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 301         .emif_ddr_ext_phy_ctrl_2        = 0x00000040,
 302         .emif_ddr_ext_phy_ctrl_3        = 0x0000003e,
 303         .emif_ddr_ext_phy_ctrl_4        = 0x00000051,
 304         .emif_ddr_ext_phy_ctrl_5        = 0x00000051,
 305         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 306         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 307         .emif_rd_wr_lvl_ctl             = 0x00000000,
 308         .emif_rd_wr_exec_thresh         = 0x00000405,
 309         .emif_prio_class_serv_map       = 0x00000000,
 310         .emif_connect_id_serv_1_map     = 0x00000000,
 311         .emif_connect_id_serv_2_map     = 0x00000000,
 312         .emif_cos_config                = 0x00ffffff
 313 };
 314
 315 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 316 {
 317         if (board_is_eposevm()) {
 318                 *regs = ext_phy_ctrl_const_base_lpddr2;
 319                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 320         }
 321
 322         return;
 323 }
 324
 325 const struct dpll_params *get_dpll_ddr_params(void)
 326 {
 327         int ind = get_sys_clk_index();
 328
 329         if (board_is_eposevm())
 330                 return &epos_evm_dpll_ddr[ind];
 331         else if (board_is_evm() || board_is_sk())
 332                 return &gp_evm_dpll_ddr;
 333         else if (board_is_idk())
 334                 return &idk_dpll_ddr;
 335
 336         printf(" Board '%s' not supported\n", board_ti_get_name());
 337         return NULL;
 338 }
 339
 340
 341 /*
 342  * get_opp_offset:
 343  * Returns the index for safest OPP of the device to boot.
 344  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 345  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 346  * This data is read from dev_attribute register which is e-fused.
 347  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 348  * OPP available. Lowest OPP starts with min_off. So returning the
 349  * bit with rightmost '0'.
 350  */
 351 static int get_opp_offset(int max_off, int min_off)
 352 {
 353         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 354         int opp, offset, i;
 355
 356         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 357         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 358
 359         for (i = max_off; i >= min_off; i--) {
 360                 offset = opp & (1 << i);
 361                 if (!offset)
 362                         return i;
 363         }
 364
 365         return min_off;
 366 }
 367
 368 const struct dpll_params *get_dpll_mpu_params(void)
 369 {
 370         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 371         u32 ind = get_sys_clk_index();
 372
 373         return &dpll_mpu[ind][opp];
 374 }
 375
 376 const struct dpll_params *get_dpll_core_params(void)
 377 {
 378         int ind = get_sys_clk_index();
 379
 380         return &dpll_core[ind];
 381 }
 382
 383 const struct dpll_params *get_dpll_per_params(void)
 384 {
 385         int ind = get_sys_clk_index();
 386
 387         return &dpll_per[ind];
 388 }
 389
 390 void scale_vcores_generic(u32 m)
 391 {
 392         int mpu_vdd, ddr_volt;
 393
 394         if (power_tps65218_init(0))
 395                 return;
 396
 397         switch (m) {
 398         case 1000:
 399                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 400                 break;
 401         case 800:
 402                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
 403                 break;
 404         case 720:
 405                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
 406                 break;
 407         case 600:
 408                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 409                 break;
 410         case 300:
 411                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
 412                 break;
 413         default:
 414                 puts("Unknown MPU clock, not scaling\n");
 415                 return;
 416         }
 417
 418         /* Set DCDC1 (CORE) voltage to 1.1V */
 419         if (tps65218_voltage_update(TPS65218_DCDC1,
 420                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 421                 printf("%s failure\n", __func__);
 422                 return;
 423         }
 424
 425         /* Set DCDC2 (MPU) voltage */
 426         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 427                 printf("%s failure\n", __func__);
 428                 return;
 429         }
 430
 431         if (board_is_eposevm())
 432                 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
 433         else
 434                 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
 435
 436         /* Set DCDC3 (DDR) voltage */
 437         if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
 438                 printf("%s failure\n", __func__);
 439                 return;
 440         }
 441 }
 442
 443 void scale_vcores_idk(u32 m)
 444 {
 445         int mpu_vdd;
 446
 447         if (power_tps62362_init(0))
 448                 return;
 449
 450         switch (m) {
 451         case 1000:
 452                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 453                 break;
 454         case 800:
 455                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
 456                 break;
 457         case 720:
 458                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
 459                 break;
 460         case 600:
 461                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
 462                 break;
 463         case 300:
 464                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 465                 break;
 466         default:
 467                 puts("Unknown MPU clock, not scaling\n");
 468                 return;
 469         }
 470         /* Set VDD_MPU voltage */
 471         if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
 472                 printf("%s failure\n", __func__);
 473                 return;
 474         }
 475 }
 476 void gpi2c_init(void)
 477 {
 478         /* When needed to be invoked prior to BSS initialization */
 479         static bool first_time = true;
 480
 481         if (first_time) {
 482                 enable_i2c0_pin_mux();
 483                 first_time = false;
 484         }
 485 }
 486
 487 void scale_vcores(void)
 488 {
 489         const struct dpll_params *mpu_params;
 490
 491         /* Ensure I2C is initialized for PMIC configuration */
 492         gpi2c_init();
 493
 494         /* Get the frequency */
 495         mpu_params = get_dpll_mpu_params();
 496
 497         if (board_is_idk())
 498                 scale_vcores_idk(mpu_params->m);
 499         else
 500                 scale_vcores_generic(mpu_params->m);
 501 }
 502
 503 void set_uart_mux_conf(void)
 504 {
 505         enable_uart0_pin_mux();
 506 }
 507
 508 void set_mux_conf_regs(void)
 509 {
 510         enable_board_pin_mux();
 511 }
 512
 513 static void enable_vtt_regulator(void)
 514 {
 515         u32 temp;
 516
 517         /* enable module */
 518         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 519
 520         /* enable output for GPIO5_7 */
 521         writel(GPIO_SETDATAOUT(7),
 522                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 523         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 524         temp = temp & ~(GPIO_OE_ENABLE(7));
 525         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 526 }
 527
 528 enum {
 529         RTC_BOARD_EPOS = 1,
 530         RTC_BOARD_EVM14,
 531         RTC_BOARD_EVM12,
 532         RTC_BOARD_GPEVM,
 533         RTC_BOARD_SK,
 534 };
 535
 536 /*
 537  * In the rtc_only+DRR in self-refresh boot path we have the board type info
 538  * in the rtc scratch pad register hence we bypass the costly i2c reads to
 539  * eeprom and directly programthe board name string
 540  */
 541 void rtc_only_update_board_type(u32 btype)
 542 {
 543         const char *name = "";
 544         const char *rev = "1.0";
 545
 546         switch (btype) {
 547         case RTC_BOARD_EPOS:
 548                 name = "AM43EPOS";
 549                 break;
 550         case RTC_BOARD_EVM14:
 551                 name = "AM43__GP";
 552                 rev = "1.4";
 553                 break;
 554         case RTC_BOARD_EVM12:
 555                 name = "AM43__GP";
 556                 rev = "1.2";
 557                 break;
 558         case RTC_BOARD_GPEVM:
 559                 name = "AM43__GP";
 560                 break;
 561         case RTC_BOARD_SK:
 562                 name = "AM43__SK";
 563                 break;
 564         }
 565         ti_i2c_eeprom_am_set(name, rev);
 566 }
 567
 568 u32 rtc_only_get_board_type(void)
 569 {
 570         if (board_is_eposevm())
 571                 return RTC_BOARD_EPOS;
 572         else if (board_is_evm_14_or_later())
 573                 return RTC_BOARD_EVM14;
 574         else if (board_is_evm_12_or_later())
 575                 return RTC_BOARD_EVM12;
 576         else if (board_is_gpevm())
 577                 return RTC_BOARD_GPEVM;
 578         else if (board_is_sk())
 579                 return RTC_BOARD_SK;
 580
 581         return 0;
 582 }
 583
 584 void sdram_init(void)
 585 {
 586         /*
 587          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 588          * GP EMV has 1GB DDR3 connected to EMIF
 589          * along with VTT regulator.
 590          */
 591         if (board_is_eposevm()) {
 592                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 593         } else if (board_is_evm_14_or_later()) {
 594                 enable_vtt_regulator();
 595                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 596                            &ddr3_emif_regs_400Mhz_production, 0);
 597         } else if (board_is_evm_12_or_later()) {
 598                 enable_vtt_regulator();
 599                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 600                            &ddr3_emif_regs_400Mhz_beta, 0);
 601         } else if (board_is_evm()) {
 602                 enable_vtt_regulator();
 603                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 604                            &ddr3_emif_regs_400Mhz, 0);
 605         } else if (board_is_sk()) {
 606                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 607                            &ddr3_sk_emif_regs_400Mhz, 0);
 608         } else if (board_is_idk()) {
 609                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 610                            &ddr3_idk_emif_regs_400Mhz, 0);
 611         }
 612 }
 613 #endif
 614
 615 /* setup board specific PMIC */
 616 int power_init_board(void)
 617 {
 618         int rc;
 619         if (board_is_idk()) {
 620                 rc = power_tps62362_init(0);
 621                 if (rc)
 622                         goto done;
 623                 puts("PMIC:  TPS62362\n");
 624         } else {
 625                 rc = power_tps65218_init(0);
 626                 if (rc)
 627                         goto done;
 628                 puts("PMIC:  TPS65218\n");
 629         }
 630 done:
 631         return 0;
 632 }
 633
 634 int board_init(void)
 635 {
 636         struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 637         u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 638             modena_init0_bw_integer, modena_init0_watermark_0;
 639
 640         gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 641         gpmc_init();
 642
 643         /*
 644          * Call this to initialize *ctrl again
 645          */
 646         hw_data_init();
 647
 648         /* Clear all important bits for DSS errata that may need to be tweaked*/
 649         mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 650                            MREQPRIO_0_SAB_INIT0_MASK;
 651
 652         mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 653
 654         modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 655                                            BW_LIMITER_BW_FRAC_MASK;
 656
 657         modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 658                                         BW_LIMITER_BW_INT_MASK;
 659
 660         modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 661                                          BW_LIMITER_BW_WATERMARK_MASK;
 662
 663         /* Setting MReq Priority of the DSS*/
 664         mreqprio_0 |= 0x77;
 665
 666         /*
 667          * Set L3 Fast Configuration Register
 668          * Limiting bandwith for ARM core to 700 MBPS
 669          */
 670         modena_init0_bw_fractional |= 0x10;
 671         modena_init0_bw_integer |= 0x3;
 672
 673         writel(mreqprio_0, &cdev->mreqprio_0);
 674         writel(mreqprio_1, &cdev->mreqprio_1);
 675
 676         writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 677         writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 678         writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 679
 680         return 0;
 681 }
 682
 683 #ifdef CONFIG_BOARD_LATE_INIT
 684 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 685 static int device_okay(const char *path)
 686 {
 687         int node;
 688
 689         node = fdt_path_offset(gd->fdt_blob, path);
 690         if (node < 0)
 691                 return 0;
 692
 693         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 694 }
 695 #endif
 696
 697 int board_late_init(void)
 698 {
 699         struct udevice *dev;
 700 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 701         set_board_info_env(NULL);
 702
 703         /*
 704          * Default FIT boot on HS devices. Non FIT images are not allowed
 705          * on HS devices.
 706          */
 707         if (get_device_type() == HS_DEVICE)
 708                 env_set("boot_fit", "1");
 709 #endif
 710
 711 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 712         if (device_okay("/ocp/omap_dwc3@48380000"))
 713                 enable_usb_clocks(0);
 714         if (device_okay("/ocp/omap_dwc3@483c0000"))
 715                 enable_usb_clocks(1);
 716 #endif
 717
 718         /* Just probe the potentially supported cdce913 device */
 719         uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
 720
 721         return 0;
 722 }
 723 #endif
 724
 725 #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
 726 #ifdef CONFIG_USB_DWC3
 727 static struct dwc3_device usb_otg_ss1 = {
 728         .maximum_speed = USB_SPEED_HIGH,
 729         .base = USB_OTG_SS1_BASE,
 730         .tx_fifo_resize = false,
 731         .index = 0,
 732 };
 733
 734 static struct dwc3_omap_device usb_otg_ss1_glue = {
 735         .base = (void *)USB_OTG_SS1_GLUE_BASE,
 736         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 737         .index = 0,
 738 };
 739
 740 static struct ti_usb_phy_device usb_phy1_device = {
 741         .usb2_phy_power = (void *)USB2_PHY1_POWER,
 742         .index = 0,
 743 };
 744
 745 static struct dwc3_device usb_otg_ss2 = {
 746         .maximum_speed = USB_SPEED_HIGH,
 747         .base = USB_OTG_SS2_BASE,
 748         .tx_fifo_resize = false,
 749         .index = 1,
 750 };
 751
 752 static struct dwc3_omap_device usb_otg_ss2_glue = {
 753         .base = (void *)USB_OTG_SS2_GLUE_BASE,
 754         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 755         .index = 1,
 756 };
 757
 758 static struct ti_usb_phy_device usb_phy2_device = {
 759         .usb2_phy_power = (void *)USB2_PHY2_POWER,
 760         .index = 1,
 761 };
 762
 763 int usb_gadget_handle_interrupts(int index)
 764 {
 765         u32 status;
 766
 767         status = dwc3_omap_uboot_interrupt_status(index);
 768         if (status)
 769                 dwc3_uboot_handle_interrupt(index);
 770
 771         return 0;
 772 }
 773 #endif /* CONFIG_USB_DWC3 */
 774
 775 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 776 int board_usb_init(int index, enum usb_init_type init)
 777 {
 778         enable_usb_clocks(index);
 779 #ifdef CONFIG_USB_DWC3
 780         switch (index) {
 781         case 0:
 782                 if (init == USB_INIT_DEVICE) {
 783                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 784                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 785                         dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 786                         ti_usb_phy_uboot_init(&usb_phy1_device);
 787                         dwc3_uboot_init(&usb_otg_ss1);
 788                 }
 789                 break;
 790         case 1:
 791                 if (init == USB_INIT_DEVICE) {
 792                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 793                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 794                         ti_usb_phy_uboot_init(&usb_phy2_device);
 795                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 796                         dwc3_uboot_init(&usb_otg_ss2);
 797                 }
 798                 break;
 799         default:
 800                 printf("Invalid Controller Index\n");
 801         }
 802 #endif
 803
 804         return 0;
 805 }
 806
 807 int board_usb_cleanup(int index, enum usb_init_type init)
 808 {
 809 #ifdef CONFIG_USB_DWC3
 810         switch (index) {
 811         case 0:
 812         case 1:
 813                 if (init == USB_INIT_DEVICE) {
 814                         ti_usb_phy_uboot_exit(index);
 815                         dwc3_uboot_exit(index);
 816                         dwc3_omap_uboot_exit(index);
 817                 }
 818                 break;
 819         default:
 820                 printf("Invalid Controller Index\n");
 821         }
 822 #endif
 823         disable_usb_clocks(index);
 824
 825         return 0;
 826 }
 827 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 828 #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
 829
 830 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 831 int ft_board_setup(void *blob, struct bd_info *bd)
 832 {
 833         ft_cpu_setup(blob, bd);
 834
 835         return 0;
 836 }
 837 #endif
 838
 839 #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
 840 int board_fit_config_name_match(const char *name)
 841 {
 842         bool eeprom_read = board_ti_was_eeprom_read();
 843
 844         if (!strcmp(name, "am4372-generic") && !eeprom_read)
 845                 return 0;
 846         else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
 847                 return 0;
 848         else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
 849                 return 0;
 850         else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
 851                 return 0;
 852         else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
 853                 return 0;
 854         else
 855                 return -1;
 856 }
 857 #endif
 858
 859 #ifdef CONFIG_DTB_RESELECT
 860 int embedded_dtb_select(void)
 861 {
 862         do_board_detect();
 863         fdtdec_setup();
 864
 865         return 0;
 866 }
 867 #endif