board/ti/am43xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TI AM43XX based boards
   6  *
   7  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <eeprom.h>
  12 #include <image.h>
  13 #include <asm/global_data.h>
  14 #include <dm/uclass.h>
  15 #include <env.h>
  16 #include <fdt_support.h>
  17 #include <i2c.h>
  18 #include <init.h>
  19 #include <net.h>
  20 #include <linux/errno.h>
  21 #include <spl.h>
  22 #include <usb.h>
  23 #include <asm/omap_sec_common.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/arch/mux.h>
  27 #include <asm/arch/ddr_defs.h>
  28 #include <asm/arch/gpio.h>
  29 #include <asm/emif.h>
  30 #include <asm/omap_common.h>
  31 #include "../common/board_detect.h"
  32 #include "board.h"
  33 #include <power/pmic.h>
  34 #include <power/tps65218.h>
  35 #include <power/tps62362.h>
  36 #include <linux/usb/gadget.h>
  37 #include <dwc3-uboot.h>
  38 #include <dwc3-omap-uboot.h>
  39 #include <ti-usb-phy-uboot.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  44
  45 /*
  46  * Read header information from EEPROM into global structure.
  47  */
  48 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  49 void do_board_detect(void)
  50 {
  51         /* Ensure I2C is initialized for EEPROM access*/
  52         gpi2c_init();
  53         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  54                                  CONFIG_EEPROM_CHIP_ADDRESS))
  55                 printf("ti_i2c_eeprom_init failed\n");
  56 }
  57 #endif
  58
  59 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  60
  61 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  62         {       /* 19.2 MHz */
  63                 {125, 3, 2, -1, -1, -1, -1},    /* OPP 50 */
  64                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  65                 {125, 3, 1, -1, -1, -1, -1},    /* OPP 100 */
  66                 {150, 3, 1, -1, -1, -1, -1},    /* OPP 120 */
  67                 {125, 2, 1, -1, -1, -1, -1},    /* OPP TB */
  68                 {625, 11, 1, -1, -1, -1, -1}    /* OPP NT */
  69         },
  70         {       /* 24 MHz */
  71                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  72                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  73                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  74                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  75                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  76                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  77         },
  78         {       /* 25 MHz */
  79                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
  80                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  81                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
  82                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
  83                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
  84                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
  85         },
  86         {       /* 26 MHz */
  87                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
  88                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  89                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
  90                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
  91                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
  92                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
  93         },
  94 };
  95
  96 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  97                 {625, 11, -1, -1, 10, 8, 4},    /* 19.2 MHz */
  98                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
  99                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
 100                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
 101 };
 102
 103 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
 104                 {400, 7, 5, -1, -1, -1, -1},    /* 19.2 MHz */
 105                 {400, 9, 5, -1, -1, -1, -1},    /* 24 MHz */
 106                 {384, 9, 5, -1, -1, -1, -1},    /* 25 MHz */
 107                 {480, 12, 5, -1, -1, -1, -1}    /* 26 MHz */
 108 };
 109
 110 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
 111                 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
 112                 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
 113                 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
 114                 {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
 115 };
 116
 117 const struct dpll_params gp_evm_dpll_ddr = {
 118                 50, 2, 1, -1, 2, -1, -1};
 119
 120 static const struct dpll_params idk_dpll_ddr = {
 121         400, 23, 1, -1, 2, -1, -1
 122 };
 123
 124 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 125         0x00500050,
 126         0x00350035,
 127         0x00350035,
 128         0x00350035,
 129         0x00350035,
 130         0x00350035,
 131         0x00000000,
 132         0x00000000,
 133         0x00000000,
 134         0x00000000,
 135         0x00000000,
 136         0x00000000,
 137         0x00000000,
 138         0x00000000,
 139         0x00000000,
 140         0x00000000,
 141         0x00000000,
 142         0x00000000,
 143         0x40001000,
 144         0x08102040
 145 };
 146
 147 const struct ctrl_ioregs ioregs_lpddr2 = {
 148         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 149         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 150         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 151         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 152         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 153         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 154         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 155         .emif_sdram_config_ext  = 0x1,
 156 };
 157
 158 const struct emif_regs emif_regs_lpddr2 = {
 159         .sdram_config                   = 0x808012BA,
 160         .ref_ctrl                       = 0x0000040D,
 161         .sdram_tim1                     = 0xEA86B411,
 162         .sdram_tim2                     = 0x103A094A,
 163         .sdram_tim3                     = 0x0F6BA37F,
 164         .read_idle_ctrl                 = 0x00050000,
 165         .zq_config                      = 0x50074BE4,
 166         .temp_alert_config              = 0x0,
 167         .emif_rd_wr_lvl_rmp_win         = 0x0,
 168         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 169         .emif_rd_wr_lvl_ctl             = 0x0,
 170         .emif_ddr_phy_ctlr_1            = 0x0E284006,
 171         .emif_rd_wr_exec_thresh         = 0x80000405,
 172         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 173         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 174         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 175         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 176         .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
 177         .emif_prio_class_serv_map       = 0x80000001,
 178         .emif_connect_id_serv_1_map     = 0x80000094,
 179         .emif_connect_id_serv_2_map     = 0x00000000,
 180         .emif_cos_config                        = 0x000FFFFF
 181 };
 182
 183 const struct ctrl_ioregs ioregs_ddr3 = {
 184         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 185         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 186         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 187         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 188         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 189         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 190         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 191         .emif_sdram_config_ext  = 0xc163,
 192 };
 193
 194 const struct emif_regs ddr3_emif_regs_400Mhz = {
 195         .sdram_config                   = 0x638413B2,
 196         .ref_ctrl                       = 0x00000C30,
 197         .sdram_tim1                     = 0xEAAAD4DB,
 198         .sdram_tim2                     = 0x266B7FDA,
 199         .sdram_tim3                     = 0x107F8678,
 200         .read_idle_ctrl                 = 0x00050000,
 201         .zq_config                      = 0x50074BE4,
 202         .temp_alert_config              = 0x0,
 203         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 204         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 205         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 206         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 207         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 208         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 209         .emif_rd_wr_lvl_rmp_win         = 0x0,
 210         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 211         .emif_rd_wr_lvl_ctl             = 0x0,
 212         .emif_rd_wr_exec_thresh         = 0x80000405,
 213         .emif_prio_class_serv_map       = 0x80000001,
 214         .emif_connect_id_serv_1_map     = 0x80000094,
 215         .emif_connect_id_serv_2_map     = 0x00000000,
 216         .emif_cos_config                = 0x000FFFFF
 217 };
 218
 219 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 220 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 221         .sdram_config                   = 0x638413B2,
 222         .ref_ctrl                       = 0x00000C30,
 223         .sdram_tim1                     = 0xEAAAD4DB,
 224         .sdram_tim2                     = 0x266B7FDA,
 225         .sdram_tim3                     = 0x107F8678,
 226         .read_idle_ctrl                 = 0x00050000,
 227         .zq_config                      = 0x50074BE4,
 228         .temp_alert_config              = 0x0,
 229         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 230         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 231         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 232         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 233         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 234         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 235         .emif_rd_wr_exec_thresh         = 0x80000405,
 236         .emif_prio_class_serv_map       = 0x80000001,
 237         .emif_connect_id_serv_1_map     = 0x80000094,
 238         .emif_connect_id_serv_2_map     = 0x00000000,
 239         .emif_cos_config                = 0x000FFFFF
 240 };
 241
 242 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 243 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 244         .sdram_config                   = 0x638413B2,
 245         .ref_ctrl                       = 0x00000C30,
 246         .sdram_tim1                     = 0xEAAAD4DB,
 247         .sdram_tim2                     = 0x266B7FDA,
 248         .sdram_tim3                     = 0x107F8678,
 249         .read_idle_ctrl                 = 0x00050000,
 250         .zq_config                      = 0x50074BE4,
 251         .temp_alert_config              = 0x0,
 252         .emif_ddr_phy_ctlr_1            = 0x00048008,
 253         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 254         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 255         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 256         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 257         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 258         .emif_rd_wr_exec_thresh         = 0x80000405,
 259         .emif_prio_class_serv_map       = 0x80000001,
 260         .emif_connect_id_serv_1_map     = 0x80000094,
 261         .emif_connect_id_serv_2_map     = 0x00000000,
 262         .emif_cos_config                = 0x000FFFFF
 263 };
 264
 265 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 266         .sdram_config                   = 0x638413b2,
 267         .sdram_config2                  = 0x00000000,
 268         .ref_ctrl                       = 0x00000c30,
 269         .sdram_tim1                     = 0xeaaad4db,
 270         .sdram_tim2                     = 0x266b7fda,
 271         .sdram_tim3                     = 0x107f8678,
 272         .read_idle_ctrl                 = 0x00050000,
 273         .zq_config                      = 0x50074be4,
 274         .temp_alert_config              = 0x0,
 275         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 276         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 277         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 278         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 279         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 280         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 281         .emif_rd_wr_lvl_rmp_win         = 0x0,
 282         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 283         .emif_rd_wr_lvl_ctl             = 0x00000000,
 284         .emif_rd_wr_exec_thresh         = 0x80000000,
 285         .emif_prio_class_serv_map       = 0x80000001,
 286         .emif_connect_id_serv_1_map     = 0x80000094,
 287         .emif_connect_id_serv_2_map     = 0x00000000,
 288         .emif_cos_config                = 0x000FFFFF
 289 };
 290
 291 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
 292         .sdram_config                   = 0x61a11b32,
 293         .sdram_config2                  = 0x00000000,
 294         .ref_ctrl                       = 0x00000c30,
 295         .sdram_tim1                     = 0xeaaad4db,
 296         .sdram_tim2                     = 0x266b7fda,
 297         .sdram_tim3                     = 0x107f8678,
 298         .read_idle_ctrl                 = 0x00050000,
 299         .zq_config                      = 0x50074be4,
 300         .temp_alert_config              = 0x00000000,
 301         .emif_ddr_phy_ctlr_1            = 0x00008009,
 302         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 303         .emif_ddr_ext_phy_ctrl_2        = 0x00000040,
 304         .emif_ddr_ext_phy_ctrl_3        = 0x0000003e,
 305         .emif_ddr_ext_phy_ctrl_4        = 0x00000051,
 306         .emif_ddr_ext_phy_ctrl_5        = 0x00000051,
 307         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 308         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 309         .emif_rd_wr_lvl_ctl             = 0x00000000,
 310         .emif_rd_wr_exec_thresh         = 0x00000405,
 311         .emif_prio_class_serv_map       = 0x00000000,
 312         .emif_connect_id_serv_1_map     = 0x00000000,
 313         .emif_connect_id_serv_2_map     = 0x00000000,
 314         .emif_cos_config                = 0x00ffffff
 315 };
 316
 317 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 318 {
 319         if (board_is_eposevm()) {
 320                 *regs = ext_phy_ctrl_const_base_lpddr2;
 321                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 322         }
 323
 324         return;
 325 }
 326
 327 const struct dpll_params *get_dpll_ddr_params(void)
 328 {
 329         int ind = get_sys_clk_index();
 330
 331         if (board_is_eposevm())
 332                 return &epos_evm_dpll_ddr[ind];
 333         else if (board_is_evm() || board_is_sk())
 334                 return &gp_evm_dpll_ddr;
 335         else if (board_is_idk())
 336                 return &idk_dpll_ddr;
 337
 338         printf(" Board '%s' not supported\n", board_ti_get_name());
 339         return NULL;
 340 }
 341
 342
 343 /*
 344  * get_opp_offset:
 345  * Returns the index for safest OPP of the device to boot.
 346  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 347  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 348  * This data is read from dev_attribute register which is e-fused.
 349  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 350  * OPP available. Lowest OPP starts with min_off. So returning the
 351  * bit with rightmost '0'.
 352  */
 353 static int get_opp_offset(int max_off, int min_off)
 354 {
 355         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 356         int opp, offset, i;
 357
 358         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 359         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 360
 361         for (i = max_off; i >= min_off; i--) {
 362                 offset = opp & (1 << i);
 363                 if (!offset)
 364                         return i;
 365         }
 366
 367         return min_off;
 368 }
 369
 370 const struct dpll_params *get_dpll_mpu_params(void)
 371 {
 372         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 373         u32 ind = get_sys_clk_index();
 374
 375         return &dpll_mpu[ind][opp];
 376 }
 377
 378 const struct dpll_params *get_dpll_core_params(void)
 379 {
 380         int ind = get_sys_clk_index();
 381
 382         return &dpll_core[ind];
 383 }
 384
 385 const struct dpll_params *get_dpll_per_params(void)
 386 {
 387         int ind = get_sys_clk_index();
 388
 389         return &dpll_per[ind];
 390 }
 391
 392 void scale_vcores_generic(u32 m)
 393 {
 394         int mpu_vdd, ddr_volt;
 395
 396         if (power_tps65218_init(0))
 397                 return;
 398
 399         switch (m) {
 400         case 1000:
 401                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 402                 break;
 403         case 800:
 404                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
 405                 break;
 406         case 720:
 407                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
 408                 break;
 409         case 600:
 410                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 411                 break;
 412         case 300:
 413                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
 414                 break;
 415         default:
 416                 puts("Unknown MPU clock, not scaling\n");
 417                 return;
 418         }
 419
 420         /* Set DCDC1 (CORE) voltage to 1.1V */
 421         if (tps65218_voltage_update(TPS65218_DCDC1,
 422                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 423                 printf("%s failure\n", __func__);
 424                 return;
 425         }
 426
 427         /* Set DCDC2 (MPU) voltage */
 428         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 429                 printf("%s failure\n", __func__);
 430                 return;
 431         }
 432
 433         if (board_is_eposevm())
 434                 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
 435         else
 436                 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
 437
 438         /* Set DCDC3 (DDR) voltage */
 439         if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
 440                 printf("%s failure\n", __func__);
 441                 return;
 442         }
 443 }
 444
 445 void scale_vcores_idk(u32 m)
 446 {
 447         int mpu_vdd;
 448
 449         if (power_tps62362_init(0))
 450                 return;
 451
 452         switch (m) {
 453         case 1000:
 454                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 455                 break;
 456         case 800:
 457                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
 458                 break;
 459         case 720:
 460                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
 461                 break;
 462         case 600:
 463                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
 464                 break;
 465         case 300:
 466                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 467                 break;
 468         default:
 469                 puts("Unknown MPU clock, not scaling\n");
 470                 return;
 471         }
 472         /* Set VDD_MPU voltage */
 473         if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
 474                 printf("%s failure\n", __func__);
 475                 return;
 476         }
 477 }
 478 void gpi2c_init(void)
 479 {
 480         /* When needed to be invoked prior to BSS initialization */
 481         static bool first_time = true;
 482
 483         if (first_time) {
 484                 enable_i2c0_pin_mux();
 485                 first_time = false;
 486         }
 487 }
 488
 489 void scale_vcores(void)
 490 {
 491         const struct dpll_params *mpu_params;
 492
 493         /* Ensure I2C is initialized for PMIC configuration */
 494         gpi2c_init();
 495
 496         /* Get the frequency */
 497         mpu_params = get_dpll_mpu_params();
 498
 499         if (board_is_idk())
 500                 scale_vcores_idk(mpu_params->m);
 501         else
 502                 scale_vcores_generic(mpu_params->m);
 503 }
 504
 505 void set_uart_mux_conf(void)
 506 {
 507         enable_uart0_pin_mux();
 508 }
 509
 510 void set_mux_conf_regs(void)
 511 {
 512         enable_board_pin_mux();
 513 }
 514
 515 static void enable_vtt_regulator(void)
 516 {
 517         u32 temp;
 518
 519         /* enable module */
 520         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 521
 522         /* enable output for GPIO5_7 */
 523         writel(GPIO_SETDATAOUT(7),
 524                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 525         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 526         temp = temp & ~(GPIO_OE_ENABLE(7));
 527         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 528 }
 529
 530 enum {
 531         RTC_BOARD_EPOS = 1,
 532         RTC_BOARD_EVM14,
 533         RTC_BOARD_EVM12,
 534         RTC_BOARD_GPEVM,
 535         RTC_BOARD_SK,
 536 };
 537
 538 /*
 539  * In the rtc_only+DRR in self-refresh boot path we have the board type info
 540  * in the rtc scratch pad register hence we bypass the costly i2c reads to
 541  * eeprom and directly programthe board name string
 542  */
 543 void rtc_only_update_board_type(u32 btype)
 544 {
 545         const char *name = "";
 546         const char *rev = "1.0";
 547
 548         switch (btype) {
 549         case RTC_BOARD_EPOS:
 550                 name = "AM43EPOS";
 551                 break;
 552         case RTC_BOARD_EVM14:
 553                 name = "AM43__GP";
 554                 rev = "1.4";
 555                 break;
 556         case RTC_BOARD_EVM12:
 557                 name = "AM43__GP";
 558                 rev = "1.2";
 559                 break;
 560         case RTC_BOARD_GPEVM:
 561                 name = "AM43__GP";
 562                 break;
 563         case RTC_BOARD_SK:
 564                 name = "AM43__SK";
 565                 break;
 566         }
 567         ti_i2c_eeprom_am_set(name, rev);
 568 }
 569
 570 u32 rtc_only_get_board_type(void)
 571 {
 572         if (board_is_eposevm())
 573                 return RTC_BOARD_EPOS;
 574         else if (board_is_evm_14_or_later())
 575                 return RTC_BOARD_EVM14;
 576         else if (board_is_evm_12_or_later())
 577                 return RTC_BOARD_EVM12;
 578         else if (board_is_gpevm())
 579                 return RTC_BOARD_GPEVM;
 580         else if (board_is_sk())
 581                 return RTC_BOARD_SK;
 582
 583         return 0;
 584 }
 585
 586 void sdram_init(void)
 587 {
 588         /*
 589          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 590          * GP EMV has 1GB DDR3 connected to EMIF
 591          * along with VTT regulator.
 592          */
 593         if (board_is_eposevm()) {
 594                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 595         } else if (board_is_evm_14_or_later()) {
 596                 enable_vtt_regulator();
 597                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 598                            &ddr3_emif_regs_400Mhz_production, 0);
 599         } else if (board_is_evm_12_or_later()) {
 600                 enable_vtt_regulator();
 601                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 602                            &ddr3_emif_regs_400Mhz_beta, 0);
 603         } else if (board_is_evm()) {
 604                 enable_vtt_regulator();
 605                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 606                            &ddr3_emif_regs_400Mhz, 0);
 607         } else if (board_is_sk()) {
 608                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 609                            &ddr3_sk_emif_regs_400Mhz, 0);
 610         } else if (board_is_idk()) {
 611                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 612                            &ddr3_idk_emif_regs_400Mhz, 0);
 613         }
 614 }
 615 #endif
 616
 617 /* setup board specific PMIC */
 618 int power_init_board(void)
 619 {
 620         int rc;
 621         if (board_is_idk()) {
 622                 rc = power_tps62362_init(0);
 623                 if (rc)
 624                         goto done;
 625                 puts("PMIC:  TPS62362\n");
 626         } else {
 627                 rc = power_tps65218_init(0);
 628                 if (rc)
 629                         goto done;
 630                 puts("PMIC:  TPS65218\n");
 631         }
 632 done:
 633         return 0;
 634 }
 635
 636 int board_init(void)
 637 {
 638         struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 639         u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 640             modena_init0_bw_integer, modena_init0_watermark_0;
 641
 642         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 643         gpmc_init();
 644
 645         /*
 646          * Call this to initialize *ctrl again
 647          */
 648         hw_data_init();
 649
 650         /* Clear all important bits for DSS errata that may need to be tweaked*/
 651         mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 652                            MREQPRIO_0_SAB_INIT0_MASK;
 653
 654         mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 655
 656         modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 657                                            BW_LIMITER_BW_FRAC_MASK;
 658
 659         modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 660                                         BW_LIMITER_BW_INT_MASK;
 661
 662         modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 663                                          BW_LIMITER_BW_WATERMARK_MASK;
 664
 665         /* Setting MReq Priority of the DSS*/
 666         mreqprio_0 |= 0x77;
 667
 668         /*
 669          * Set L3 Fast Configuration Register
 670          * Limiting bandwith for ARM core to 700 MBPS
 671          */
 672         modena_init0_bw_fractional |= 0x10;
 673         modena_init0_bw_integer |= 0x3;
 674
 675         writel(mreqprio_0, &cdev->mreqprio_0);
 676         writel(mreqprio_1, &cdev->mreqprio_1);
 677
 678         writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 679         writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 680         writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 681
 682         return 0;
 683 }
 684
 685 #ifdef CONFIG_BOARD_LATE_INIT
 686 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 687 static int device_okay(const char *path)
 688 {
 689         int node;
 690
 691         node = fdt_path_offset(gd->fdt_blob, path);
 692         if (node < 0)
 693                 return 0;
 694
 695         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 696 }
 697 #endif
 698
 699 int board_late_init(void)
 700 {
 701         struct udevice *dev;
 702 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 703         set_board_info_env(NULL);
 704
 705         /*
 706          * Default FIT boot on HS devices. Non FIT images are not allowed
 707          * on HS devices.
 708          */
 709         if (get_device_type() == HS_DEVICE)
 710                 env_set("boot_fit", "1");
 711 #endif
 712
 713 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 714         if (device_okay("/ocp/omap_dwc3@48380000"))
 715                 enable_usb_clocks(0);
 716         if (device_okay("/ocp/omap_dwc3@483c0000"))
 717                 enable_usb_clocks(1);
 718 #endif
 719
 720         /* Just probe the potentially supported cdce913 device */
 721         uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
 722
 723         return 0;
 724 }
 725 #endif
 726
 727 #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
 728 #ifdef CONFIG_USB_DWC3
 729 static struct dwc3_device usb_otg_ss1 = {
 730         .maximum_speed = USB_SPEED_HIGH,
 731         .base = USB_OTG_SS1_BASE,
 732         .tx_fifo_resize = false,
 733         .index = 0,
 734 };
 735
 736 static struct dwc3_omap_device usb_otg_ss1_glue = {
 737         .base = (void *)USB_OTG_SS1_GLUE_BASE,
 738         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 739         .index = 0,
 740 };
 741
 742 static struct ti_usb_phy_device usb_phy1_device = {
 743         .usb2_phy_power = (void *)USB2_PHY1_POWER,
 744         .index = 0,
 745 };
 746
 747 static struct dwc3_device usb_otg_ss2 = {
 748         .maximum_speed = USB_SPEED_HIGH,
 749         .base = USB_OTG_SS2_BASE,
 750         .tx_fifo_resize = false,
 751         .index = 1,
 752 };
 753
 754 static struct dwc3_omap_device usb_otg_ss2_glue = {
 755         .base = (void *)USB_OTG_SS2_GLUE_BASE,
 756         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 757         .index = 1,
 758 };
 759
 760 static struct ti_usb_phy_device usb_phy2_device = {
 761         .usb2_phy_power = (void *)USB2_PHY2_POWER,
 762         .index = 1,
 763 };
 764
 765 int usb_gadget_handle_interrupts(int index)
 766 {
 767         u32 status;
 768
 769         status = dwc3_omap_uboot_interrupt_status(index);
 770         if (status)
 771                 dwc3_uboot_handle_interrupt(index);
 772
 773         return 0;
 774 }
 775 #endif /* CONFIG_USB_DWC3 */
 776
 777 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 778 int board_usb_init(int index, enum usb_init_type init)
 779 {
 780         enable_usb_clocks(index);
 781 #ifdef CONFIG_USB_DWC3
 782         switch (index) {
 783         case 0:
 784                 if (init == USB_INIT_DEVICE) {
 785                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 786                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 787                         dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 788                         ti_usb_phy_uboot_init(&usb_phy1_device);
 789                         dwc3_uboot_init(&usb_otg_ss1);
 790                 }
 791                 break;
 792         case 1:
 793                 if (init == USB_INIT_DEVICE) {
 794                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 795                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 796                         ti_usb_phy_uboot_init(&usb_phy2_device);
 797                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 798                         dwc3_uboot_init(&usb_otg_ss2);
 799                 }
 800                 break;
 801         default:
 802                 printf("Invalid Controller Index\n");
 803         }
 804 #endif
 805
 806         return 0;
 807 }
 808
 809 int board_usb_cleanup(int index, enum usb_init_type init)
 810 {
 811 #ifdef CONFIG_USB_DWC3
 812         switch (index) {
 813         case 0:
 814         case 1:
 815                 if (init == USB_INIT_DEVICE) {
 816                         ti_usb_phy_uboot_exit(index);
 817                         dwc3_uboot_exit(index);
 818                         dwc3_omap_uboot_exit(index);
 819                 }
 820                 break;
 821         default:
 822                 printf("Invalid Controller Index\n");
 823         }
 824 #endif
 825         disable_usb_clocks(index);
 826
 827         return 0;
 828 }
 829 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 830 #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
 831
 832 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 833 int ft_board_setup(void *blob, struct bd_info *bd)
 834 {
 835         ft_cpu_setup(blob, bd);
 836
 837         return 0;
 838 }
 839 #endif
 840
 841 #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
 842 int board_fit_config_name_match(const char *name)
 843 {
 844         bool eeprom_read = board_ti_was_eeprom_read();
 845
 846         if (!strcmp(name, "am4372-generic") && !eeprom_read)
 847                 return 0;
 848         else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
 849                 return 0;
 850         else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
 851                 return 0;
 852         else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
 853                 return 0;
 854         else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
 855                 return 0;
 856         else
 857                 return -1;
 858 }
 859 #endif
 860
 861 #ifdef CONFIG_DTB_RESELECT
 862 int embedded_dtb_select(void)
 863 {
 864         do_board_detect();
 865         fdtdec_setup();
 866
 867         return 0;
 868 }
 869 #endif
 870
 871 #ifdef CONFIG_TI_SECURE_DEVICE
 872 void board_fit_image_post_process(const void *fit, int node, void **p_image,
 873                                   size_t *p_size)
 874 {
 875         secure_boot_verify_image(p_image, p_size);
 876 }
 877
 878 void board_tee_image_process(ulong tee_image, size_t tee_size)
 879 {
 880         secure_tee_install((u32)tee_image);
 881 }
 882
 883 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 884 #endif