4 * Board functions for TI AM43XX based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/mux.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/gpio.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
30 * Read header information from EEPROM into global structure.
32 static int read_eeprom(struct am43xx_board_id *header)
34 /* Check if baseboard eeprom is available */
35 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
36 printf("Could not probe the EEPROM at 0x%x\n",
37 CONFIG_SYS_I2C_EEPROM_ADDR);
41 /* read the eeprom using i2c */
42 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
43 sizeof(struct am43xx_board_id))) {
44 printf("Could not read the EEPROM\n");
48 if (header->magic != 0xEE3355AA) {
50 * read the eeprom using i2c again,
51 * but use only a 1 byte address
53 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
54 sizeof(struct am43xx_board_id))) {
55 printf("Could not read the EEPROM at 0x%x\n",
56 CONFIG_SYS_I2C_EEPROM_ADDR);
60 if (header->magic != 0xEE3355AA) {
61 printf("Incorrect magic number (0x%x) in EEPROM\n",
67 strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
68 am43xx_board_name[sizeof(header->name)] = 0;
73 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
77 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
79 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */
80 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
81 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */
82 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */
83 {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */
84 {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */
87 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
88 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
89 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
90 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
91 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
92 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
95 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
96 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
97 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
98 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
99 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
100 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
103 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
104 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
105 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
106 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
107 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
108 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
112 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
113 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
114 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
115 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
116 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
119 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
120 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
121 {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */
122 {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */
123 {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */
126 const struct dpll_params epos_evm_dpll_ddr = {
127 266, 24, 1, -1, 1, -1, -1};
129 const struct dpll_params gp_evm_dpll_ddr = {
130 400, 23, 1, -1, 1, -1, -1};
132 const struct ctrl_ioregs ioregs_lpddr2 = {
133 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
134 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
135 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
136 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
137 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
138 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
139 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
140 .emif_sdram_config_ext = 0x1,
143 const struct emif_regs emif_regs_lpddr2 = {
144 .sdram_config = 0x808012BA,
145 .ref_ctrl = 0x0000040D,
146 .sdram_tim1 = 0xEA86B411,
147 .sdram_tim2 = 0x103A094A,
148 .sdram_tim3 = 0x0F6BA37F,
149 .read_idle_ctrl = 0x00050000,
150 .zq_config = 0x50074BE4,
151 .temp_alert_config = 0x0,
152 .emif_rd_wr_lvl_rmp_win = 0x0,
153 .emif_rd_wr_lvl_rmp_ctl = 0x0,
154 .emif_rd_wr_lvl_ctl = 0x0,
155 .emif_ddr_phy_ctlr_1 = 0x0E084006,
156 .emif_rd_wr_exec_thresh = 0x00000405,
157 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
158 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
159 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
160 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
161 .emif_ddr_ext_phy_ctrl_5 = 0x00500050
164 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
187 const struct ctrl_ioregs ioregs_ddr3 = {
188 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
189 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
190 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
191 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
192 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
193 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
194 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
195 .emif_sdram_config_ext = 0x0143,
198 const struct emif_regs ddr3_emif_regs_400Mhz = {
199 .sdram_config = 0x638413B2,
200 .ref_ctrl = 0x00000C30,
201 .sdram_tim1 = 0xEAAAD4DB,
202 .sdram_tim2 = 0x266B7FDA,
203 .sdram_tim3 = 0x107F8678,
204 .read_idle_ctrl = 0x00050000,
205 .zq_config = 0x50074BE4,
206 .temp_alert_config = 0x0,
207 .emif_ddr_phy_ctlr_1 = 0x0E004008,
208 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
209 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
210 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
211 .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
212 .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
213 .emif_rd_wr_lvl_rmp_win = 0x0,
214 .emif_rd_wr_lvl_rmp_ctl = 0x0,
215 .emif_rd_wr_lvl_ctl = 0x0,
216 .emif_rd_wr_exec_thresh = 0x00000405
219 const u32 ext_phy_ctrl_const_base_ddr3[] = {
242 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
244 if (board_is_eposevm()) {
245 *regs = ext_phy_ctrl_const_base_lpddr2;
246 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
247 } else if (board_is_gpevm()) {
248 *regs = ext_phy_ctrl_const_base_ddr3;
249 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
255 const struct dpll_params *get_dpll_ddr_params(void)
257 struct am43xx_board_id header;
259 enable_i2c0_pin_mux();
260 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
261 if (read_eeprom(&header) < 0)
262 puts("Could not get board ID.\n");
264 if (board_is_eposevm())
265 return &epos_evm_dpll_ddr;
266 else if (board_is_gpevm())
267 return &gp_evm_dpll_ddr;
269 puts(" Board not supported\n");
274 * get_sys_clk_index : returns the index of the sys_clk read from
275 * ctrl status register. This value is either
276 * read from efuse or sysboot pins.
278 static u32 get_sys_clk_index(void)
280 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
281 u32 ind = readl(&ctrl->statusreg), src;
283 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
284 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
285 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
286 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
287 else /* Value read from SYS BOOT pins */
288 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
289 CTRL_SYSBOOT_15_14_SHIFT);
294 * Returns the index for safest OPP of the device to boot.
295 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
296 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
297 * This data is read from dev_attribute register which is e-fused.
298 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
299 * OPP available. Lowest OPP starts with min_off. So returning the
300 * bit with rightmost '0'.
302 static int get_opp_offset(int max_off, int min_off)
304 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
307 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
308 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
310 for (i = max_off; i >= min_off; i--) {
311 offset = opp & (1 << i);
319 const struct dpll_params *get_dpll_mpu_params(void)
321 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
322 u32 ind = get_sys_clk_index();
324 return &dpll_mpu[ind][opp];
327 const struct dpll_params *get_dpll_core_params(void)
329 int ind = get_sys_clk_index();
331 return &dpll_core[ind];
334 const struct dpll_params *get_dpll_per_params(void)
336 int ind = get_sys_clk_index();
338 return &dpll_per[ind];
341 void set_uart_mux_conf(void)
343 enable_uart0_pin_mux();
346 void set_mux_conf_regs(void)
348 enable_board_pin_mux();
351 static void enable_vtt_regulator(void)
356 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
358 /* enable output for GPIO5_7 */
359 writel(GPIO_SETDATAOUT(7),
360 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
361 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
362 temp = temp & ~(GPIO_OE_ENABLE(7));
363 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
366 void sdram_init(void)
369 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
370 * GP EMV has 1GB DDR3 connected to EMIF
371 * along with VTT regulator.
373 if (board_is_eposevm()) {
374 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
375 } else if (board_is_gpevm()) {
376 enable_vtt_regulator();
377 config_ddr(0, &ioregs_ddr3, NULL, NULL,
378 &ddr3_emif_regs_400Mhz, 0);
385 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
390 #ifdef CONFIG_BOARD_LATE_INIT
391 int board_late_init(void)
393 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
394 char safe_string[HDR_NAME_LEN + 1];
395 struct am43xx_board_id header;
397 if (read_eeprom(&header) < 0)
398 puts("Could not get board ID.\n");
400 /* Now set variables based on the header. */
401 strncpy(safe_string, (char *)header.name, sizeof(header.name));
402 safe_string[sizeof(header.name)] = 0;
403 setenv("board_name", safe_string);
405 strncpy(safe_string, (char *)header.version, sizeof(header.version));
406 safe_string[sizeof(header.version)] = 0;
407 setenv("board_rev", safe_string);
413 #ifdef CONFIG_DRIVER_TI_CPSW
415 static void cpsw_control(int enabled)
417 /* Additional controls can be added here */
421 static struct cpsw_slave_data cpsw_slaves[] = {
423 .slave_reg_ofs = 0x208,
424 .sliver_reg_ofs = 0xd80,
428 .slave_reg_ofs = 0x308,
429 .sliver_reg_ofs = 0xdc0,
434 static struct cpsw_platform_data cpsw_data = {
435 .mdio_base = CPSW_MDIO_BASE,
436 .cpsw_base = CPSW_BASE,
439 .cpdma_reg_ofs = 0x800,
441 .slave_data = cpsw_slaves,
442 .ale_reg_ofs = 0xd00,
444 .host_port_reg_ofs = 0x108,
445 .hw_stats_reg_ofs = 0x900,
446 .bd_ram_ofs = 0x2000,
447 .mac_control = (1 << 5),
448 .control = cpsw_control,
450 .version = CPSW_CTRL_VERSION_2,
453 int board_eth_init(bd_t *bis)
457 uint32_t mac_hi, mac_lo;
459 /* try reading mac address from efuse */
460 mac_lo = readl(&cdev->macid0l);
461 mac_hi = readl(&cdev->macid0h);
462 mac_addr[0] = mac_hi & 0xFF;
463 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
464 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
465 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
466 mac_addr[4] = mac_lo & 0xFF;
467 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
469 if (!getenv("ethaddr")) {
470 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
471 if (is_valid_ether_addr(mac_addr))
472 eth_setenv_enetaddr("ethaddr", mac_addr);
475 mac_lo = readl(&cdev->macid1l);
476 mac_hi = readl(&cdev->macid1h);
477 mac_addr[0] = mac_hi & 0xFF;
478 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
479 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
480 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
481 mac_addr[4] = mac_lo & 0xFF;
482 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
484 if (!getenv("eth1addr")) {
485 if (is_valid_ether_addr(mac_addr))
486 eth_setenv_enetaddr("eth1addr", mac_addr);
489 if (board_is_eposevm()) {
490 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
491 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
492 cpsw_slaves[0].phy_addr = 16;
494 writel(RGMII_MODE_ENABLE, &cdev->miisel);
495 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
496 cpsw_slaves[0].phy_addr = 0;
499 rv = cpsw_register(&cpsw_data);
501 printf("Error %d registering CPSW switch\n", rv);