board/ti/am43xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TI AM43XX based boards
   6  *
   7  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <eeprom.h>
  12 #include <image.h>
  13 #include <dm/uclass.h>
  14 #include <env.h>
  15 #include <fdt_support.h>
  16 #include <i2c.h>
  17 #include <init.h>
  18 #include <net.h>
  19 #include <linux/errno.h>
  20 #include <spl.h>
  21 #include <usb.h>
  22 #include <asm/omap_sec_common.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/arch/mux.h>
  26 #include <asm/arch/ddr_defs.h>
  27 #include <asm/arch/gpio.h>
  28 #include <asm/emif.h>
  29 #include <asm/omap_common.h>
  30 #include "../common/board_detect.h"
  31 #include "board.h"
  32 #include <power/pmic.h>
  33 #include <power/tps65218.h>
  34 #include <power/tps62362.h>
  35 #include <linux/usb/gadget.h>
  36 #include <dwc3-uboot.h>
  37 #include <dwc3-omap-uboot.h>
  38 #include <ti-usb-phy-uboot.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  43
  44 /*
  45  * Read header information from EEPROM into global structure.
  46  */
  47 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  48 void do_board_detect(void)
  49 {
  50         /* Ensure I2C is initialized for EEPROM access*/
  51         gpi2c_init();
  52         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  53                                  CONFIG_EEPROM_CHIP_ADDRESS))
  54                 printf("ti_i2c_eeprom_init failed\n");
  55 }
  56 #endif
  57
  58 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  59
  60 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  61         {       /* 19.2 MHz */
  62                 {125, 3, 2, -1, -1, -1, -1},    /* OPP 50 */
  63                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  64                 {125, 3, 1, -1, -1, -1, -1},    /* OPP 100 */
  65                 {150, 3, 1, -1, -1, -1, -1},    /* OPP 120 */
  66                 {125, 2, 1, -1, -1, -1, -1},    /* OPP TB */
  67                 {625, 11, 1, -1, -1, -1, -1}    /* OPP NT */
  68         },
  69         {       /* 24 MHz */
  70                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  71                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  72                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  73                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  74                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  75                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  76         },
  77         {       /* 25 MHz */
  78                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
  79                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  80                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
  81                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
  82                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
  83                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
  84         },
  85         {       /* 26 MHz */
  86                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
  87                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  88                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
  89                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
  90                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
  91                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
  92         },
  93 };
  94
  95 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  96                 {625, 11, -1, -1, 10, 8, 4},    /* 19.2 MHz */
  97                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
  98                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
  99                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
 100 };
 101
 102 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
 103                 {400, 7, 5, -1, -1, -1, -1},    /* 19.2 MHz */
 104                 {400, 9, 5, -1, -1, -1, -1},    /* 24 MHz */
 105                 {384, 9, 5, -1, -1, -1, -1},    /* 25 MHz */
 106                 {480, 12, 5, -1, -1, -1, -1}    /* 26 MHz */
 107 };
 108
 109 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
 110                 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
 111                 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
 112                 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
 113                 {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
 114 };
 115
 116 const struct dpll_params gp_evm_dpll_ddr = {
 117                 50, 2, 1, -1, 2, -1, -1};
 118
 119 static const struct dpll_params idk_dpll_ddr = {
 120         400, 23, 1, -1, 2, -1, -1
 121 };
 122
 123 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 124         0x00500050,
 125         0x00350035,
 126         0x00350035,
 127         0x00350035,
 128         0x00350035,
 129         0x00350035,
 130         0x00000000,
 131         0x00000000,
 132         0x00000000,
 133         0x00000000,
 134         0x00000000,
 135         0x00000000,
 136         0x00000000,
 137         0x00000000,
 138         0x00000000,
 139         0x00000000,
 140         0x00000000,
 141         0x00000000,
 142         0x40001000,
 143         0x08102040
 144 };
 145
 146 const struct ctrl_ioregs ioregs_lpddr2 = {
 147         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 148         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 149         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 150         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 151         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 152         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 153         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 154         .emif_sdram_config_ext  = 0x1,
 155 };
 156
 157 const struct emif_regs emif_regs_lpddr2 = {
 158         .sdram_config                   = 0x808012BA,
 159         .ref_ctrl                       = 0x0000040D,
 160         .sdram_tim1                     = 0xEA86B411,
 161         .sdram_tim2                     = 0x103A094A,
 162         .sdram_tim3                     = 0x0F6BA37F,
 163         .read_idle_ctrl                 = 0x00050000,
 164         .zq_config                      = 0x50074BE4,
 165         .temp_alert_config              = 0x0,
 166         .emif_rd_wr_lvl_rmp_win         = 0x0,
 167         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 168         .emif_rd_wr_lvl_ctl             = 0x0,
 169         .emif_ddr_phy_ctlr_1            = 0x0E284006,
 170         .emif_rd_wr_exec_thresh         = 0x80000405,
 171         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 172         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 173         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 174         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 175         .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
 176         .emif_prio_class_serv_map       = 0x80000001,
 177         .emif_connect_id_serv_1_map     = 0x80000094,
 178         .emif_connect_id_serv_2_map     = 0x00000000,
 179         .emif_cos_config                        = 0x000FFFFF
 180 };
 181
 182 const struct ctrl_ioregs ioregs_ddr3 = {
 183         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 184         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 185         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 186         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 187         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 188         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 189         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 190         .emif_sdram_config_ext  = 0xc163,
 191 };
 192
 193 const struct emif_regs ddr3_emif_regs_400Mhz = {
 194         .sdram_config                   = 0x638413B2,
 195         .ref_ctrl                       = 0x00000C30,
 196         .sdram_tim1                     = 0xEAAAD4DB,
 197         .sdram_tim2                     = 0x266B7FDA,
 198         .sdram_tim3                     = 0x107F8678,
 199         .read_idle_ctrl                 = 0x00050000,
 200         .zq_config                      = 0x50074BE4,
 201         .temp_alert_config              = 0x0,
 202         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 203         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 204         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 205         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 206         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 207         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 208         .emif_rd_wr_lvl_rmp_win         = 0x0,
 209         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 210         .emif_rd_wr_lvl_ctl             = 0x0,
 211         .emif_rd_wr_exec_thresh         = 0x80000405,
 212         .emif_prio_class_serv_map       = 0x80000001,
 213         .emif_connect_id_serv_1_map     = 0x80000094,
 214         .emif_connect_id_serv_2_map     = 0x00000000,
 215         .emif_cos_config                = 0x000FFFFF
 216 };
 217
 218 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 219 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 220         .sdram_config                   = 0x638413B2,
 221         .ref_ctrl                       = 0x00000C30,
 222         .sdram_tim1                     = 0xEAAAD4DB,
 223         .sdram_tim2                     = 0x266B7FDA,
 224         .sdram_tim3                     = 0x107F8678,
 225         .read_idle_ctrl                 = 0x00050000,
 226         .zq_config                      = 0x50074BE4,
 227         .temp_alert_config              = 0x0,
 228         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 229         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 230         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 231         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 232         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 233         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 234         .emif_rd_wr_exec_thresh         = 0x80000405,
 235         .emif_prio_class_serv_map       = 0x80000001,
 236         .emif_connect_id_serv_1_map     = 0x80000094,
 237         .emif_connect_id_serv_2_map     = 0x00000000,
 238         .emif_cos_config                = 0x000FFFFF
 239 };
 240
 241 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 242 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 243         .sdram_config                   = 0x638413B2,
 244         .ref_ctrl                       = 0x00000C30,
 245         .sdram_tim1                     = 0xEAAAD4DB,
 246         .sdram_tim2                     = 0x266B7FDA,
 247         .sdram_tim3                     = 0x107F8678,
 248         .read_idle_ctrl                 = 0x00050000,
 249         .zq_config                      = 0x50074BE4,
 250         .temp_alert_config              = 0x0,
 251         .emif_ddr_phy_ctlr_1            = 0x00048008,
 252         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 253         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 254         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 255         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 256         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 257         .emif_rd_wr_exec_thresh         = 0x80000405,
 258         .emif_prio_class_serv_map       = 0x80000001,
 259         .emif_connect_id_serv_1_map     = 0x80000094,
 260         .emif_connect_id_serv_2_map     = 0x00000000,
 261         .emif_cos_config                = 0x000FFFFF
 262 };
 263
 264 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 265         .sdram_config                   = 0x638413b2,
 266         .sdram_config2                  = 0x00000000,
 267         .ref_ctrl                       = 0x00000c30,
 268         .sdram_tim1                     = 0xeaaad4db,
 269         .sdram_tim2                     = 0x266b7fda,
 270         .sdram_tim3                     = 0x107f8678,
 271         .read_idle_ctrl                 = 0x00050000,
 272         .zq_config                      = 0x50074be4,
 273         .temp_alert_config              = 0x0,
 274         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 275         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 276         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 277         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 278         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 279         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 280         .emif_rd_wr_lvl_rmp_win         = 0x0,
 281         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 282         .emif_rd_wr_lvl_ctl             = 0x00000000,
 283         .emif_rd_wr_exec_thresh         = 0x80000000,
 284         .emif_prio_class_serv_map       = 0x80000001,
 285         .emif_connect_id_serv_1_map     = 0x80000094,
 286         .emif_connect_id_serv_2_map     = 0x00000000,
 287         .emif_cos_config                = 0x000FFFFF
 288 };
 289
 290 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
 291         .sdram_config                   = 0x61a11b32,
 292         .sdram_config2                  = 0x00000000,
 293         .ref_ctrl                       = 0x00000c30,
 294         .sdram_tim1                     = 0xeaaad4db,
 295         .sdram_tim2                     = 0x266b7fda,
 296         .sdram_tim3                     = 0x107f8678,
 297         .read_idle_ctrl                 = 0x00050000,
 298         .zq_config                      = 0x50074be4,
 299         .temp_alert_config              = 0x00000000,
 300         .emif_ddr_phy_ctlr_1            = 0x00008009,
 301         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 302         .emif_ddr_ext_phy_ctrl_2        = 0x00000040,
 303         .emif_ddr_ext_phy_ctrl_3        = 0x0000003e,
 304         .emif_ddr_ext_phy_ctrl_4        = 0x00000051,
 305         .emif_ddr_ext_phy_ctrl_5        = 0x00000051,
 306         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 307         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 308         .emif_rd_wr_lvl_ctl             = 0x00000000,
 309         .emif_rd_wr_exec_thresh         = 0x00000405,
 310         .emif_prio_class_serv_map       = 0x00000000,
 311         .emif_connect_id_serv_1_map     = 0x00000000,
 312         .emif_connect_id_serv_2_map     = 0x00000000,
 313         .emif_cos_config                = 0x00ffffff
 314 };
 315
 316 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 317 {
 318         if (board_is_eposevm()) {
 319                 *regs = ext_phy_ctrl_const_base_lpddr2;
 320                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 321         }
 322
 323         return;
 324 }
 325
 326 const struct dpll_params *get_dpll_ddr_params(void)
 327 {
 328         int ind = get_sys_clk_index();
 329
 330         if (board_is_eposevm())
 331                 return &epos_evm_dpll_ddr[ind];
 332         else if (board_is_evm() || board_is_sk())
 333                 return &gp_evm_dpll_ddr;
 334         else if (board_is_idk())
 335                 return &idk_dpll_ddr;
 336
 337         printf(" Board '%s' not supported\n", board_ti_get_name());
 338         return NULL;
 339 }
 340
 341
 342 /*
 343  * get_opp_offset:
 344  * Returns the index for safest OPP of the device to boot.
 345  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 346  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 347  * This data is read from dev_attribute register which is e-fused.
 348  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 349  * OPP available. Lowest OPP starts with min_off. So returning the
 350  * bit with rightmost '0'.
 351  */
 352 static int get_opp_offset(int max_off, int min_off)
 353 {
 354         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 355         int opp, offset, i;
 356
 357         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 358         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 359
 360         for (i = max_off; i >= min_off; i--) {
 361                 offset = opp & (1 << i);
 362                 if (!offset)
 363                         return i;
 364         }
 365
 366         return min_off;
 367 }
 368
 369 const struct dpll_params *get_dpll_mpu_params(void)
 370 {
 371         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 372         u32 ind = get_sys_clk_index();
 373
 374         return &dpll_mpu[ind][opp];
 375 }
 376
 377 const struct dpll_params *get_dpll_core_params(void)
 378 {
 379         int ind = get_sys_clk_index();
 380
 381         return &dpll_core[ind];
 382 }
 383
 384 const struct dpll_params *get_dpll_per_params(void)
 385 {
 386         int ind = get_sys_clk_index();
 387
 388         return &dpll_per[ind];
 389 }
 390
 391 void scale_vcores_generic(u32 m)
 392 {
 393         int mpu_vdd, ddr_volt;
 394
 395 #ifndef CONFIG_DM_I2C
 396         if (i2c_probe(TPS65218_CHIP_PM))
 397                 return;
 398 #else
 399         if (power_tps65218_init(0))
 400                 return;
 401 #endif
 402
 403         switch (m) {
 404         case 1000:
 405                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 406                 break;
 407         case 800:
 408                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
 409                 break;
 410         case 720:
 411                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
 412                 break;
 413         case 600:
 414                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 415                 break;
 416         case 300:
 417                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
 418                 break;
 419         default:
 420                 puts("Unknown MPU clock, not scaling\n");
 421                 return;
 422         }
 423
 424         /* Set DCDC1 (CORE) voltage to 1.1V */
 425         if (tps65218_voltage_update(TPS65218_DCDC1,
 426                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 427                 printf("%s failure\n", __func__);
 428                 return;
 429         }
 430
 431         /* Set DCDC2 (MPU) voltage */
 432         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 433                 printf("%s failure\n", __func__);
 434                 return;
 435         }
 436
 437         if (board_is_eposevm())
 438                 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
 439         else
 440                 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
 441
 442         /* Set DCDC3 (DDR) voltage */
 443         if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
 444                 printf("%s failure\n", __func__);
 445                 return;
 446         }
 447 }
 448
 449 void scale_vcores_idk(u32 m)
 450 {
 451         int mpu_vdd;
 452
 453 #ifndef CONFIG_DM_I2C
 454         if (i2c_probe(TPS62362_I2C_ADDR))
 455                 return;
 456 #else
 457         if (power_tps62362_init(0))
 458                 return;
 459 #endif
 460
 461         switch (m) {
 462         case 1000:
 463                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 464                 break;
 465         case 800:
 466                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
 467                 break;
 468         case 720:
 469                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
 470                 break;
 471         case 600:
 472                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
 473                 break;
 474         case 300:
 475                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 476                 break;
 477         default:
 478                 puts("Unknown MPU clock, not scaling\n");
 479                 return;
 480         }
 481         /* Set VDD_MPU voltage */
 482         if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
 483                 printf("%s failure\n", __func__);
 484                 return;
 485         }
 486 }
 487 void gpi2c_init(void)
 488 {
 489         /* When needed to be invoked prior to BSS initialization */
 490         static bool first_time = true;
 491
 492         if (first_time) {
 493                 enable_i2c0_pin_mux();
 494 #ifndef CONFIG_DM_I2C
 495                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 496                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 497 #endif
 498                 first_time = false;
 499         }
 500 }
 501
 502 void scale_vcores(void)
 503 {
 504         const struct dpll_params *mpu_params;
 505
 506         /* Ensure I2C is initialized for PMIC configuration */
 507         gpi2c_init();
 508
 509         /* Get the frequency */
 510         mpu_params = get_dpll_mpu_params();
 511
 512         if (board_is_idk())
 513                 scale_vcores_idk(mpu_params->m);
 514         else
 515                 scale_vcores_generic(mpu_params->m);
 516 }
 517
 518 void set_uart_mux_conf(void)
 519 {
 520         enable_uart0_pin_mux();
 521 }
 522
 523 void set_mux_conf_regs(void)
 524 {
 525         enable_board_pin_mux();
 526 }
 527
 528 static void enable_vtt_regulator(void)
 529 {
 530         u32 temp;
 531
 532         /* enable module */
 533         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 534
 535         /* enable output for GPIO5_7 */
 536         writel(GPIO_SETDATAOUT(7),
 537                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 538         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 539         temp = temp & ~(GPIO_OE_ENABLE(7));
 540         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 541 }
 542
 543 enum {
 544         RTC_BOARD_EPOS = 1,
 545         RTC_BOARD_EVM14,
 546         RTC_BOARD_EVM12,
 547         RTC_BOARD_GPEVM,
 548         RTC_BOARD_SK,
 549 };
 550
 551 /*
 552  * In the rtc_only+DRR in self-refresh boot path we have the board type info
 553  * in the rtc scratch pad register hence we bypass the costly i2c reads to
 554  * eeprom and directly programthe board name string
 555  */
 556 void rtc_only_update_board_type(u32 btype)
 557 {
 558         const char *name = "";
 559         const char *rev = "1.0";
 560
 561         switch (btype) {
 562         case RTC_BOARD_EPOS:
 563                 name = "AM43EPOS";
 564                 break;
 565         case RTC_BOARD_EVM14:
 566                 name = "AM43__GP";
 567                 rev = "1.4";
 568                 break;
 569         case RTC_BOARD_EVM12:
 570                 name = "AM43__GP";
 571                 rev = "1.2";
 572                 break;
 573         case RTC_BOARD_GPEVM:
 574                 name = "AM43__GP";
 575                 break;
 576         case RTC_BOARD_SK:
 577                 name = "AM43__SK";
 578                 break;
 579         }
 580         ti_i2c_eeprom_am_set(name, rev);
 581 }
 582
 583 u32 rtc_only_get_board_type(void)
 584 {
 585         if (board_is_eposevm())
 586                 return RTC_BOARD_EPOS;
 587         else if (board_is_evm_14_or_later())
 588                 return RTC_BOARD_EVM14;
 589         else if (board_is_evm_12_or_later())
 590                 return RTC_BOARD_EVM12;
 591         else if (board_is_gpevm())
 592                 return RTC_BOARD_GPEVM;
 593         else if (board_is_sk())
 594                 return RTC_BOARD_SK;
 595
 596         return 0;
 597 }
 598
 599 void sdram_init(void)
 600 {
 601         /*
 602          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 603          * GP EMV has 1GB DDR3 connected to EMIF
 604          * along with VTT regulator.
 605          */
 606         if (board_is_eposevm()) {
 607                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 608         } else if (board_is_evm_14_or_later()) {
 609                 enable_vtt_regulator();
 610                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 611                            &ddr3_emif_regs_400Mhz_production, 0);
 612         } else if (board_is_evm_12_or_later()) {
 613                 enable_vtt_regulator();
 614                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 615                            &ddr3_emif_regs_400Mhz_beta, 0);
 616         } else if (board_is_evm()) {
 617                 enable_vtt_regulator();
 618                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 619                            &ddr3_emif_regs_400Mhz, 0);
 620         } else if (board_is_sk()) {
 621                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 622                            &ddr3_sk_emif_regs_400Mhz, 0);
 623         } else if (board_is_idk()) {
 624                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 625                            &ddr3_idk_emif_regs_400Mhz, 0);
 626         }
 627 }
 628 #endif
 629
 630 /* setup board specific PMIC */
 631 int power_init_board(void)
 632 {
 633         int rc;
 634 #ifndef CONFIG_DM_I2C
 635         struct pmic *p = NULL;
 636 #endif
 637         if (board_is_idk()) {
 638                 rc = power_tps62362_init(0);
 639                 if (rc)
 640                         goto done;
 641 #ifndef CONFIG_DM_I2C
 642                 p = pmic_get("TPS62362");
 643                 if (!p || pmic_probe(p))
 644                         goto done;
 645 #endif
 646                 puts("PMIC:  TPS62362\n");
 647         } else {
 648                 rc = power_tps65218_init(0);
 649                 if (rc)
 650                         goto done;
 651 #ifndef CONFIG_DM_I2C
 652                 p = pmic_get("TPS65218_PMIC");
 653                 if (!p || pmic_probe(p))
 654                         goto done;
 655 #endif
 656                 puts("PMIC:  TPS65218\n");
 657         }
 658 done:
 659         return 0;
 660 }
 661
 662 int board_init(void)
 663 {
 664         struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 665         u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 666             modena_init0_bw_integer, modena_init0_watermark_0;
 667
 668         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 669         gpmc_init();
 670
 671         /*
 672          * Call this to initialize *ctrl again
 673          */
 674         hw_data_init();
 675
 676         /* Clear all important bits for DSS errata that may need to be tweaked*/
 677         mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 678                            MREQPRIO_0_SAB_INIT0_MASK;
 679
 680         mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 681
 682         modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 683                                            BW_LIMITER_BW_FRAC_MASK;
 684
 685         modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 686                                         BW_LIMITER_BW_INT_MASK;
 687
 688         modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 689                                          BW_LIMITER_BW_WATERMARK_MASK;
 690
 691         /* Setting MReq Priority of the DSS*/
 692         mreqprio_0 |= 0x77;
 693
 694         /*
 695          * Set L3 Fast Configuration Register
 696          * Limiting bandwith for ARM core to 700 MBPS
 697          */
 698         modena_init0_bw_fractional |= 0x10;
 699         modena_init0_bw_integer |= 0x3;
 700
 701         writel(mreqprio_0, &cdev->mreqprio_0);
 702         writel(mreqprio_1, &cdev->mreqprio_1);
 703
 704         writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 705         writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 706         writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 707
 708         return 0;
 709 }
 710
 711 #ifdef CONFIG_BOARD_LATE_INIT
 712 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 713 static int device_okay(const char *path)
 714 {
 715         int node;
 716
 717         node = fdt_path_offset(gd->fdt_blob, path);
 718         if (node < 0)
 719                 return 0;
 720
 721         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 722 }
 723 #endif
 724
 725 int board_late_init(void)
 726 {
 727         struct udevice *dev;
 728 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 729         set_board_info_env(NULL);
 730
 731         /*
 732          * Default FIT boot on HS devices. Non FIT images are not allowed
 733          * on HS devices.
 734          */
 735         if (get_device_type() == HS_DEVICE)
 736                 env_set("boot_fit", "1");
 737 #endif
 738
 739 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 740         if (device_okay("/ocp/omap_dwc3@48380000"))
 741                 enable_usb_clocks(0);
 742         if (device_okay("/ocp/omap_dwc3@483c0000"))
 743                 enable_usb_clocks(1);
 744 #endif
 745
 746         /* Just probe the potentially supported cdce913 device */
 747         uclass_get_device(UCLASS_CLK, 0, &dev);
 748
 749         return 0;
 750 }
 751 #endif
 752
 753 #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
 754 #ifdef CONFIG_USB_DWC3
 755 static struct dwc3_device usb_otg_ss1 = {
 756         .maximum_speed = USB_SPEED_HIGH,
 757         .base = USB_OTG_SS1_BASE,
 758         .tx_fifo_resize = false,
 759         .index = 0,
 760 };
 761
 762 static struct dwc3_omap_device usb_otg_ss1_glue = {
 763         .base = (void *)USB_OTG_SS1_GLUE_BASE,
 764         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 765         .index = 0,
 766 };
 767
 768 static struct ti_usb_phy_device usb_phy1_device = {
 769         .usb2_phy_power = (void *)USB2_PHY1_POWER,
 770         .index = 0,
 771 };
 772
 773 static struct dwc3_device usb_otg_ss2 = {
 774         .maximum_speed = USB_SPEED_HIGH,
 775         .base = USB_OTG_SS2_BASE,
 776         .tx_fifo_resize = false,
 777         .index = 1,
 778 };
 779
 780 static struct dwc3_omap_device usb_otg_ss2_glue = {
 781         .base = (void *)USB_OTG_SS2_GLUE_BASE,
 782         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 783         .index = 1,
 784 };
 785
 786 static struct ti_usb_phy_device usb_phy2_device = {
 787         .usb2_phy_power = (void *)USB2_PHY2_POWER,
 788         .index = 1,
 789 };
 790
 791 int usb_gadget_handle_interrupts(int index)
 792 {
 793         u32 status;
 794
 795         status = dwc3_omap_uboot_interrupt_status(index);
 796         if (status)
 797                 dwc3_uboot_handle_interrupt(index);
 798
 799         return 0;
 800 }
 801 #endif /* CONFIG_USB_DWC3 */
 802
 803 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 804 int board_usb_init(int index, enum usb_init_type init)
 805 {
 806         enable_usb_clocks(index);
 807 #ifdef CONFIG_USB_DWC3
 808         switch (index) {
 809         case 0:
 810                 if (init == USB_INIT_DEVICE) {
 811                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 812                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 813                         dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 814                         ti_usb_phy_uboot_init(&usb_phy1_device);
 815                         dwc3_uboot_init(&usb_otg_ss1);
 816                 }
 817                 break;
 818         case 1:
 819                 if (init == USB_INIT_DEVICE) {
 820                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 821                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 822                         ti_usb_phy_uboot_init(&usb_phy2_device);
 823                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 824                         dwc3_uboot_init(&usb_otg_ss2);
 825                 }
 826                 break;
 827         default:
 828                 printf("Invalid Controller Index\n");
 829         }
 830 #endif
 831
 832         return 0;
 833 }
 834
 835 int board_usb_cleanup(int index, enum usb_init_type init)
 836 {
 837 #ifdef CONFIG_USB_DWC3
 838         switch (index) {
 839         case 0:
 840         case 1:
 841                 if (init == USB_INIT_DEVICE) {
 842                         ti_usb_phy_uboot_exit(index);
 843                         dwc3_uboot_exit(index);
 844                         dwc3_omap_uboot_exit(index);
 845                 }
 846                 break;
 847         default:
 848                 printf("Invalid Controller Index\n");
 849         }
 850 #endif
 851         disable_usb_clocks(index);
 852
 853         return 0;
 854 }
 855 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 856 #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
 857
 858 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 859 int ft_board_setup(void *blob, bd_t *bd)
 860 {
 861         ft_cpu_setup(blob, bd);
 862
 863         return 0;
 864 }
 865 #endif
 866
 867 #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
 868 int board_fit_config_name_match(const char *name)
 869 {
 870         bool eeprom_read = board_ti_was_eeprom_read();
 871
 872         if (!strcmp(name, "am4372-generic") && !eeprom_read)
 873                 return 0;
 874         else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
 875                 return 0;
 876         else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
 877                 return 0;
 878         else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
 879                 return 0;
 880         else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
 881                 return 0;
 882         else
 883                 return -1;
 884 }
 885 #endif
 886
 887 #ifdef CONFIG_DTB_RESELECT
 888 int embedded_dtb_select(void)
 889 {
 890         do_board_detect();
 891         fdtdec_setup();
 892
 893         return 0;
 894 }
 895 #endif
 896
 897 #ifdef CONFIG_TI_SECURE_DEVICE
 898 void board_fit_image_post_process(void **p_image, size_t *p_size)
 899 {
 900         secure_boot_verify_image(p_image, p_size);
 901 }
 902
 903 void board_tee_image_process(ulong tee_image, size_t tee_size)
 904 {
 905         secure_tee_install((u32)tee_image);
 906 }
 907
 908 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 909 #endif