board/ti/am335x/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <spl.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/omap.h>
  17 #include <asm/arch/ddr_defs.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/mmc_host_def.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mem.h>
  23 #include <asm/io.h>
  24 #include <asm/emif.h>
  25 #include <asm/gpio.h>
  26 #include <i2c.h>
  27 #include <miiphy.h>
  28 #include <cpsw.h>
  29 #include <power/tps65217.h>
  30 #include <power/tps65910.h>
  31 #include <environment.h>
  32 #include <watchdog.h>
  33 #include <environment.h>
  34 #include "board.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 /* GPIO that controls power to DDR on EVM-SK */
  39 #define GPIO_DDR_VTT_EN         7
  40
  41 #if defined(CONFIG_SPL_BUILD) || \
  42         (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
  43 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  44 #endif
  45
  46 /*
  47  * Read header information from EEPROM into global structure.
  48  */
  49 static int read_eeprom(struct am335x_baseboard_id *header)
  50 {
  51         /* Check if baseboard eeprom is available */
  52         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  53                 puts("Could not probe the EEPROM; something fundamentally "
  54                         "wrong on the I2C bus.\n");
  55                 return -ENODEV;
  56         }
  57
  58         /* read the eeprom using i2c */
  59         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  60                      sizeof(struct am335x_baseboard_id))) {
  61                 puts("Could not read the EEPROM; something fundamentally"
  62                         " wrong on the I2C bus.\n");
  63                 return -EIO;
  64         }
  65
  66         if (header->magic != 0xEE3355AA) {
  67                 /*
  68                  * read the eeprom using i2c again,
  69                  * but use only a 1 byte address
  70                  */
  71                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  72                              sizeof(struct am335x_baseboard_id))) {
  73                         puts("Could not read the EEPROM; something "
  74                                 "fundamentally wrong on the I2C bus.\n");
  75                         return -EIO;
  76                 }
  77
  78                 if (header->magic != 0xEE3355AA) {
  79                         printf("Incorrect magic number (0x%x) in EEPROM\n",
  80                                         header->magic);
  81                         return -EINVAL;
  82                 }
  83         }
  84
  85         return 0;
  86 }
  87
  88 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  89 static const struct ddr_data ddr2_data = {
  90         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  91         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  92         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  93 };
  94
  95 static const struct cmd_control ddr2_cmd_ctrl_data = {
  96         .cmd0csratio = MT47H128M16RT25E_RATIO,
  97
  98         .cmd1csratio = MT47H128M16RT25E_RATIO,
  99
 100         .cmd2csratio = MT47H128M16RT25E_RATIO,
 101 };
 102
 103 static const struct emif_regs ddr2_emif_reg_data = {
 104         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 105         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 106         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 107         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 108         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 109         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 110 };
 111
 112 static const struct ddr_data ddr3_data = {
 113         .datardsratio0 = MT41J128MJT125_RD_DQS,
 114         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 115         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 116         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 117 };
 118
 119 static const struct ddr_data ddr3_beagleblack_data = {
 120         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 121         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 122         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 123         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 124 };
 125
 126 static const struct ddr_data ddr3_evm_data = {
 127         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 128         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 129         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 130         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 131 };
 132
 133 static const struct cmd_control ddr3_cmd_ctrl_data = {
 134         .cmd0csratio = MT41J128MJT125_RATIO,
 135         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 136
 137         .cmd1csratio = MT41J128MJT125_RATIO,
 138         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 139
 140         .cmd2csratio = MT41J128MJT125_RATIO,
 141         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 142 };
 143
 144 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 145         .cmd0csratio = MT41K256M16HA125E_RATIO,
 146         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 147
 148         .cmd1csratio = MT41K256M16HA125E_RATIO,
 149         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 150
 151         .cmd2csratio = MT41K256M16HA125E_RATIO,
 152         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 153 };
 154
 155 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 156         .cmd0csratio = MT41J512M8RH125_RATIO,
 157         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 158
 159         .cmd1csratio = MT41J512M8RH125_RATIO,
 160         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 161
 162         .cmd2csratio = MT41J512M8RH125_RATIO,
 163         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 164 };
 165
 166 static struct emif_regs ddr3_emif_reg_data = {
 167         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 168         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 169         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 170         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 171         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 172         .zq_config = MT41J128MJT125_ZQ_CFG,
 173         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 174                                 PHY_EN_DYN_PWRDN,
 175 };
 176
 177 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 178         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 179         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 180         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 181         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 182         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 183         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 184         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 185 };
 186
 187 static struct emif_regs ddr3_evm_emif_reg_data = {
 188         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 189         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 190         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 191         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 192         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 193         .zq_config = MT41J512M8RH125_ZQ_CFG,
 194         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 195                                 PHY_EN_DYN_PWRDN,
 196 };
 197
 198 #ifdef CONFIG_SPL_OS_BOOT
 199 int spl_start_uboot(void)
 200 {
 201         /* break into full u-boot on 'c' */
 202         if (serial_tstc() && serial_getc() == 'c')
 203                 return 1;
 204
 205 #ifdef CONFIG_SPL_ENV_SUPPORT
 206         env_init();
 207         env_relocate_spec();
 208         if (getenv_yesno("boot_os") != 1)
 209                 return 1;
 210 #endif
 211
 212         return 0;
 213 }
 214 #endif
 215
 216 #define OSC     (V_OSCK/1000000)
 217 const struct dpll_params dpll_ddr = {
 218                 266, OSC-1, 1, -1, -1, -1, -1};
 219 const struct dpll_params dpll_ddr_evm_sk = {
 220                 303, OSC-1, 1, -1, -1, -1, -1};
 221 const struct dpll_params dpll_ddr_bone_black = {
 222                 400, OSC-1, 1, -1, -1, -1, -1};
 223
 224 void am33xx_spl_board_init(void)
 225 {
 226         struct am335x_baseboard_id header;
 227         int mpu_vdd;
 228
 229         if (read_eeprom(&header) < 0)
 230                 puts("Could not get board ID.\n");
 231
 232         /* Get the frequency */
 233         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 234
 235         if (board_is_bone(&header) || board_is_bone_lt(&header)) {
 236                 /* BeagleBone PMIC Code */
 237                 int usb_cur_lim;
 238
 239                 /*
 240                  * Only perform PMIC configurations if board rev > A1
 241                  * on Beaglebone White
 242                  */
 243                 if (board_is_bone(&header) && !strncmp(header.version,
 244                                                        "00A1", 4))
 245                         return;
 246
 247                 if (i2c_probe(TPS65217_CHIP_PM))
 248                         return;
 249
 250                 /*
 251                  * On Beaglebone White we need to ensure we have AC power
 252                  * before increasing the frequency.
 253                  */
 254                 if (board_is_bone(&header)) {
 255                         uchar pmic_status_reg;
 256                         if (tps65217_reg_read(TPS65217_STATUS,
 257                                               &pmic_status_reg))
 258                                 return;
 259                         if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 260                                 puts("No AC power, disabling frequency switch\n");
 261                                 return;
 262                         }
 263                 }
 264
 265                 /*
 266                  * Override what we have detected since we know if we have
 267                  * a Beaglebone Black it supports 1GHz.
 268                  */
 269                 if (board_is_bone_lt(&header))
 270                         dpll_mpu_opp100.m = MPUPLL_M_1000;
 271
 272                 /*
 273                  * Increase USB current limit to 1300mA or 1800mA and set
 274                  * the MPU voltage controller as needed.
 275                  */
 276                 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 277                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 278                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 279                 } else {
 280                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 281                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 282                 }
 283
 284                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 285                                        TPS65217_POWER_PATH,
 286                                        usb_cur_lim,
 287                                        TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 288                         puts("tps65217_reg_write failure\n");
 289
 290                 /* Set DCDC3 (CORE) voltage to 1.125V */
 291                 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 292                                             TPS65217_DCDC_VOLT_SEL_1125MV)) {
 293                         puts("tps65217_voltage_update failure\n");
 294                         return;
 295                 }
 296
 297                 /* Set CORE Frequencies to OPP100 */
 298                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 299
 300                 /* Set DCDC2 (MPU) voltage */
 301                 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 302                         puts("tps65217_voltage_update failure\n");
 303                         return;
 304                 }
 305
 306                 /*
 307                  * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 308                  * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 309                  */
 310                 if (board_is_bone(&header)) {
 311                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 312                                                TPS65217_DEFLS1,
 313                                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 314                                                TPS65217_LDO_MASK))
 315                                 puts("tps65217_reg_write failure\n");
 316                 } else {
 317                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 318                                                TPS65217_DEFLS1,
 319                                                TPS65217_LDO_VOLTAGE_OUT_1_8,
 320                                                TPS65217_LDO_MASK))
 321                                 puts("tps65217_reg_write failure\n");
 322                 }
 323
 324                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 325                                        TPS65217_DEFLS2,
 326                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
 327                                        TPS65217_LDO_MASK))
 328                         puts("tps65217_reg_write failure\n");
 329         } else {
 330                 int sil_rev;
 331
 332                 /*
 333                  * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 334                  * MPU frequencies we support we use a CORE voltage of
 335                  * 1.1375V.  For MPU voltage we need to switch based on
 336                  * the frequency we are running at.
 337                  */
 338                 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
 339                         return;
 340
 341                 /*
 342                  * Depending on MPU clock and PG we will need a different
 343                  * VDD to drive at that speed.
 344                  */
 345                 sil_rev = readl(&cdev->deviceid) >> 28;
 346                 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
 347                                                       dpll_mpu_opp100.m);
 348
 349                 /* Tell the TPS65910 to use i2c */
 350                 tps65910_set_i2c_control();
 351
 352                 /* First update MPU voltage. */
 353                 if (tps65910_voltage_update(MPU, mpu_vdd))
 354                         return;
 355
 356                 /* Second, update the CORE voltage. */
 357                 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 358                         return;
 359
 360                 /* Set CORE Frequencies to OPP100 */
 361                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 362         }
 363
 364         /* Set MPU Frequency to what we detected now that voltages are set */
 365         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 366 }
 367
 368 const struct dpll_params *get_dpll_ddr_params(void)
 369 {
 370         struct am335x_baseboard_id header;
 371
 372         enable_i2c0_pin_mux();
 373         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 374         if (read_eeprom(&header) < 0)
 375                 puts("Could not get board ID.\n");
 376
 377         if (board_is_evm_sk(&header))
 378                 return &dpll_ddr_evm_sk;
 379         else if (board_is_bone_lt(&header))
 380                 return &dpll_ddr_bone_black;
 381         else if (board_is_evm_15_or_later(&header))
 382                 return &dpll_ddr_evm_sk;
 383         else
 384                 return &dpll_ddr;
 385 }
 386
 387 void set_uart_mux_conf(void)
 388 {
 389 #if CONFIG_CONS_INDEX == 1
 390         enable_uart0_pin_mux();
 391 #elif CONFIG_CONS_INDEX == 2
 392         enable_uart1_pin_mux();
 393 #elif CONFIG_CONS_INDEX == 3
 394         enable_uart2_pin_mux();
 395 #elif CONFIG_CONS_INDEX == 4
 396         enable_uart3_pin_mux();
 397 #elif CONFIG_CONS_INDEX == 5
 398         enable_uart4_pin_mux();
 399 #elif CONFIG_CONS_INDEX == 6
 400         enable_uart5_pin_mux();
 401 #endif
 402 }
 403
 404 void set_mux_conf_regs(void)
 405 {
 406         __maybe_unused struct am335x_baseboard_id header;
 407
 408         if (read_eeprom(&header) < 0)
 409                 puts("Could not get board ID.\n");
 410
 411         enable_board_pin_mux(&header);
 412 }
 413
 414 const struct ctrl_ioregs ioregs_evmsk = {
 415         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 416         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 417         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 418         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 419         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 420 };
 421
 422 const struct ctrl_ioregs ioregs_bonelt = {
 423         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 424         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 425         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 426         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 427         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 428 };
 429
 430 const struct ctrl_ioregs ioregs_evm15 = {
 431         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 432         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 433         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 434         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 435         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 436 };
 437
 438 const struct ctrl_ioregs ioregs = {
 439         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 440         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 441         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 442         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 443         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 444 };
 445
 446 void sdram_init(void)
 447 {
 448         __maybe_unused struct am335x_baseboard_id header;
 449
 450         if (read_eeprom(&header) < 0)
 451                 puts("Could not get board ID.\n");
 452
 453         if (board_is_evm_sk(&header)) {
 454                 /*
 455                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 456                  * This is safe enough to do on older revs.
 457                  */
 458                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 459                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 460         }
 461
 462         if (board_is_evm_sk(&header))
 463                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
 464                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 465         else if (board_is_bone_lt(&header))
 466                 config_ddr(400, &ioregs_bonelt,
 467                            &ddr3_beagleblack_data,
 468                            &ddr3_beagleblack_cmd_ctrl_data,
 469                            &ddr3_beagleblack_emif_reg_data, 0);
 470         else if (board_is_evm_15_or_later(&header))
 471                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 472                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 473         else
 474                 config_ddr(266, &ioregs, &ddr2_data,
 475                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 476 }
 477 #endif
 478
 479 /*
 480  * Basic board specific setup.  Pinmux has been handled already.
 481  */
 482 int board_init(void)
 483 {
 484 #if defined(CONFIG_HW_WATCHDOG)
 485         hw_watchdog_init();
 486 #endif
 487
 488         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 489 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 490         gpmc_init();
 491 #endif
 492         return 0;
 493 }
 494
 495 #ifdef CONFIG_BOARD_LATE_INIT
 496 int board_late_init(void)
 497 {
 498 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 499         char safe_string[HDR_NAME_LEN + 1];
 500         struct am335x_baseboard_id header;
 501
 502         if (read_eeprom(&header) < 0)
 503                 puts("Could not get board ID.\n");
 504
 505         /* Now set variables based on the header. */
 506         strncpy(safe_string, (char *)header.name, sizeof(header.name));
 507         safe_string[sizeof(header.name)] = 0;
 508         setenv("board_name", safe_string);
 509
 510         /* BeagleBone Green eeprom, board_rev: 0x1a 0x00 0x00 0x00 */
 511         if ( (header.version[0] == 0x1a) && (header.version[1] == 0x00) &&
 512              (header.version[2] == 0x00) && (header.version[3] == 0x00) ) {
 513                 setenv("board_rev", "BBG1");
 514         } else {
 515                 strncpy(safe_string, (char *)header.version, sizeof(header.version));
 516                 safe_string[sizeof(header.version)] = 0;
 517                 setenv("board_rev", safe_string);
 518         }
 519 #endif
 520
 521         return 0;
 522 }
 523 #endif
 524
 525 #ifndef CONFIG_DM_ETH
 526
 527 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 528         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 529 static void cpsw_control(int enabled)
 530 {
 531         /* VTP can be added here */
 532
 533         return;
 534 }
 535
 536 static struct cpsw_slave_data cpsw_slaves[] = {
 537         {
 538                 .slave_reg_ofs  = 0x208,
 539                 .sliver_reg_ofs = 0xd80,
 540                 .phy_addr       = 0,
 541         },
 542         {
 543                 .slave_reg_ofs  = 0x308,
 544                 .sliver_reg_ofs = 0xdc0,
 545                 .phy_addr       = 1,
 546         },
 547 };
 548
 549 static struct cpsw_platform_data cpsw_data = {
 550         .mdio_base              = CPSW_MDIO_BASE,
 551         .cpsw_base              = CPSW_BASE,
 552         .mdio_div               = 0xff,
 553         .channels               = 8,
 554         .cpdma_reg_ofs          = 0x800,
 555         .slaves                 = 1,
 556         .slave_data             = cpsw_slaves,
 557         .ale_reg_ofs            = 0xd00,
 558         .ale_entries            = 1024,
 559         .host_port_reg_ofs      = 0x108,
 560         .hw_stats_reg_ofs       = 0x900,
 561         .bd_ram_ofs             = 0x2000,
 562         .mac_control            = (1 << 5),
 563         .control                = cpsw_control,
 564         .host_port_num          = 0,
 565         .version                = CPSW_CTRL_VERSION_2,
 566 };
 567 #endif
 568
 569 /*
 570  * This function will:
 571  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
 572  * in the environment
 573  * Perform fixups to the PHY present on certain boards.  We only need this
 574  * function in:
 575  * - SPL with either CPSW or USB ethernet support
 576  * - Full U-Boot, with either CPSW or USB ethernet
 577  * Build in only these cases to avoid warnings about unused variables
 578  * when we build an SPL that has neither option but full U-Boot will.
 579  */
 580 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
 581                 && defined(CONFIG_SPL_BUILD)) || \
 582         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 583           defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
 584          !defined(CONFIG_SPL_BUILD))
 585 int board_eth_init(bd_t *bis)
 586 {
 587         int rv, n = 0;
 588         uint8_t mac_addr[6];
 589         uint32_t mac_hi, mac_lo;
 590         __maybe_unused struct am335x_baseboard_id header;
 591
 592         /* try reading mac address from efuse */
 593         mac_lo = readl(&cdev->macid0l);
 594         mac_hi = readl(&cdev->macid0h);
 595         mac_addr[0] = mac_hi & 0xFF;
 596         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 597         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 598         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 599         mac_addr[4] = mac_lo & 0xFF;
 600         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 601
 602 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 603         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 604         if (!getenv("ethaddr")) {
 605                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 606
 607                 if (is_valid_ethaddr(mac_addr))
 608                         eth_setenv_enetaddr("ethaddr", mac_addr);
 609         }
 610
 611 #ifdef CONFIG_DRIVER_TI_CPSW
 612
 613         mac_lo = readl(&cdev->macid1l);
 614         mac_hi = readl(&cdev->macid1h);
 615         mac_addr[0] = mac_hi & 0xFF;
 616         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 617         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 618         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 619         mac_addr[4] = mac_lo & 0xFF;
 620         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 621
 622         if (!getenv("eth1addr")) {
 623                 if (is_valid_ethaddr(mac_addr))
 624                         eth_setenv_enetaddr("eth1addr", mac_addr);
 625         }
 626
 627         if (read_eeprom(&header) < 0)
 628                 puts("Could not get board ID.\n");
 629
 630         if (board_is_bone(&header) || board_is_bone_lt(&header) ||
 631             board_is_idk(&header)) {
 632                 writel(MII_MODE_ENABLE, &cdev->miisel);
 633                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 634                                 PHY_INTERFACE_MODE_MII;
 635         } else {
 636                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 637                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 638                                 PHY_INTERFACE_MODE_RGMII;
 639         }
 640
 641         rv = cpsw_register(&cpsw_data);
 642         if (rv < 0)
 643                 printf("Error %d registering CPSW switch\n", rv);
 644         else
 645                 n += rv;
 646 #endif
 647
 648         /*
 649          *
 650          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 651          * operating points.  So we must set the TX clock delay feature
 652          * in the AR8051 PHY.  Since we only support a single ethernet
 653          * device in U-Boot, we only do this for the first instance.
 654          */
 655 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 656 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 657 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 658 #define AR8051_RGMII_TX_CLK_DLY         0x100
 659
 660         if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
 661                 const char *devname;
 662                 devname = miiphy_get_current_dev();
 663
 664                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 665                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
 666                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 667                                 AR8051_RGMII_TX_CLK_DLY);
 668         }
 669 #endif
 670 #if defined(CONFIG_USB_ETHER) && \
 671         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 672         if (is_valid_ethaddr(mac_addr))
 673                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 674
 675         rv = usb_eth_initialize(bis);
 676         if (rv < 0)
 677                 printf("Error %d registering USB_ETHER\n", rv);
 678         else
 679                 n += rv;
 680 #endif
 681         return n;
 682 }
 683 #endif
 684
 685 #endif /* CONFIG_DM_ETH */