board/ti/am335x/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TI AM335X based boards
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <env.h>
  13 #include <errno.h>
  14 #include <hang.h>
  15 #include <image.h>
  16 #include <init.h>
  17 #include <malloc.h>
  18 #include <net.h>
  19 #include <spl.h>
  20 #include <serial.h>
  21 #include <asm/arch/cpu.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/arch/omap.h>
  24 #include <asm/arch/ddr_defs.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/clk_synthesizer.h>
  27 #include <asm/arch/gpio.h>
  28 #include <asm/arch/mmc_host_def.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/arch/mem.h>
  31 #include <asm/global_data.h>
  32 #include <asm/io.h>
  33 #include <asm/emif.h>
  34 #include <asm/gpio.h>
  35 #include <asm/omap_common.h>
  36 #include <asm/omap_mmc.h>
  37 #include <i2c.h>
  38 #include <miiphy.h>
  39 #include <cpsw.h>
  40 #include <linux/bitops.h>
  41 #include <linux/compiler.h>
  42 #include <linux/delay.h>
  43 #include <power/tps65217.h>
  44 #include <power/tps65910.h>
  45 #include <env_internal.h>
  46 #include <watchdog.h>
  47 #include "../common/board_detect.h"
  48 #include "../common/cape_detect.h"
  49 #include "board.h"
  50
  51 DECLARE_GLOBAL_DATA_PTR;
  52
  53 /* GPIO that controls power to DDR on EVM-SK */
  54 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
  55 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
  56 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
  57 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
  58 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
  59 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
  60 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
  61 #define GPIO_ETH0_MODE          GPIO_TO_PIN(0, 11)
  62 #define GPIO_ETH1_MODE          GPIO_TO_PIN(1, 26)
  63
  64 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  65
  66 #define GPIO0_RISINGDETECT      (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  67 #define GPIO1_RISINGDETECT      (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  68
  69 #define GPIO0_IRQSTATUS1        (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  70 #define GPIO1_IRQSTATUS1        (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  71
  72 #define GPIO0_IRQSTATUSRAW      (AM33XX_GPIO0_BASE + 0x024)
  73 #define GPIO1_IRQSTATUSRAW      (AM33XX_GPIO1_BASE + 0x024)
  74
  75 /*
  76  * Read header information from EEPROM into global structure.
  77  */
  78 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  79 void do_board_detect(void)
  80 {
  81         enable_i2c0_pin_mux();
  82         enable_i2c2_pin_mux();
  83         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  84                                  CONFIG_EEPROM_CHIP_ADDRESS))
  85                 printf("ti_i2c_eeprom_init failed\n");
  86 }
  87 #endif
  88
  89 #ifndef CONFIG_DM_SERIAL
  90 struct serial_device *default_serial_console(void)
  91 {
  92         if (board_is_icev2())
  93                 return &eserial4_device;
  94         else
  95                 return &eserial1_device;
  96 }
  97 #endif
  98
  99 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 100 static const struct ddr_data ddr2_data = {
 101         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
 102         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
 103         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
 104 };
 105
 106 static const struct cmd_control ddr2_cmd_ctrl_data = {
 107         .cmd0csratio = MT47H128M16RT25E_RATIO,
 108
 109         .cmd1csratio = MT47H128M16RT25E_RATIO,
 110
 111         .cmd2csratio = MT47H128M16RT25E_RATIO,
 112 };
 113
 114 static const struct emif_regs ddr2_emif_reg_data = {
 115         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 116         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 117         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 118         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 119         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 120         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 121 };
 122
 123 static const struct emif_regs ddr2_evm_emif_reg_data = {
 124         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 125         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 126         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 127         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 128         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 129         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 130         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 131 };
 132
 133 static const struct ddr_data ddr3_data = {
 134         .datardsratio0 = MT41J128MJT125_RD_DQS,
 135         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 136         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 137         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 138 };
 139
 140 static const struct ddr_data ddr3_beagleblack_data = {
 141         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 142         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 143         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 144         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 145 };
 146
 147 static const struct ddr_data ddr3_evm_data = {
 148         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 149         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 150         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 151         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 152 };
 153
 154 static const struct ddr_data ddr3_icev2_data = {
 155         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
 156         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
 157         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
 158         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
 159 };
 160
 161 static const struct cmd_control ddr3_cmd_ctrl_data = {
 162         .cmd0csratio = MT41J128MJT125_RATIO,
 163         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 164
 165         .cmd1csratio = MT41J128MJT125_RATIO,
 166         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 167
 168         .cmd2csratio = MT41J128MJT125_RATIO,
 169         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 170 };
 171
 172 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 173         .cmd0csratio = MT41K256M16HA125E_RATIO,
 174         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 175
 176         .cmd1csratio = MT41K256M16HA125E_RATIO,
 177         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 178
 179         .cmd2csratio = MT41K256M16HA125E_RATIO,
 180         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 181 };
 182
 183 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 184         .cmd0csratio = MT41J512M8RH125_RATIO,
 185         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 186
 187         .cmd1csratio = MT41J512M8RH125_RATIO,
 188         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 189
 190         .cmd2csratio = MT41J512M8RH125_RATIO,
 191         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 192 };
 193
 194 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
 195         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
 196         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 197
 198         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
 199         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 200
 201         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
 202         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 203 };
 204
 205 static struct emif_regs ddr3_emif_reg_data = {
 206         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 207         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 208         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 209         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 210         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 211         .zq_config = MT41J128MJT125_ZQ_CFG,
 212         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 213                                 PHY_EN_DYN_PWRDN,
 214 };
 215
 216 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 217         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 218         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 219         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 220         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 221         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 222         .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
 223         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 224         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 225 };
 226
 227 static struct emif_regs ddr3_evm_emif_reg_data = {
 228         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 229         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 230         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 231         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 232         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 233         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 234         .zq_config = MT41J512M8RH125_ZQ_CFG,
 235         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 236                                 PHY_EN_DYN_PWRDN,
 237 };
 238
 239 static struct emif_regs ddr3_icev2_emif_reg_data = {
 240         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
 241         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
 242         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
 243         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
 244         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
 245         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
 246         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
 247                                 PHY_EN_DYN_PWRDN,
 248 };
 249
 250 #ifdef CONFIG_SPL_OS_BOOT
 251 int spl_start_uboot(void)
 252 {
 253 #ifdef CONFIG_SPL_SERIAL
 254         /* break into full u-boot on 'c' */
 255         if (serial_tstc() && serial_getc() == 'c')
 256                 return 1;
 257 #endif
 258
 259 #ifdef CONFIG_SPL_ENV_SUPPORT
 260         env_init();
 261         env_load();
 262         if (env_get_yesno("boot_os") != 1)
 263                 return 1;
 264 #endif
 265
 266         return 0;
 267 }
 268 #endif
 269
 270 const struct dpll_params *get_dpll_ddr_params(void)
 271 {
 272         int ind = get_sys_clk_index();
 273
 274         if (board_is_evm_sk())
 275                 return &dpll_ddr3_303MHz[ind];
 276         else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
 277                 return &dpll_ddr3_400MHz[ind];
 278         else if (board_is_evm_15_or_later())
 279                 return &dpll_ddr3_303MHz[ind];
 280         else
 281                 return &dpll_ddr2_266MHz[ind];
 282 }
 283
 284 static u8 bone_not_connected_to_ac_power(void)
 285 {
 286         if (board_is_bone()) {
 287                 uchar pmic_status_reg;
 288                 if (tps65217_reg_read(TPS65217_STATUS,
 289                                       &pmic_status_reg))
 290                         return 1;
 291                 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 292                         puts("No AC power, switching to default OPP\n");
 293                         return 1;
 294                 }
 295         }
 296         return 0;
 297 }
 298
 299 const struct dpll_params *get_dpll_mpu_params(void)
 300 {
 301         int ind = get_sys_clk_index();
 302         int freq = am335x_get_efuse_mpu_max_freq(cdev);
 303
 304         if (bone_not_connected_to_ac_power())
 305                 freq = MPUPLL_M_600;
 306
 307         if (board_is_pb() || board_is_bone_lt())
 308                 freq = MPUPLL_M_1000;
 309
 310         switch (freq) {
 311         case MPUPLL_M_1000:
 312                 return &dpll_mpu_opp[ind][5];
 313         case MPUPLL_M_800:
 314                 return &dpll_mpu_opp[ind][4];
 315         case MPUPLL_M_720:
 316                 return &dpll_mpu_opp[ind][3];
 317         case MPUPLL_M_600:
 318                 return &dpll_mpu_opp[ind][2];
 319         case MPUPLL_M_500:
 320                 return &dpll_mpu_opp100;
 321         case MPUPLL_M_300:
 322                 return &dpll_mpu_opp[ind][0];
 323         }
 324
 325         return &dpll_mpu_opp[ind][0];
 326 }
 327
 328 static void scale_vcores_bone(int freq)
 329 {
 330         int usb_cur_lim, mpu_vdd;
 331
 332         /*
 333          * Only perform PMIC configurations if board rev > A1
 334          * on Beaglebone White
 335          */
 336         if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
 337                 return;
 338
 339         if (power_tps65217_init(0))
 340                 return;
 341
 342
 343         /*
 344          * On Beaglebone White we need to ensure we have AC power
 345          * before increasing the frequency.
 346          */
 347         if (bone_not_connected_to_ac_power())
 348                 freq = MPUPLL_M_600;
 349
 350         /*
 351          * Override what we have detected since we know if we have
 352          * a Beaglebone Black it supports 1GHz.
 353          */
 354         if (board_is_pb() || board_is_bone_lt())
 355                 freq = MPUPLL_M_1000;
 356
 357         switch (freq) {
 358         case MPUPLL_M_1000:
 359                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 360                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 361                 break;
 362         case MPUPLL_M_800:
 363                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 364                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 365                 break;
 366         case MPUPLL_M_720:
 367                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
 368                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 369                 break;
 370         case MPUPLL_M_600:
 371         case MPUPLL_M_500:
 372         case MPUPLL_M_300:
 373         default:
 374                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
 375                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 376                 break;
 377         }
 378
 379         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 380                                TPS65217_POWER_PATH,
 381                                usb_cur_lim,
 382                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 383                 puts("tps65217_reg_write failure\n");
 384
 385         /* Set DCDC3 (CORE) voltage to 1.10V */
 386         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 387                                     TPS65217_DCDC_VOLT_SEL_1100MV)) {
 388                 puts("tps65217_voltage_update failure\n");
 389                 return;
 390         }
 391
 392         /* Set DCDC2 (MPU) voltage */
 393         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 394                 puts("tps65217_voltage_update failure\n");
 395                 return;
 396         }
 397
 398         /*
 399          * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 400          * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 401          */
 402         if (board_is_bone()) {
 403                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 404                                        TPS65217_DEFLS1,
 405                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
 406                                        TPS65217_LDO_MASK))
 407                         puts("tps65217_reg_write failure\n");
 408         } else {
 409                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 410                                        TPS65217_DEFLS1,
 411                                        TPS65217_LDO_VOLTAGE_OUT_1_8,
 412                                        TPS65217_LDO_MASK))
 413                         puts("tps65217_reg_write failure\n");
 414         }
 415
 416         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 417                                TPS65217_DEFLS2,
 418                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 419                                TPS65217_LDO_MASK))
 420                 puts("tps65217_reg_write failure\n");
 421 }
 422
 423 void scale_vcores_generic(int freq)
 424 {
 425         int sil_rev, mpu_vdd;
 426
 427         /*
 428          * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 429          * MPU frequencies we support we use a CORE voltage of
 430          * 1.10V.  For MPU voltage we need to switch based on
 431          * the frequency we are running at.
 432          */
 433         if (power_tps65910_init(0))
 434                 return;
 435         /*
 436          * Depending on MPU clock and PG we will need a different
 437          * VDD to drive at that speed.
 438          */
 439         sil_rev = readl(&cdev->deviceid) >> 28;
 440         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
 441
 442         /* Tell the TPS65910 to use i2c */
 443         tps65910_set_i2c_control();
 444
 445         /* First update MPU voltage. */
 446         if (tps65910_voltage_update(MPU, mpu_vdd))
 447                 return;
 448
 449         /* Second, update the CORE voltage. */
 450         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
 451                 return;
 452
 453 }
 454
 455 void gpi2c_init(void)
 456 {
 457         /* When needed to be invoked prior to BSS initialization */
 458         static bool first_time = true;
 459
 460         if (first_time) {
 461                 enable_i2c0_pin_mux();
 462                 first_time = false;
 463         }
 464 }
 465
 466 void scale_vcores(void)
 467 {
 468         int freq;
 469
 470         gpi2c_init();
 471         freq = am335x_get_efuse_mpu_max_freq(cdev);
 472
 473         if (board_is_beaglebonex())
 474                 scale_vcores_bone(freq);
 475         else
 476                 scale_vcores_generic(freq);
 477 }
 478
 479 void set_uart_mux_conf(void)
 480 {
 481 #if CONFIG_CONS_INDEX == 1
 482         enable_uart0_pin_mux();
 483 #elif CONFIG_CONS_INDEX == 2
 484         enable_uart1_pin_mux();
 485 #elif CONFIG_CONS_INDEX == 3
 486         enable_uart2_pin_mux();
 487 #elif CONFIG_CONS_INDEX == 4
 488         enable_uart3_pin_mux();
 489 #elif CONFIG_CONS_INDEX == 5
 490         enable_uart4_pin_mux();
 491 #elif CONFIG_CONS_INDEX == 6
 492         enable_uart5_pin_mux();
 493 #endif
 494 }
 495
 496 void set_mux_conf_regs(void)
 497 {
 498         enable_board_pin_mux();
 499 }
 500
 501 const struct ctrl_ioregs ioregs_evmsk = {
 502         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 503         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 504         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 505         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 506         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 507 };
 508
 509 const struct ctrl_ioregs ioregs_bonelt = {
 510         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 511         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 512         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 513         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 514         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 515 };
 516
 517 const struct ctrl_ioregs ioregs_evm15 = {
 518         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 519         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 520         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 521         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 522         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 523 };
 524
 525 const struct ctrl_ioregs ioregs = {
 526         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 527         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 528         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 529         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 530         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 531 };
 532
 533 void sdram_init(void)
 534 {
 535         if (board_is_evm_sk()) {
 536                 /*
 537                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 538                  * This is safe enough to do on older revs.
 539                  */
 540                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 541                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 542         }
 543
 544         if (board_is_icev2()) {
 545                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
 546                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
 547         }
 548
 549         if (board_is_evm_sk())
 550                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
 551                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 552         else if (board_is_pb() || board_is_bone_lt())
 553                 config_ddr(400, &ioregs_bonelt,
 554                            &ddr3_beagleblack_data,
 555                            &ddr3_beagleblack_cmd_ctrl_data,
 556                            &ddr3_beagleblack_emif_reg_data, 0);
 557         else if (board_is_evm_15_or_later())
 558                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 559                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 560         else if (board_is_icev2())
 561                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 562                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 563                            0);
 564         else if (board_is_gp_evm())
 565                 config_ddr(266, &ioregs, &ddr2_data,
 566                            &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
 567         else
 568                 config_ddr(266, &ioregs, &ddr2_data,
 569                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 570 }
 571 #endif
 572
 573 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
 574         (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)))
 575 static void request_and_set_gpio(int gpio, char *name, int val)
 576 {
 577         int ret;
 578
 579         ret = gpio_request(gpio, name);
 580         if (ret < 0) {
 581                 printf("%s: Unable to request %s\n", __func__, name);
 582                 return;
 583         }
 584
 585         ret = gpio_direction_output(gpio, 0);
 586         if (ret < 0) {
 587                 printf("%s: Unable to set %s  as output\n", __func__, name);
 588                 goto err_free_gpio;
 589         }
 590
 591         gpio_set_value(gpio, val);
 592
 593         return;
 594
 595 err_free_gpio:
 596         gpio_free(gpio);
 597 }
 598
 599 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
 600 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
 601
 602 /**
 603  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
 604  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
 605  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
 606  * give 50MHz output for Eth0 and 1.
 607  */
 608 static struct clk_synth cdce913_data = {
 609         .id = 0x81,
 610         .capacitor = 0x90,
 611         .mux = 0x6d,
 612         .pdiv2 = 0x2,
 613         .pdiv3 = 0x2,
 614 };
 615 #endif
 616
 617 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
 618         defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
 619
 620 #define MAX_CPSW_SLAVES 2
 621
 622 /* At the moment, we do not want to stop booting for any failures here */
 623 int ft_board_setup(void *fdt, struct bd_info *bd)
 624 {
 625         const char *slave_path, *enet_name;
 626         int enetnode, slavenode, phynode;
 627         struct udevice *ethdev;
 628         char alias[16];
 629         u32 phy_id[2];
 630         int phy_addr;
 631         int i, ret;
 632
 633         /* phy address fixup needed only on beagle bone family */
 634         if (!board_is_beaglebonex())
 635                 goto done;
 636
 637         for (i = 0; i < MAX_CPSW_SLAVES; i++) {
 638                 sprintf(alias, "ethernet%d", i);
 639
 640                 slave_path = fdt_get_alias(fdt, alias);
 641                 if (!slave_path)
 642                         continue;
 643
 644                 slavenode = fdt_path_offset(fdt, slave_path);
 645                 if (slavenode < 0)
 646                         continue;
 647
 648                 enetnode = fdt_parent_offset(fdt, slavenode);
 649                 enet_name = fdt_get_name(fdt, enetnode, NULL);
 650
 651                 ethdev = eth_get_dev_by_name(enet_name);
 652                 if (!ethdev)
 653                         continue;
 654
 655                 phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
 656
 657                 /* check for phy_id as well as phy-handle properties */
 658                 ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
 659                                                  phy_id, 2);
 660                 if (ret == 2) {
 661                         if (phy_id[1] != phy_addr) {
 662                                 printf("fixing up phy_id for %s, old: %d, new: %d\n",
 663                                        alias, phy_id[1], phy_addr);
 664
 665                                 phy_id[0] = cpu_to_fdt32(phy_id[0]);
 666                                 phy_id[1] = cpu_to_fdt32(phy_addr);
 667                                 do_fixup_by_path(fdt, slave_path, "phy_id",
 668                                                  phy_id, sizeof(phy_id), 0);
 669                         }
 670                 } else {
 671                         phynode = fdtdec_lookup_phandle(fdt, slavenode,
 672                                                         "phy-handle");
 673                         if (phynode < 0)
 674                                 continue;
 675
 676                         ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
 677                         if (ret < 0)
 678                                 continue;
 679
 680                         if (ret != phy_addr) {
 681                                 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
 682                                        alias, ret, phy_addr);
 683
 684                                 fdt_setprop_u32(fdt, phynode, "reg",
 685                                                 cpu_to_fdt32(phy_addr));
 686                         }
 687                 }
 688         }
 689
 690 done:
 691         return 0;
 692 }
 693 #endif
 694
 695 static bool __maybe_unused prueth_is_mii = true;
 696
 697 /*
 698  * Basic board specific setup.  Pinmux has been handled already.
 699  */
 700 int board_init(void)
 701 {
 702 #if defined(CONFIG_HW_WATCHDOG)
 703         hw_watchdog_init();
 704 #endif
 705
 706         gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 707 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
 708         gpmc_init();
 709 #endif
 710
 711 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
 712         (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)))
 713         if (board_is_icev2()) {
 714                 int rv;
 715                 u32 reg;
 716                 bool eth0_is_mii = true;
 717                 bool eth1_is_mii = true;
 718
 719                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
 720                 /* Make J19 status available on GPIO1_26 */
 721                 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
 722
 723                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
 724                 /*
 725                  * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
 726                  * jumpers near the port. Read the jumper value and set
 727                  * the pinmux, external mux and PHY clock accordingly.
 728                  * As jumper line is overridden by PHY RX_DV pin immediately
 729                  * after bootstrap (power-up/reset), we need to sample
 730                  * it during PHY reset using GPIO rising edge detection.
 731                  */
 732                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
 733                 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
 734                 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
 735                 writel(reg, GPIO0_RISINGDETECT);
 736                 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
 737                 writel(reg, GPIO1_RISINGDETECT);
 738                 /* Reset PHYs to capture the Jumper setting */
 739                 gpio_set_value(GPIO_PHY_RESET, 0);
 740                 udelay(2);      /* PHY datasheet states 1uS min. */
 741                 gpio_set_value(GPIO_PHY_RESET, 1);
 742
 743                 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
 744                 if (reg) {
 745                         writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
 746                         /* RMII mode */
 747                         printf("ETH0, CPSW\n");
 748                         eth0_is_mii = false;
 749                 } else {
 750                         /* MII mode */
 751                         printf("ETH0, PRU\n");
 752                         cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
 753                 }
 754
 755                 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
 756                 if (reg) {
 757                         writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
 758                         /* RMII mode */
 759                         printf("ETH1, CPSW\n");
 760                         gpio_set_value(GPIO_MUX_MII_CTRL, 1);
 761                         eth1_is_mii = false;
 762                 } else {
 763                         /* MII mode */
 764                         printf("ETH1, PRU\n");
 765                         cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
 766                 }
 767
 768                 if (eth0_is_mii != eth1_is_mii) {
 769                         printf("Unsupported Ethernet port configuration\n");
 770                         printf("Both ports must be set as RMII or MII\n");
 771                         hang();
 772                 }
 773
 774                 prueth_is_mii = eth0_is_mii;
 775
 776                 /* disable rising edge IRQs */
 777                 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
 778                 writel(reg, GPIO0_RISINGDETECT);
 779                 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
 780                 writel(reg, GPIO1_RISINGDETECT);
 781
 782                 rv = setup_clock_synthesizer(&cdce913_data);
 783                 if (rv) {
 784                         printf("Clock synthesizer setup failed %d\n", rv);
 785                         return rv;
 786                 }
 787
 788                 /* reset PHYs */
 789                 gpio_set_value(GPIO_PHY_RESET, 0);
 790                 udelay(2);      /* PHY datasheet states 1uS min. */
 791                 gpio_set_value(GPIO_PHY_RESET, 1);
 792         }
 793 #endif
 794
 795         return 0;
 796 }
 797
 798 #ifdef CONFIG_BOARD_LATE_INIT
 799 int board_late_init(void)
 800 {
 801         struct udevice *dev;
 802 #if !defined(CONFIG_SPL_BUILD)
 803         uint8_t mac_addr[6];
 804         uint32_t mac_hi, mac_lo;
 805 #endif
 806
 807 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 808         char *name = NULL;
 809
 810         if (board_is_bone_lt()) {
 811                 /* BeagleBoard.org BeagleBone Black Wireless: */
 812                 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
 813                         name = "BBBW";
 814                 }
 815                 /* SeeedStudio BeagleBone Green Wireless */
 816                 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
 817                         name = "BBGW";
 818                 }
 819                 /* BeagleBoard.org BeagleBone Blue */
 820                 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
 821                         name = "BBBL";
 822                 }
 823         }
 824
 825         if (board_is_bbg1())
 826                 name = "BBG1";
 827         if (board_is_bben()) {
 828                 char subtype_id = board_ti_get_config()[1];
 829
 830                 switch (subtype_id) {
 831                 case 'L':
 832                         name = "BBELITE";
 833                         break;
 834                 case 'I':
 835                         name = "BBE_EX_WIFI";
 836                         break;
 837                 default:
 838                         name = "BBEN";
 839                 }
 840         }
 841         set_board_info_env(name);
 842
 843         /*
 844          * Default FIT boot on HS devices. Non FIT images are not allowed
 845          * on HS devices.
 846          */
 847         if (get_device_type() == HS_DEVICE)
 848                 env_set("boot_fit", "1");
 849 #endif
 850
 851 #if !defined(CONFIG_SPL_BUILD)
 852         /* try reading mac address from efuse */
 853         mac_lo = readl(&cdev->macid0l);
 854         mac_hi = readl(&cdev->macid0h);
 855         mac_addr[0] = mac_hi & 0xFF;
 856         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 857         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 858         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 859         mac_addr[4] = mac_lo & 0xFF;
 860         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 861
 862         if (!env_get("ethaddr")) {
 863                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 864
 865                 if (is_valid_ethaddr(mac_addr))
 866                         eth_env_set_enetaddr("ethaddr", mac_addr);
 867         }
 868
 869         mac_lo = readl(&cdev->macid1l);
 870         mac_hi = readl(&cdev->macid1h);
 871         mac_addr[0] = mac_hi & 0xFF;
 872         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 873         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 874         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 875         mac_addr[4] = mac_lo & 0xFF;
 876         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 877
 878         if (!env_get("eth1addr")) {
 879                 if (is_valid_ethaddr(mac_addr))
 880                         eth_env_set_enetaddr("eth1addr", mac_addr);
 881         }
 882
 883         env_set("ice_mii", prueth_is_mii ? "mii" : "rmii");
 884 #endif
 885
 886         if (!env_get("serial#")) {
 887                 char *board_serial = env_get("board_serial");
 888                 char *ethaddr = env_get("ethaddr");
 889
 890                 if (!board_serial || !strncmp(board_serial, "unknown", 7))
 891                         env_set("serial#", ethaddr);
 892                 else
 893                         env_set("serial#", board_serial);
 894         }
 895
 896         /* Just probe the potentially supported cdce913 device */
 897         uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
 898
 899         return 0;
 900 }
 901 #endif
 902
 903 /* CPSW plat */
 904 #if CONFIG_IS_ENABLED(NET) && !CONFIG_IS_ENABLED(OF_CONTROL)
 905 struct cpsw_slave_data slave_data[] = {
 906         {
 907                 .slave_reg_ofs  = CPSW_SLAVE0_OFFSET,
 908                 .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
 909                 .phy_addr       = 0,
 910         },
 911         {
 912                 .slave_reg_ofs  = CPSW_SLAVE1_OFFSET,
 913                 .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
 914                 .phy_addr       = 1,
 915         },
 916 };
 917
 918 struct cpsw_platform_data am335_eth_data = {
 919         .cpsw_base              = CPSW_BASE,
 920         .version                = CPSW_CTRL_VERSION_2,
 921         .bd_ram_ofs             = CPSW_BD_OFFSET,
 922         .ale_reg_ofs            = CPSW_ALE_OFFSET,
 923         .cpdma_reg_ofs          = CPSW_CPDMA_OFFSET,
 924         .mdio_div               = CPSW_MDIO_DIV,
 925         .host_port_reg_ofs      = CPSW_HOST_PORT_OFFSET,
 926         .channels               = 8,
 927         .slaves                 = 2,
 928         .slave_data             = slave_data,
 929         .ale_entries            = 1024,
 930         .mac_control            = 0x20,
 931         .active_slave           = 0,
 932         .mdio_base              = 0x4a101000,
 933         .gmii_sel               = 0x44e10650,
 934         .phy_sel_compat         = "ti,am3352-cpsw-phy-sel",
 935         .syscon_addr            = 0x44e10630,
 936         .macid_sel_compat       = "cpsw,am33xx",
 937 };
 938
 939 struct eth_pdata cpsw_pdata = {
 940         .iobase = 0x4a100000,
 941         .phy_interface = 0,
 942         .priv_pdata = &am335_eth_data,
 943 };
 944
 945 U_BOOT_DRVINFO(am335x_eth) = {
 946         .name = "eth_cpsw",
 947         .plat = &cpsw_pdata,
 948 };
 949 #endif
 950
 951 #ifdef CONFIG_SPL_LOAD_FIT
 952 int board_fit_config_name_match(const char *name)
 953 {
 954         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
 955                 return 0;
 956         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
 957                 return 0;
 958         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
 959                 return 0;
 960         else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
 961                 return 0;
 962         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
 963                 return 0;
 964         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
 965                 return 0;
 966         else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
 967                 return 0;
 968         else if (board_is_bben()) {
 969                 char subtype_id = board_ti_get_config()[1];
 970
 971                 if (subtype_id == 'L') {
 972                         if (!strcmp(name, "am335x-sancloud-bbe-lite"))
 973                                 return 0;
 974                 } else if (subtype_id == 'I') {
 975                         if (!strcmp(name, "am335x-sancloud-bbe-extended-wifi"))
 976                                 return 0;
 977                 } else if (!strcmp(name, "am335x-sancloud-bbe")) {
 978                         return 0;
 979                 }
 980         }
 981         return -1;
 982 }
 983 #endif
 984
 985 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 986 static const struct omap_hsmmc_plat am335x_mmc0_plat = {
 987         .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
 988         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
 989         .cfg.f_min = 400000,
 990         .cfg.f_max = 52000000,
 991         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 992         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 993 };
 994
 995 U_BOOT_DRVINFO(am335x_mmc0) = {
 996         .name = "omap_hsmmc",
 997         .plat = &am335x_mmc0_plat,
 998 };
 999
1000 static const struct omap_hsmmc_plat am335x_mmc1_plat = {
1001         .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
1002         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
1003         .cfg.f_min = 400000,
1004         .cfg.f_max = 52000000,
1005         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
1006         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
1007 };
1008
1009 U_BOOT_DRVINFO(am335x_mmc1) = {
1010         .name = "omap_hsmmc",
1011         .plat = &am335x_mmc1_plat,
1012 };
1013 #endif