1 // SPDX-License-Identifier: GPL-2.0+
5 * Board functions for TI AM335X based boards
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/hardware.h>
22 #include <asm/arch/omap.h>
23 #include <asm/arch/ddr_defs.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/clk_synthesizer.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/mmc_host_def.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/mem.h>
30 #include <asm/global_data.h>
34 #include <asm/omap_common.h>
35 #include <asm/omap_sec_common.h>
36 #include <asm/omap_mmc.h>
40 #include <linux/bitops.h>
41 #include <linux/delay.h>
42 #include <power/tps65217.h>
43 #include <power/tps65910.h>
44 #include <env_internal.h>
46 #include "../common/board_detect.h"
49 DECLARE_GLOBAL_DATA_PTR;
51 /* GPIO that controls power to DDR on EVM-SK */
52 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
53 #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
54 #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
55 #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
56 #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
57 #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
58 #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
59 #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
60 #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
62 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
64 #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
65 #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
67 #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
68 #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
70 #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
71 #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
74 * Read header information from EEPROM into global structure.
76 #ifdef CONFIG_TI_I2C_BOARD_DETECT
77 void do_board_detect(void)
79 enable_i2c0_pin_mux();
81 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
83 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
84 CONFIG_EEPROM_CHIP_ADDRESS))
85 printf("ti_i2c_eeprom_init failed\n");
89 #ifndef CONFIG_DM_SERIAL
90 struct serial_device *default_serial_console(void)
93 return &eserial4_device;
95 return &eserial1_device;
99 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
100 static const struct ddr_data ddr2_data = {
101 .datardsratio0 = MT47H128M16RT25E_RD_DQS,
102 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
103 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
106 static const struct cmd_control ddr2_cmd_ctrl_data = {
107 .cmd0csratio = MT47H128M16RT25E_RATIO,
109 .cmd1csratio = MT47H128M16RT25E_RATIO,
111 .cmd2csratio = MT47H128M16RT25E_RATIO,
114 static const struct emif_regs ddr2_emif_reg_data = {
115 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
116 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
117 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
118 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
119 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
120 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
123 static const struct emif_regs ddr2_evm_emif_reg_data = {
124 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
125 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
126 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
127 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
128 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
129 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
130 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
133 static const struct ddr_data ddr3_data = {
134 .datardsratio0 = MT41J128MJT125_RD_DQS,
135 .datawdsratio0 = MT41J128MJT125_WR_DQS,
136 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
137 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
140 static const struct ddr_data ddr3_beagleblack_data = {
141 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
142 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
143 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
144 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
147 static const struct ddr_data ddr3_evm_data = {
148 .datardsratio0 = MT41J512M8RH125_RD_DQS,
149 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
150 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
151 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
154 static const struct ddr_data ddr3_icev2_data = {
155 .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
156 .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
157 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
158 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
161 static const struct cmd_control ddr3_cmd_ctrl_data = {
162 .cmd0csratio = MT41J128MJT125_RATIO,
163 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
165 .cmd1csratio = MT41J128MJT125_RATIO,
166 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
168 .cmd2csratio = MT41J128MJT125_RATIO,
169 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
172 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
173 .cmd0csratio = MT41K256M16HA125E_RATIO,
174 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
176 .cmd1csratio = MT41K256M16HA125E_RATIO,
177 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
179 .cmd2csratio = MT41K256M16HA125E_RATIO,
180 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
183 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
184 .cmd0csratio = MT41J512M8RH125_RATIO,
185 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
187 .cmd1csratio = MT41J512M8RH125_RATIO,
188 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
190 .cmd2csratio = MT41J512M8RH125_RATIO,
191 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
194 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
195 .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
196 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
198 .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
199 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
201 .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
202 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
205 static struct emif_regs ddr3_emif_reg_data = {
206 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
207 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
208 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
209 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
210 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
211 .zq_config = MT41J128MJT125_ZQ_CFG,
212 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
216 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
217 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
218 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
219 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
220 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
221 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
222 .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
223 .zq_config = MT41K256M16HA125E_ZQ_CFG,
224 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
227 static struct emif_regs ddr3_evm_emif_reg_data = {
228 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
229 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
230 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
231 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
232 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
233 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
234 .zq_config = MT41J512M8RH125_ZQ_CFG,
235 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
239 static struct emif_regs ddr3_icev2_emif_reg_data = {
240 .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
241 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
242 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
243 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
244 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
245 .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
246 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
250 #ifdef CONFIG_SPL_OS_BOOT
251 int spl_start_uboot(void)
253 #ifdef CONFIG_SPL_SERIAL_SUPPORT
254 /* break into full u-boot on 'c' */
255 if (serial_tstc() && serial_getc() == 'c')
259 #ifdef CONFIG_SPL_ENV_SUPPORT
262 if (env_get_yesno("boot_os") != 1)
270 const struct dpll_params *get_dpll_ddr_params(void)
272 int ind = get_sys_clk_index();
274 if (board_is_evm_sk())
275 return &dpll_ddr3_303MHz[ind];
276 else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
277 return &dpll_ddr3_400MHz[ind];
278 else if (board_is_evm_15_or_later())
279 return &dpll_ddr3_303MHz[ind];
281 return &dpll_ddr2_266MHz[ind];
284 static u8 bone_not_connected_to_ac_power(void)
286 if (board_is_bone()) {
287 uchar pmic_status_reg;
288 if (tps65217_reg_read(TPS65217_STATUS,
291 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
292 puts("No AC power, switching to default OPP\n");
299 const struct dpll_params *get_dpll_mpu_params(void)
301 int ind = get_sys_clk_index();
302 int freq = am335x_get_efuse_mpu_max_freq(cdev);
304 if (bone_not_connected_to_ac_power())
307 if (board_is_pb() || board_is_bone_lt())
308 freq = MPUPLL_M_1000;
312 return &dpll_mpu_opp[ind][5];
314 return &dpll_mpu_opp[ind][4];
316 return &dpll_mpu_opp[ind][3];
318 return &dpll_mpu_opp[ind][2];
320 return &dpll_mpu_opp100;
322 return &dpll_mpu_opp[ind][0];
325 return &dpll_mpu_opp[ind][0];
328 static void scale_vcores_bone(int freq)
330 int usb_cur_lim, mpu_vdd;
333 * Only perform PMIC configurations if board rev > A1
334 * on Beaglebone White
336 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
339 #ifndef CONFIG_DM_I2C
340 if (i2c_probe(TPS65217_CHIP_PM))
343 if (power_tps65217_init(0))
349 * On Beaglebone White we need to ensure we have AC power
350 * before increasing the frequency.
352 if (bone_not_connected_to_ac_power())
356 * Override what we have detected since we know if we have
357 * a Beaglebone Black it supports 1GHz.
359 if (board_is_pb() || board_is_bone_lt())
360 freq = MPUPLL_M_1000;
364 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
365 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
368 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
369 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
372 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
373 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
379 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
380 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
384 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
387 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
388 puts("tps65217_reg_write failure\n");
390 /* Set DCDC3 (CORE) voltage to 1.10V */
391 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
392 TPS65217_DCDC_VOLT_SEL_1100MV)) {
393 puts("tps65217_voltage_update failure\n");
397 /* Set DCDC2 (MPU) voltage */
398 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
399 puts("tps65217_voltage_update failure\n");
404 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
405 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
407 if (board_is_bone()) {
408 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
410 TPS65217_LDO_VOLTAGE_OUT_3_3,
412 puts("tps65217_reg_write failure\n");
414 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
416 TPS65217_LDO_VOLTAGE_OUT_1_8,
418 puts("tps65217_reg_write failure\n");
421 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
423 TPS65217_LDO_VOLTAGE_OUT_3_3,
425 puts("tps65217_reg_write failure\n");
428 void scale_vcores_generic(int freq)
430 int sil_rev, mpu_vdd;
433 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
434 * MPU frequencies we support we use a CORE voltage of
435 * 1.10V. For MPU voltage we need to switch based on
436 * the frequency we are running at.
438 #ifndef CONFIG_DM_I2C
439 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
442 if (power_tps65910_init(0))
446 * Depending on MPU clock and PG we will need a different
447 * VDD to drive at that speed.
449 sil_rev = readl(&cdev->deviceid) >> 28;
450 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
452 /* Tell the TPS65910 to use i2c */
453 tps65910_set_i2c_control();
455 /* First update MPU voltage. */
456 if (tps65910_voltage_update(MPU, mpu_vdd))
459 /* Second, update the CORE voltage. */
460 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
465 void gpi2c_init(void)
467 /* When needed to be invoked prior to BSS initialization */
468 static bool first_time = true;
471 enable_i2c0_pin_mux();
472 #ifndef CONFIG_DM_I2C
473 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
474 CONFIG_SYS_OMAP24_I2C_SLAVE);
480 void scale_vcores(void)
485 freq = am335x_get_efuse_mpu_max_freq(cdev);
487 if (board_is_beaglebonex())
488 scale_vcores_bone(freq);
490 scale_vcores_generic(freq);
493 void set_uart_mux_conf(void)
495 #if CONFIG_CONS_INDEX == 1
496 enable_uart0_pin_mux();
497 #elif CONFIG_CONS_INDEX == 2
498 enable_uart1_pin_mux();
499 #elif CONFIG_CONS_INDEX == 3
500 enable_uart2_pin_mux();
501 #elif CONFIG_CONS_INDEX == 4
502 enable_uart3_pin_mux();
503 #elif CONFIG_CONS_INDEX == 5
504 enable_uart4_pin_mux();
505 #elif CONFIG_CONS_INDEX == 6
506 enable_uart5_pin_mux();
510 void set_mux_conf_regs(void)
512 enable_board_pin_mux();
515 const struct ctrl_ioregs ioregs_evmsk = {
516 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
517 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
518 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
519 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
520 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
523 const struct ctrl_ioregs ioregs_bonelt = {
524 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
525 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
526 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
527 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
528 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
531 const struct ctrl_ioregs ioregs_evm15 = {
532 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
533 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
534 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
535 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
536 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
539 const struct ctrl_ioregs ioregs = {
540 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
541 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
542 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
543 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
544 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
547 void sdram_init(void)
549 if (board_is_evm_sk()) {
551 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
552 * This is safe enough to do on older revs.
554 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
555 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
558 if (board_is_icev2()) {
559 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
560 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
563 if (board_is_evm_sk())
564 config_ddr(303, &ioregs_evmsk, &ddr3_data,
565 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
566 else if (board_is_pb() || board_is_bone_lt())
567 config_ddr(400, &ioregs_bonelt,
568 &ddr3_beagleblack_data,
569 &ddr3_beagleblack_cmd_ctrl_data,
570 &ddr3_beagleblack_emif_reg_data, 0);
571 else if (board_is_evm_15_or_later())
572 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
573 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
574 else if (board_is_icev2())
575 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
576 &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
578 else if (board_is_gp_evm())
579 config_ddr(266, &ioregs, &ddr2_data,
580 &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
582 config_ddr(266, &ioregs, &ddr2_data,
583 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
587 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
588 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
589 static void request_and_set_gpio(int gpio, char *name, int val)
593 ret = gpio_request(gpio, name);
595 printf("%s: Unable to request %s\n", __func__, name);
599 ret = gpio_direction_output(gpio, 0);
601 printf("%s: Unable to set %s as output\n", __func__, name);
605 gpio_set_value(gpio, val);
613 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
614 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
617 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
618 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
619 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
620 * give 50MHz output for Eth0 and 1.
622 static struct clk_synth cdce913_data = {
631 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
632 defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
634 #define MAX_CPSW_SLAVES 2
636 /* At the moment, we do not want to stop booting for any failures here */
637 int ft_board_setup(void *fdt, struct bd_info *bd)
639 const char *slave_path, *enet_name;
640 int enetnode, slavenode, phynode;
641 struct udevice *ethdev;
647 /* phy address fixup needed only on beagle bone family */
648 if (!board_is_beaglebonex())
651 for (i = 0; i < MAX_CPSW_SLAVES; i++) {
652 sprintf(alias, "ethernet%d", i);
654 slave_path = fdt_get_alias(fdt, alias);
658 slavenode = fdt_path_offset(fdt, slave_path);
662 enetnode = fdt_parent_offset(fdt, slavenode);
663 enet_name = fdt_get_name(fdt, enetnode, NULL);
665 ethdev = eth_get_dev_by_name(enet_name);
669 phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
671 /* check for phy_id as well as phy-handle properties */
672 ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
675 if (phy_id[1] != phy_addr) {
676 printf("fixing up phy_id for %s, old: %d, new: %d\n",
677 alias, phy_id[1], phy_addr);
679 phy_id[0] = cpu_to_fdt32(phy_id[0]);
680 phy_id[1] = cpu_to_fdt32(phy_addr);
681 do_fixup_by_path(fdt, slave_path, "phy_id",
682 phy_id, sizeof(phy_id), 0);
685 phynode = fdtdec_lookup_phandle(fdt, slavenode,
690 ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
694 if (ret != phy_addr) {
695 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
696 alias, ret, phy_addr);
698 fdt_setprop_u32(fdt, phynode, "reg",
699 cpu_to_fdt32(phy_addr));
710 * Basic board specific setup. Pinmux has been handled already.
714 #if defined(CONFIG_HW_WATCHDOG)
718 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
719 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
723 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
724 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
725 if (board_is_icev2()) {
729 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
730 /* Make J19 status available on GPIO1_26 */
731 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
733 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
735 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
736 * jumpers near the port. Read the jumper value and set
737 * the pinmux, external mux and PHY clock accordingly.
738 * As jumper line is overridden by PHY RX_DV pin immediately
739 * after bootstrap (power-up/reset), we need to sample
740 * it during PHY reset using GPIO rising edge detection.
742 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
743 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
744 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
745 writel(reg, GPIO0_RISINGDETECT);
746 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
747 writel(reg, GPIO1_RISINGDETECT);
748 /* Reset PHYs to capture the Jumper setting */
749 gpio_set_value(GPIO_PHY_RESET, 0);
750 udelay(2); /* PHY datasheet states 1uS min. */
751 gpio_set_value(GPIO_PHY_RESET, 1);
753 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
755 writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
757 printf("ETH0, CPSW\n");
760 printf("ETH0, PRU\n");
761 cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
764 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
766 writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
768 printf("ETH1, CPSW\n");
769 gpio_set_value(GPIO_MUX_MII_CTRL, 1);
772 printf("ETH1, PRU\n");
773 cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
776 /* disable rising edge IRQs */
777 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
778 writel(reg, GPIO0_RISINGDETECT);
779 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
780 writel(reg, GPIO1_RISINGDETECT);
782 rv = setup_clock_synthesizer(&cdce913_data);
784 printf("Clock synthesizer setup failed %d\n", rv);
789 gpio_set_value(GPIO_PHY_RESET, 0);
790 udelay(2); /* PHY datasheet states 1uS min. */
791 gpio_set_value(GPIO_PHY_RESET, 1);
798 #ifdef CONFIG_BOARD_LATE_INIT
799 int board_late_init(void)
802 #if !defined(CONFIG_SPL_BUILD)
804 uint32_t mac_hi, mac_lo;
807 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
810 if (board_is_bone_lt()) {
811 /* BeagleBoard.org BeagleBone Black Wireless: */
812 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
815 /* SeeedStudio BeagleBone Green Wireless */
816 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
819 /* BeagleBoard.org BeagleBone Blue */
820 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
829 set_board_info_env(name);
832 * Default FIT boot on HS devices. Non FIT images are not allowed
835 if (get_device_type() == HS_DEVICE)
836 env_set("boot_fit", "1");
839 #if !defined(CONFIG_SPL_BUILD)
840 /* try reading mac address from efuse */
841 mac_lo = readl(&cdev->macid0l);
842 mac_hi = readl(&cdev->macid0h);
843 mac_addr[0] = mac_hi & 0xFF;
844 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
845 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
846 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
847 mac_addr[4] = mac_lo & 0xFF;
848 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
850 if (!env_get("ethaddr")) {
851 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
853 if (is_valid_ethaddr(mac_addr))
854 eth_env_set_enetaddr("ethaddr", mac_addr);
857 mac_lo = readl(&cdev->macid1l);
858 mac_hi = readl(&cdev->macid1h);
859 mac_addr[0] = mac_hi & 0xFF;
860 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
861 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
862 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
863 mac_addr[4] = mac_lo & 0xFF;
864 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
866 if (!env_get("eth1addr")) {
867 if (is_valid_ethaddr(mac_addr))
868 eth_env_set_enetaddr("eth1addr", mac_addr);
872 if (!env_get("serial#")) {
873 char *board_serial = env_get("board_serial");
874 char *ethaddr = env_get("ethaddr");
876 if (!board_serial || !strncmp(board_serial, "unknown", 7))
877 env_set("serial#", ethaddr);
879 env_set("serial#", board_serial);
882 /* Just probe the potentially supported cdce913 device */
883 uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
890 #if !CONFIG_IS_ENABLED(OF_CONTROL)
891 struct cpsw_slave_data slave_data[] = {
893 .slave_reg_ofs = CPSW_SLAVE0_OFFSET,
894 .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
898 .slave_reg_ofs = CPSW_SLAVE1_OFFSET,
899 .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
904 struct cpsw_platform_data am335_eth_data = {
905 .cpsw_base = CPSW_BASE,
906 .version = CPSW_CTRL_VERSION_2,
907 .bd_ram_ofs = CPSW_BD_OFFSET,
908 .ale_reg_ofs = CPSW_ALE_OFFSET,
909 .cpdma_reg_ofs = CPSW_CPDMA_OFFSET,
910 .mdio_div = CPSW_MDIO_DIV,
911 .host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
914 .slave_data = slave_data,
918 .mdio_base = 0x4a101000,
919 .gmii_sel = 0x44e10650,
920 .phy_sel_compat = "ti,am3352-cpsw-phy-sel",
921 .syscon_addr = 0x44e10630,
922 .macid_sel_compat = "cpsw,am33xx",
925 struct eth_pdata cpsw_pdata = {
926 .iobase = 0x4a100000,
928 .priv_pdata = &am335_eth_data,
931 U_BOOT_DRVINFO(am335x_eth) = {
937 #ifdef CONFIG_SPL_LOAD_FIT
938 int board_fit_config_name_match(const char *name)
940 if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
942 else if (board_is_bone() && !strcmp(name, "am335x-bone"))
944 else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
946 else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
948 else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
950 else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
952 else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
959 #ifdef CONFIG_TI_SECURE_DEVICE
960 void board_fit_image_post_process(void **p_image, size_t *p_size)
962 secure_boot_verify_image(p_image, p_size);
966 #if !CONFIG_IS_ENABLED(OF_CONTROL)
967 static const struct omap_hsmmc_plat am335x_mmc0_plat = {
968 .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
969 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
971 .cfg.f_max = 52000000,
972 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
973 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
976 U_BOOT_DRVINFO(am335x_mmc0) = {
977 .name = "omap_hsmmc",
978 .plat = &am335x_mmc0_plat,
981 static const struct omap_hsmmc_plat am335x_mmc1_plat = {
982 .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
983 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
985 .cfg.f_max = 52000000,
986 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
987 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
990 U_BOOT_DRVINFO(am335x_mmc1) = {
991 .name = "omap_hsmmc",
992 .plat = &am335x_mmc1_plat,