4 * Board functions for TI AM335X based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
29 #include <power/tps65217.h>
30 #include <power/tps65910.h>
31 #include <environment.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 /* GPIO that controls power to DDR on EVM-SK */
38 #define GPIO_DDR_VTT_EN 7
40 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
43 * Read header information from EEPROM into global structure.
45 static int read_eeprom(struct am335x_baseboard_id *header)
47 /* Check if baseboard eeprom is available */
48 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
49 puts("Could not probe the EEPROM; something fundamentally "
50 "wrong on the I2C bus.\n");
54 /* read the eeprom using i2c */
55 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
56 sizeof(struct am335x_baseboard_id))) {
57 puts("Could not read the EEPROM; something fundamentally"
58 " wrong on the I2C bus.\n");
62 if (header->magic != 0xEE3355AA) {
64 * read the eeprom using i2c again,
65 * but use only a 1 byte address
67 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
68 sizeof(struct am335x_baseboard_id))) {
69 puts("Could not read the EEPROM; something "
70 "fundamentally wrong on the I2C bus.\n");
74 if (header->magic != 0xEE3355AA) {
75 printf("Incorrect magic number (0x%x) in EEPROM\n",
84 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
85 static const struct ddr_data ddr2_data = {
86 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
87 (MT47H128M16RT25E_RD_DQS<<20) |
88 (MT47H128M16RT25E_RD_DQS<<10) |
89 (MT47H128M16RT25E_RD_DQS<<0)),
90 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
91 (MT47H128M16RT25E_WR_DQS<<20) |
92 (MT47H128M16RT25E_WR_DQS<<10) |
93 (MT47H128M16RT25E_WR_DQS<<0)),
94 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
95 (MT47H128M16RT25E_PHY_WRLVL<<20) |
96 (MT47H128M16RT25E_PHY_WRLVL<<10) |
97 (MT47H128M16RT25E_PHY_WRLVL<<0)),
98 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
99 (MT47H128M16RT25E_PHY_GATELVL<<20) |
100 (MT47H128M16RT25E_PHY_GATELVL<<10) |
101 (MT47H128M16RT25E_PHY_GATELVL<<0)),
102 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
103 (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
104 (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
105 (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
106 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
107 (MT47H128M16RT25E_PHY_WR_DATA<<20) |
108 (MT47H128M16RT25E_PHY_WR_DATA<<10) |
109 (MT47H128M16RT25E_PHY_WR_DATA<<0)),
112 static const struct cmd_control ddr2_cmd_ctrl_data = {
113 .cmd0csratio = MT47H128M16RT25E_RATIO,
114 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
116 .cmd1csratio = MT47H128M16RT25E_RATIO,
117 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
119 .cmd2csratio = MT47H128M16RT25E_RATIO,
120 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
123 static const struct emif_regs ddr2_emif_reg_data = {
124 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
125 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
126 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
127 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
128 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
129 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
132 static const struct ddr_data ddr3_data = {
133 .datardsratio0 = MT41J128MJT125_RD_DQS,
134 .datawdsratio0 = MT41J128MJT125_WR_DQS,
135 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
136 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
139 static const struct ddr_data ddr3_beagleblack_data = {
140 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
141 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
142 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
143 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
146 static const struct ddr_data ddr3_evm_data = {
147 .datardsratio0 = MT41J512M8RH125_RD_DQS,
148 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
149 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
150 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
153 static const struct cmd_control ddr3_cmd_ctrl_data = {
154 .cmd0csratio = MT41J128MJT125_RATIO,
155 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
157 .cmd1csratio = MT41J128MJT125_RATIO,
158 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
160 .cmd2csratio = MT41J128MJT125_RATIO,
161 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
164 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
165 .cmd0csratio = MT41K256M16HA125E_RATIO,
166 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
168 .cmd1csratio = MT41K256M16HA125E_RATIO,
169 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
171 .cmd2csratio = MT41K256M16HA125E_RATIO,
172 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
175 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
176 .cmd0csratio = MT41J512M8RH125_RATIO,
177 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
179 .cmd1csratio = MT41J512M8RH125_RATIO,
180 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
182 .cmd2csratio = MT41J512M8RH125_RATIO,
183 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
186 static struct emif_regs ddr3_emif_reg_data = {
187 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
188 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
189 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
190 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
191 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
192 .zq_config = MT41J128MJT125_ZQ_CFG,
193 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
197 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
198 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
199 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
200 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
201 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
202 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
203 .zq_config = MT41K256M16HA125E_ZQ_CFG,
204 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
207 static struct emif_regs ddr3_evm_emif_reg_data = {
208 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
209 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
210 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
211 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
212 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
213 .zq_config = MT41J512M8RH125_ZQ_CFG,
214 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
218 #ifdef CONFIG_SPL_OS_BOOT
219 int spl_start_uboot(void)
221 /* break into full u-boot on 'c' */
222 return (serial_tstc() && serial_getc() == 'c');
226 #define OSC (V_OSCK/1000000)
227 const struct dpll_params dpll_ddr = {
228 266, OSC-1, 1, -1, -1, -1, -1};
229 const struct dpll_params dpll_ddr_evm_sk = {
230 303, OSC-1, 1, -1, -1, -1, -1};
231 const struct dpll_params dpll_ddr_bone_black = {
232 400, OSC-1, 1, -1, -1, -1, -1};
234 void am33xx_spl_board_init(void)
236 struct am335x_baseboard_id header;
239 if (read_eeprom(&header) < 0)
240 puts("Could not get board ID.\n");
242 /* Get the frequency */
243 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
245 if (board_is_bone(&header) || board_is_bone_lt(&header)) {
246 /* BeagleBone PMIC Code */
250 * Only perform PMIC configurations if board rev > A1
251 * on Beaglebone White
253 if (board_is_bone(&header) && !strncmp(header.version,
257 if (i2c_probe(TPS65217_CHIP_PM))
261 * On Beaglebone White we need to ensure we have AC power
262 * before increasing the frequency.
264 if (board_is_bone(&header)) {
265 uchar pmic_status_reg;
266 if (tps65217_reg_read(TPS65217_STATUS,
269 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
270 puts("No AC power, disabling frequency switch\n");
276 * Override what we have detected since we know if we have
277 * a Beaglebone Black it supports 1GHz.
279 if (board_is_bone_lt(&header))
280 dpll_mpu_opp100.m = MPUPLL_M_1000;
283 * Increase USB current limit to 1300mA or 1800mA and set
284 * the MPU voltage controller as needed.
286 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
287 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
288 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
290 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
291 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
294 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
297 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
298 puts("tps65217_reg_write failure\n");
300 /* Set DCDC3 (CORE) voltage to 1.125V */
301 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
302 TPS65217_DCDC_VOLT_SEL_1125MV)) {
303 puts("tps65217_voltage_update failure\n");
307 /* Set CORE Frequencies to OPP100 */
308 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
310 /* Set DCDC2 (MPU) voltage */
311 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
312 puts("tps65217_voltage_update failure\n");
317 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
318 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
320 if (board_is_bone(&header)) {
321 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
323 TPS65217_LDO_VOLTAGE_OUT_3_3,
325 puts("tps65217_reg_write failure\n");
327 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
329 TPS65217_LDO_VOLTAGE_OUT_1_8,
331 puts("tps65217_reg_write failure\n");
334 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
336 TPS65217_LDO_VOLTAGE_OUT_3_3,
338 puts("tps65217_reg_write failure\n");
343 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
344 * MPU frequencies we support we use a CORE voltage of
345 * 1.1375V. For MPU voltage we need to switch based on
346 * the frequency we are running at.
348 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
352 * Depending on MPU clock and PG we will need a different
353 * VDD to drive at that speed.
355 sil_rev = readl(&cdev->deviceid) >> 28;
356 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
359 /* Tell the TPS65910 to use i2c */
360 tps65910_set_i2c_control();
362 /* First update MPU voltage. */
363 if (tps65910_voltage_update(MPU, mpu_vdd))
366 /* Second, update the CORE voltage. */
367 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
370 /* Set CORE Frequencies to OPP100 */
371 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
374 /* Set MPU Frequency to what we detected now that voltages are set */
375 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
378 const struct dpll_params *get_dpll_ddr_params(void)
380 struct am335x_baseboard_id header;
382 enable_i2c0_pin_mux();
383 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
384 if (read_eeprom(&header) < 0)
385 puts("Could not get board ID.\n");
387 if (board_is_evm_sk(&header))
388 return &dpll_ddr_evm_sk;
389 else if (board_is_bone_lt(&header))
390 return &dpll_ddr_bone_black;
391 else if (board_is_evm_15_or_later(&header))
392 return &dpll_ddr_evm_sk;
397 void set_uart_mux_conf(void)
399 #ifdef CONFIG_SERIAL1
400 enable_uart0_pin_mux();
401 #endif /* CONFIG_SERIAL1 */
402 #ifdef CONFIG_SERIAL2
403 enable_uart1_pin_mux();
404 #endif /* CONFIG_SERIAL2 */
405 #ifdef CONFIG_SERIAL3
406 enable_uart2_pin_mux();
407 #endif /* CONFIG_SERIAL3 */
408 #ifdef CONFIG_SERIAL4
409 enable_uart3_pin_mux();
410 #endif /* CONFIG_SERIAL4 */
411 #ifdef CONFIG_SERIAL5
412 enable_uart4_pin_mux();
413 #endif /* CONFIG_SERIAL5 */
414 #ifdef CONFIG_SERIAL6
415 enable_uart5_pin_mux();
416 #endif /* CONFIG_SERIAL6 */
419 void set_mux_conf_regs(void)
421 __maybe_unused struct am335x_baseboard_id header;
423 if (read_eeprom(&header) < 0)
424 puts("Could not get board ID.\n");
426 enable_board_pin_mux(&header);
429 const struct ctrl_ioregs ioregs_evmsk = {
430 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
431 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
432 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
433 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
434 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
437 const struct ctrl_ioregs ioregs_bonelt = {
438 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
439 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
440 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
441 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
442 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
445 const struct ctrl_ioregs ioregs_evm15 = {
446 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
447 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
448 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
449 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
450 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
453 const struct ctrl_ioregs ioregs = {
454 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
455 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
456 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
457 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
458 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
461 void sdram_init(void)
463 __maybe_unused struct am335x_baseboard_id header;
465 if (read_eeprom(&header) < 0)
466 puts("Could not get board ID.\n");
468 if (board_is_evm_sk(&header)) {
470 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
471 * This is safe enough to do on older revs.
473 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
474 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
477 if (board_is_evm_sk(&header))
478 config_ddr(303, &ioregs_evmsk, &ddr3_data,
479 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
480 else if (board_is_bone_lt(&header))
481 config_ddr(400, &ioregs_bonelt,
482 &ddr3_beagleblack_data,
483 &ddr3_beagleblack_cmd_ctrl_data,
484 &ddr3_beagleblack_emif_reg_data, 0);
485 else if (board_is_evm_15_or_later(&header))
486 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
487 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
489 config_ddr(266, &ioregs, &ddr2_data,
490 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
495 * Basic board specific setup. Pinmux has been handled already.
499 #if defined(CONFIG_HW_WATCHDOG)
503 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
504 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
510 #ifdef CONFIG_BOARD_LATE_INIT
511 int board_late_init(void)
513 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
514 char safe_string[HDR_NAME_LEN + 1];
515 struct am335x_baseboard_id header;
517 if (read_eeprom(&header) < 0)
518 puts("Could not get board ID.\n");
520 /* Now set variables based on the header. */
521 strncpy(safe_string, (char *)header.name, sizeof(header.name));
522 safe_string[sizeof(header.name)] = 0;
523 setenv("board_name", safe_string);
525 strncpy(safe_string, (char *)header.version, sizeof(header.version));
526 safe_string[sizeof(header.version)] = 0;
527 setenv("board_rev", safe_string);
534 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
535 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
536 static void cpsw_control(int enabled)
538 /* VTP can be added here */
543 static struct cpsw_slave_data cpsw_slaves[] = {
545 .slave_reg_ofs = 0x208,
546 .sliver_reg_ofs = 0xd80,
550 .slave_reg_ofs = 0x308,
551 .sliver_reg_ofs = 0xdc0,
556 static struct cpsw_platform_data cpsw_data = {
557 .mdio_base = CPSW_MDIO_BASE,
558 .cpsw_base = CPSW_BASE,
561 .cpdma_reg_ofs = 0x800,
563 .slave_data = cpsw_slaves,
564 .ale_reg_ofs = 0xd00,
566 .host_port_reg_ofs = 0x108,
567 .hw_stats_reg_ofs = 0x900,
568 .bd_ram_ofs = 0x2000,
569 .mac_control = (1 << 5),
570 .control = cpsw_control,
572 .version = CPSW_CTRL_VERSION_2,
577 * This function will:
578 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
580 * Perform fixups to the PHY present on certain boards. We only need this
582 * - SPL with either CPSW or USB ethernet support
583 * - Full U-Boot, with either CPSW or USB ethernet
584 * Build in only these cases to avoid warnings about unused variables
585 * when we build an SPL that has neither option but full U-Boot will.
587 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
588 && defined(CONFIG_SPL_BUILD)) || \
589 ((defined(CONFIG_DRIVER_TI_CPSW) || \
590 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
591 !defined(CONFIG_SPL_BUILD))
592 int board_eth_init(bd_t *bis)
596 uint32_t mac_hi, mac_lo;
597 __maybe_unused struct am335x_baseboard_id header;
599 /* try reading mac address from efuse */
600 mac_lo = readl(&cdev->macid0l);
601 mac_hi = readl(&cdev->macid0h);
602 mac_addr[0] = mac_hi & 0xFF;
603 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
604 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
605 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
606 mac_addr[4] = mac_lo & 0xFF;
607 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
609 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
610 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
611 if (!getenv("ethaddr")) {
612 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
614 if (is_valid_ether_addr(mac_addr))
615 eth_setenv_enetaddr("ethaddr", mac_addr);
618 #ifdef CONFIG_DRIVER_TI_CPSW
620 mac_lo = readl(&cdev->macid1l);
621 mac_hi = readl(&cdev->macid1h);
622 mac_addr[0] = mac_hi & 0xFF;
623 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
624 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
625 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
626 mac_addr[4] = mac_lo & 0xFF;
627 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
629 if (!getenv("eth1addr")) {
630 if (is_valid_ether_addr(mac_addr))
631 eth_setenv_enetaddr("eth1addr", mac_addr);
634 if (read_eeprom(&header) < 0)
635 puts("Could not get board ID.\n");
637 if (board_is_bone(&header) || board_is_bone_lt(&header) ||
638 board_is_idk(&header)) {
639 writel(MII_MODE_ENABLE, &cdev->miisel);
640 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
641 PHY_INTERFACE_MODE_MII;
643 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
644 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
645 PHY_INTERFACE_MODE_RGMII;
648 rv = cpsw_register(&cpsw_data);
650 printf("Error %d registering CPSW switch\n", rv);
657 * CPSW RGMII Internal Delay Mode is not supported in all PVT
658 * operating points. So we must set the TX clock delay feature
659 * in the AR8051 PHY. Since we only support a single ethernet
660 * device in U-Boot, we only do this for the first instance.
662 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
663 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
664 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
665 #define AR8051_RGMII_TX_CLK_DLY 0x100
667 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
669 devname = miiphy_get_current_dev();
671 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
672 AR8051_DEBUG_RGMII_CLK_DLY_REG);
673 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
674 AR8051_RGMII_TX_CLK_DLY);
677 #if defined(CONFIG_USB_ETHER) && \
678 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
679 if (is_valid_ether_addr(mac_addr))
680 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
682 rv = usb_eth_initialize(bis);
684 printf("Error %d registering USB_ETHER\n", rv);