Merge branch 'master' of git://git.denx.de/u-boot-arm
[platform/kernel/u-boot.git] / board / ti / am335x / board.c
1 /*
2  * board.c
3  *
4  * Board functions for TI AM335X based boards
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #include <common.h>
20 #include <errno.h>
21 #include <spl.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/omap.h>
25 #include <asm/arch/ddr_defs.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mmc_host_def.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/io.h>
31 #include <asm/emif.h>
32 #include <asm/gpio.h>
33 #include <i2c.h>
34 #include <miiphy.h>
35 #include <cpsw.h>
36 #include "board.h"
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
41
42 /* MII mode defines */
43 #define MII_MODE_ENABLE         0x0
44 #define RGMII_MODE_ENABLE       0x3A
45
46 /* GPIO that controls power to DDR on EVM-SK */
47 #define GPIO_DDR_VTT_EN         7
48
49 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
50
51 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
52
53 static inline int board_is_bone(void)
54 {
55         return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
56 }
57
58 static inline int board_is_bone_lt(void)
59 {
60         return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
61 }
62
63 static inline int board_is_evm_sk(void)
64 {
65         return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
66 }
67
68 static inline int board_is_idk(void)
69 {
70         return !strncmp(header.config, "SKU#02", 6);
71 }
72
73 static int __maybe_unused board_is_gp_evm(void)
74 {
75         return !strncmp("A33515BB", header.name, 8);
76 }
77
78 int board_is_evm_15_or_later(void)
79 {
80         return (!strncmp("A33515BB", header.name, 8) &&
81                 strncmp("1.5", header.version, 3) <= 0);
82 }
83
84 /*
85  * Read header information from EEPROM into global structure.
86  */
87 static int read_eeprom(void)
88 {
89         /* Check if baseboard eeprom is available */
90         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
91                 puts("Could not probe the EEPROM; something fundamentally "
92                         "wrong on the I2C bus.\n");
93                 return -ENODEV;
94         }
95
96         /* read the eeprom using i2c */
97         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
98                                                         sizeof(header))) {
99                 puts("Could not read the EEPROM; something fundamentally"
100                         " wrong on the I2C bus.\n");
101                 return -EIO;
102         }
103
104         if (header.magic != 0xEE3355AA) {
105                 /*
106                  * read the eeprom using i2c again,
107                  * but use only a 1 byte address
108                  */
109                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
110                                         (uchar *)&header, sizeof(header))) {
111                         puts("Could not read the EEPROM; something "
112                                 "fundamentally wrong on the I2C bus.\n");
113                         return -EIO;
114                 }
115
116                 if (header.magic != 0xEE3355AA) {
117                         printf("Incorrect magic number (0x%x) in EEPROM\n",
118                                         header.magic);
119                         return -EINVAL;
120                 }
121         }
122
123         return 0;
124 }
125
126 #ifdef CONFIG_SPL_BUILD
127 static const struct ddr_data ddr2_data = {
128         .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
129                           (MT47H128M16RT25E_RD_DQS<<20) |
130                           (MT47H128M16RT25E_RD_DQS<<10) |
131                           (MT47H128M16RT25E_RD_DQS<<0)),
132         .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
133                           (MT47H128M16RT25E_WR_DQS<<20) |
134                           (MT47H128M16RT25E_WR_DQS<<10) |
135                           (MT47H128M16RT25E_WR_DQS<<0)),
136         .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
137                          (MT47H128M16RT25E_PHY_WRLVL<<20) |
138                          (MT47H128M16RT25E_PHY_WRLVL<<10) |
139                          (MT47H128M16RT25E_PHY_WRLVL<<0)),
140         .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
141                          (MT47H128M16RT25E_PHY_GATELVL<<20) |
142                          (MT47H128M16RT25E_PHY_GATELVL<<10) |
143                          (MT47H128M16RT25E_PHY_GATELVL<<0)),
144         .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
145                           (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
146                           (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
147                           (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
148         .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
149                           (MT47H128M16RT25E_PHY_WR_DATA<<20) |
150                           (MT47H128M16RT25E_PHY_WR_DATA<<10) |
151                           (MT47H128M16RT25E_PHY_WR_DATA<<0)),
152         .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
153         .datadldiff0 = PHY_DLL_LOCK_DIFF,
154 };
155
156 static const struct cmd_control ddr2_cmd_ctrl_data = {
157         .cmd0csratio = MT47H128M16RT25E_RATIO,
158         .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
159         .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
160
161         .cmd1csratio = MT47H128M16RT25E_RATIO,
162         .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
163         .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
164
165         .cmd2csratio = MT47H128M16RT25E_RATIO,
166         .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
167         .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
168 };
169
170 static const struct emif_regs ddr2_emif_reg_data = {
171         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
172         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
173         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
174         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
175         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
176         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
177 };
178
179 static const struct ddr_data ddr3_data = {
180         .datardsratio0 = MT41J128MJT125_RD_DQS,
181         .datawdsratio0 = MT41J128MJT125_WR_DQS,
182         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
183         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
184         .datadldiff0 = PHY_DLL_LOCK_DIFF,
185 };
186
187 static const struct ddr_data ddr3_beagleblack_data = {
188         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
189         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
190         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
191         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
192         .datadldiff0 = PHY_DLL_LOCK_DIFF,
193 };
194
195 static const struct ddr_data ddr3_evm_data = {
196         .datardsratio0 = MT41J512M8RH125_RD_DQS,
197         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
198         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
199         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
200         .datadldiff0 = PHY_DLL_LOCK_DIFF,
201 };
202
203 static const struct cmd_control ddr3_cmd_ctrl_data = {
204         .cmd0csratio = MT41J128MJT125_RATIO,
205         .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
206         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
207
208         .cmd1csratio = MT41J128MJT125_RATIO,
209         .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
210         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
211
212         .cmd2csratio = MT41J128MJT125_RATIO,
213         .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
214         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
215 };
216
217 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
218         .cmd0csratio = MT41K256M16HA125E_RATIO,
219         .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
220         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
221
222         .cmd1csratio = MT41K256M16HA125E_RATIO,
223         .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
224         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
225
226         .cmd2csratio = MT41K256M16HA125E_RATIO,
227         .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
228         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
229 };
230
231 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
232         .cmd0csratio = MT41J512M8RH125_RATIO,
233         .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
234         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
235
236         .cmd1csratio = MT41J512M8RH125_RATIO,
237         .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
238         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
239
240         .cmd2csratio = MT41J512M8RH125_RATIO,
241         .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
242         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
243 };
244
245 static struct emif_regs ddr3_emif_reg_data = {
246         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
247         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
248         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
249         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
250         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
251         .zq_config = MT41J128MJT125_ZQ_CFG,
252         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
253                                 PHY_EN_DYN_PWRDN,
254 };
255
256 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
257         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
258         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
259         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
260         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
261         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
262         .zq_config = MT41K256M16HA125E_ZQ_CFG,
263         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
264 };
265
266 static struct emif_regs ddr3_evm_emif_reg_data = {
267         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
268         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
269         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
270         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
271         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
272         .zq_config = MT41J512M8RH125_ZQ_CFG,
273         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
274                                 PHY_EN_DYN_PWRDN,
275 };
276
277 #ifdef CONFIG_SPL_OS_BOOT
278 int spl_start_uboot(void)
279 {
280         /* break into full u-boot on 'c' */
281         return (serial_tstc() && serial_getc() == 'c');
282 }
283 #endif
284
285 #endif
286
287 /*
288  * early system init of muxing and clocks.
289  */
290 void s_init(void)
291 {
292         /*
293          * Save the boot parameters passed from romcode.
294          * We cannot delay the saving further than this,
295          * to prevent overwrites.
296          */
297 #ifdef CONFIG_SPL_BUILD
298         save_omap_boot_params();
299 #endif
300
301         /* WDT1 is already running when the bootloader gets control
302          * Disable it to avoid "random" resets
303          */
304         writel(0xAAAA, &wdtimer->wdtwspr);
305         while (readl(&wdtimer->wdtwwps) != 0x0)
306                 ;
307         writel(0x5555, &wdtimer->wdtwspr);
308         while (readl(&wdtimer->wdtwwps) != 0x0)
309                 ;
310
311 #ifdef CONFIG_SPL_BUILD
312         /* Setup the PLLs and the clocks for the peripherals */
313         pll_init();
314
315         /* Enable RTC32K clock */
316         rtc32k_enable();
317
318 #ifdef CONFIG_SERIAL1
319         enable_uart0_pin_mux();
320 #endif /* CONFIG_SERIAL1 */
321 #ifdef CONFIG_SERIAL2
322         enable_uart1_pin_mux();
323 #endif /* CONFIG_SERIAL2 */
324 #ifdef CONFIG_SERIAL3
325         enable_uart2_pin_mux();
326 #endif /* CONFIG_SERIAL3 */
327 #ifdef CONFIG_SERIAL4
328         enable_uart3_pin_mux();
329 #endif /* CONFIG_SERIAL4 */
330 #ifdef CONFIG_SERIAL5
331         enable_uart4_pin_mux();
332 #endif /* CONFIG_SERIAL5 */
333 #ifdef CONFIG_SERIAL6
334         enable_uart5_pin_mux();
335 #endif /* CONFIG_SERIAL6 */
336
337         uart_soft_reset();
338
339         gd = &gdata;
340
341         preloader_console_init();
342
343         /* Initalize the board header */
344         enable_i2c0_pin_mux();
345         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
346         if (read_eeprom() < 0)
347                 puts("Could not get board ID.\n");
348
349         enable_board_pin_mux(&header);
350         if (board_is_evm_sk()) {
351                 /*
352                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
353                  * This is safe enough to do on older revs.
354                  */
355                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
356                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
357         }
358
359         if (board_is_evm_sk())
360                 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
361                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
362         else if (board_is_bone_lt())
363                 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
364                            &ddr3_beagleblack_data,
365                            &ddr3_beagleblack_cmd_ctrl_data,
366                            &ddr3_beagleblack_emif_reg_data, 0);
367         else if (board_is_evm_15_or_later())
368                 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
369                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
370         else
371                 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
372                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
373 #endif
374 }
375
376 /*
377  * Basic board specific setup.  Pinmux has been handled already.
378  */
379 int board_init(void)
380 {
381         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
382         if (read_eeprom() < 0)
383                 puts("Could not get board ID.\n");
384
385         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
386
387         gpmc_init();
388
389         return 0;
390 }
391
392 #ifdef CONFIG_BOARD_LATE_INIT
393 int board_late_init(void)
394 {
395 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
396         char safe_string[HDR_NAME_LEN + 1];
397
398         /* Now set variables based on the header. */
399         strncpy(safe_string, (char *)header.name, sizeof(header.name));
400         safe_string[sizeof(header.name)] = 0;
401         setenv("board_name", safe_string);
402
403         strncpy(safe_string, (char *)header.version, sizeof(header.version));
404         safe_string[sizeof(header.version)] = 0;
405         setenv("board_rev", safe_string);
406 #endif
407
408         return 0;
409 }
410 #endif
411
412 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
413         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
414 static void cpsw_control(int enabled)
415 {
416         /* VTP can be added here */
417
418         return;
419 }
420
421 static struct cpsw_slave_data cpsw_slaves[] = {
422         {
423                 .slave_reg_ofs  = 0x208,
424                 .sliver_reg_ofs = 0xd80,
425                 .phy_id         = 0,
426         },
427         {
428                 .slave_reg_ofs  = 0x308,
429                 .sliver_reg_ofs = 0xdc0,
430                 .phy_id         = 1,
431         },
432 };
433
434 static struct cpsw_platform_data cpsw_data = {
435         .mdio_base              = CPSW_MDIO_BASE,
436         .cpsw_base              = CPSW_BASE,
437         .mdio_div               = 0xff,
438         .channels               = 8,
439         .cpdma_reg_ofs          = 0x800,
440         .slaves                 = 1,
441         .slave_data             = cpsw_slaves,
442         .ale_reg_ofs            = 0xd00,
443         .ale_entries            = 1024,
444         .host_port_reg_ofs      = 0x108,
445         .hw_stats_reg_ofs       = 0x900,
446         .mac_control            = (1 << 5),
447         .control                = cpsw_control,
448         .host_port_num          = 0,
449         .version                = CPSW_CTRL_VERSION_2,
450 };
451 #endif
452
453 #if defined(CONFIG_DRIVER_TI_CPSW) || \
454         (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
455 int board_eth_init(bd_t *bis)
456 {
457         int rv, n = 0;
458         uint8_t mac_addr[6];
459         uint32_t mac_hi, mac_lo;
460
461         /* try reading mac address from efuse */
462         mac_lo = readl(&cdev->macid0l);
463         mac_hi = readl(&cdev->macid0h);
464         mac_addr[0] = mac_hi & 0xFF;
465         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
466         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
467         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
468         mac_addr[4] = mac_lo & 0xFF;
469         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
470
471 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
472         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
473         if (!getenv("ethaddr")) {
474                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
475
476                 if (is_valid_ether_addr(mac_addr))
477                         eth_setenv_enetaddr("ethaddr", mac_addr);
478         }
479
480 #ifdef CONFIG_DRIVER_TI_CPSW
481         if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
482                 writel(MII_MODE_ENABLE, &cdev->miisel);
483                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
484                                 PHY_INTERFACE_MODE_MII;
485         } else {
486                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
487                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
488                                 PHY_INTERFACE_MODE_RGMII;
489         }
490
491         rv = cpsw_register(&cpsw_data);
492         if (rv < 0)
493                 printf("Error %d registering CPSW switch\n", rv);
494         else
495                 n += rv;
496 #endif
497
498         /*
499          *
500          * CPSW RGMII Internal Delay Mode is not supported in all PVT
501          * operating points.  So we must set the TX clock delay feature
502          * in the AR8051 PHY.  Since we only support a single ethernet
503          * device in U-Boot, we only do this for the first instance.
504          */
505 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
506 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
507 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
508 #define AR8051_RGMII_TX_CLK_DLY         0x100
509
510         if (board_is_evm_sk() || board_is_gp_evm()) {
511                 const char *devname;
512                 devname = miiphy_get_current_dev();
513
514                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
515                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
516                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
517                                 AR8051_RGMII_TX_CLK_DLY);
518         }
519 #endif
520 #if defined(CONFIG_USB_ETHER) && \
521         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
522         if (is_valid_ether_addr(mac_addr))
523                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
524
525         rv = usb_eth_initialize(bis);
526         if (rv < 0)
527                 printf("Error %d registering USB_ETHER\n", rv);
528         else
529                 n += rv;
530 #endif
531         return n;
532 }
533 #endif