am335x: add initial AM335x IDK board support
[platform/kernel/u-boot.git] / board / ti / am335x / board.c
1 /*
2  * board.c
3  *
4  * Board functions for TI AM335X based boards
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #include <common.h>
20 #include <errno.h>
21 #include <spl.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/omap.h>
25 #include <asm/arch/ddr_defs.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mmc_host_def.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/io.h>
31 #include <asm/emif.h>
32 #include <asm/gpio.h>
33 #include <i2c.h>
34 #include <miiphy.h>
35 #include <cpsw.h>
36 #include "board.h"
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
41 #ifdef CONFIG_SPL_BUILD
42 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
43 #endif
44
45 /* MII mode defines */
46 #define MII_MODE_ENABLE         0x0
47 #define RGMII_MODE_ENABLE       0xA
48
49 /* GPIO that controls power to DDR on EVM-SK */
50 #define GPIO_DDR_VTT_EN         7
51
52 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
53
54 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
55
56 static inline int board_is_bone(void)
57 {
58         return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
59 }
60
61 static inline int board_is_bone_lt(void)
62 {
63         return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
64 }
65
66 static inline int board_is_evm_sk(void)
67 {
68         return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
69 }
70
71 static inline int board_is_idk(void)
72 {
73         return !strncmp(header.config, "SKU#02", 6);
74 }
75
76 /*
77  * Read header information from EEPROM into global structure.
78  */
79 static int read_eeprom(void)
80 {
81         /* Check if baseboard eeprom is available */
82         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
83                 puts("Could not probe the EEPROM; something fundamentally "
84                         "wrong on the I2C bus.\n");
85                 return -ENODEV;
86         }
87
88         /* read the eeprom using i2c */
89         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
90                                                         sizeof(header))) {
91                 puts("Could not read the EEPROM; something fundamentally"
92                         " wrong on the I2C bus.\n");
93                 return -EIO;
94         }
95
96         if (header.magic != 0xEE3355AA) {
97                 /*
98                  * read the eeprom using i2c again,
99                  * but use only a 1 byte address
100                  */
101                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
102                                         (uchar *)&header, sizeof(header))) {
103                         puts("Could not read the EEPROM; something "
104                                 "fundamentally wrong on the I2C bus.\n");
105                         return -EIO;
106                 }
107
108                 if (header.magic != 0xEE3355AA) {
109                         printf("Incorrect magic number (0x%x) in EEPROM\n",
110                                         header.magic);
111                         return -EINVAL;
112                 }
113         }
114
115         return 0;
116 }
117
118 /* UART Defines */
119 #ifdef CONFIG_SPL_BUILD
120 #define UART_RESET              (0x1 << 1)
121 #define UART_CLK_RUNNING_MASK   0x1
122 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
123
124 static void rtc32k_enable(void)
125 {
126         struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
127
128         /*
129          * Unlock the RTC's registers.  For more details please see the
130          * RTC_SS section of the TRM.  In order to unlock we need to
131          * write these specific values (keys) in this order.
132          */
133         writel(0x83e70b13, &rtc->kick0r);
134         writel(0x95a4f1e0, &rtc->kick1r);
135
136         /* Enable the RTC 32K OSC by setting bits 3 and 6. */
137         writel((1 << 3) | (1 << 6), &rtc->osc);
138 }
139
140 static const struct ddr_data ddr2_data = {
141         .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
142                           (MT47H128M16RT25E_RD_DQS<<20) |
143                           (MT47H128M16RT25E_RD_DQS<<10) |
144                           (MT47H128M16RT25E_RD_DQS<<0)),
145         .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
146                           (MT47H128M16RT25E_WR_DQS<<20) |
147                           (MT47H128M16RT25E_WR_DQS<<10) |
148                           (MT47H128M16RT25E_WR_DQS<<0)),
149         .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
150                          (MT47H128M16RT25E_PHY_WRLVL<<20) |
151                          (MT47H128M16RT25E_PHY_WRLVL<<10) |
152                          (MT47H128M16RT25E_PHY_WRLVL<<0)),
153         .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
154                          (MT47H128M16RT25E_PHY_GATELVL<<20) |
155                          (MT47H128M16RT25E_PHY_GATELVL<<10) |
156                          (MT47H128M16RT25E_PHY_GATELVL<<0)),
157         .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
158                           (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
159                           (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
160                           (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
161         .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
162                           (MT47H128M16RT25E_PHY_WR_DATA<<20) |
163                           (MT47H128M16RT25E_PHY_WR_DATA<<10) |
164                           (MT47H128M16RT25E_PHY_WR_DATA<<0)),
165         .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
166         .datadldiff0 = PHY_DLL_LOCK_DIFF,
167 };
168
169 static const struct cmd_control ddr2_cmd_ctrl_data = {
170         .cmd0csratio = MT47H128M16RT25E_RATIO,
171         .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
172         .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
173
174         .cmd1csratio = MT47H128M16RT25E_RATIO,
175         .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
176         .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
177
178         .cmd2csratio = MT47H128M16RT25E_RATIO,
179         .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
180         .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
181 };
182
183 static const struct emif_regs ddr2_emif_reg_data = {
184         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
185         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
186         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
187         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
188         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
189         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
190 };
191
192 static const struct ddr_data ddr3_data = {
193         .datardsratio0 = MT41J128MJT125_RD_DQS,
194         .datawdsratio0 = MT41J128MJT125_WR_DQS,
195         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
196         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
197         .datadldiff0 = PHY_DLL_LOCK_DIFF,
198 };
199
200 static const struct cmd_control ddr3_cmd_ctrl_data = {
201         .cmd0csratio = MT41J128MJT125_RATIO,
202         .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
203         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
204
205         .cmd1csratio = MT41J128MJT125_RATIO,
206         .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
207         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
208
209         .cmd2csratio = MT41J128MJT125_RATIO,
210         .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
211         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
212 };
213
214 static struct emif_regs ddr3_emif_reg_data = {
215         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
216         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
217         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
218         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
219         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
220         .zq_config = MT41J128MJT125_ZQ_CFG,
221         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
222 };
223 #endif
224
225 /*
226  * early system init of muxing and clocks.
227  */
228 void s_init(void)
229 {
230         /* WDT1 is already running when the bootloader gets control
231          * Disable it to avoid "random" resets
232          */
233         writel(0xAAAA, &wdtimer->wdtwspr);
234         while (readl(&wdtimer->wdtwwps) != 0x0)
235                 ;
236         writel(0x5555, &wdtimer->wdtwspr);
237         while (readl(&wdtimer->wdtwwps) != 0x0)
238                 ;
239
240 #ifdef CONFIG_SPL_BUILD
241         /* Setup the PLLs and the clocks for the peripherals */
242         pll_init();
243
244         /* Enable RTC32K clock */
245         rtc32k_enable();
246
247         /* UART softreset */
248         u32 regVal;
249
250 #ifdef CONFIG_SERIAL1
251         enable_uart0_pin_mux();
252 #endif /* CONFIG_SERIAL1 */
253 #ifdef CONFIG_SERIAL2
254         enable_uart1_pin_mux();
255 #endif /* CONFIG_SERIAL2 */
256 #ifdef CONFIG_SERIAL3
257         enable_uart2_pin_mux();
258 #endif /* CONFIG_SERIAL3 */
259 #ifdef CONFIG_SERIAL4
260         enable_uart3_pin_mux();
261 #endif /* CONFIG_SERIAL4 */
262 #ifdef CONFIG_SERIAL5
263         enable_uart4_pin_mux();
264 #endif /* CONFIG_SERIAL5 */
265 #ifdef CONFIG_SERIAL6
266         enable_uart5_pin_mux();
267 #endif /* CONFIG_SERIAL6 */
268
269         regVal = readl(&uart_base->uartsyscfg);
270         regVal |= UART_RESET;
271         writel(regVal, &uart_base->uartsyscfg);
272         while ((readl(&uart_base->uartsyssts) &
273                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
274                 ;
275
276         /* Disable smart idle */
277         regVal = readl(&uart_base->uartsyscfg);
278         regVal |= UART_SMART_IDLE_EN;
279         writel(regVal, &uart_base->uartsyscfg);
280
281         gd = &gdata;
282
283         preloader_console_init();
284
285         /* Initalize the board header */
286         enable_i2c0_pin_mux();
287         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
288         if (read_eeprom() < 0)
289                 puts("Could not get board ID.\n");
290
291         enable_board_pin_mux(&header);
292         if (board_is_evm_sk()) {
293                 /*
294                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
295                  * This is safe enough to do on older revs.
296                  */
297                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
298                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
299         }
300
301         if (board_is_evm_sk() || board_is_bone_lt())
302                 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
303                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
304         else
305                 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
306                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
307 #endif
308 }
309
310 /*
311  * Basic board specific setup.  Pinmux has been handled already.
312  */
313 int board_init(void)
314 {
315         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
316         if (read_eeprom() < 0)
317                 puts("Could not get board ID.\n");
318
319         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
320
321         return 0;
322 }
323
324 #ifdef CONFIG_DRIVER_TI_CPSW
325 static void cpsw_control(int enabled)
326 {
327         /* VTP can be added here */
328
329         return;
330 }
331
332 static struct cpsw_slave_data cpsw_slaves[] = {
333         {
334                 .slave_reg_ofs  = 0x208,
335                 .sliver_reg_ofs = 0xd80,
336                 .phy_id         = 0,
337         },
338         {
339                 .slave_reg_ofs  = 0x308,
340                 .sliver_reg_ofs = 0xdc0,
341                 .phy_id         = 1,
342         },
343 };
344
345 static struct cpsw_platform_data cpsw_data = {
346         .mdio_base              = AM335X_CPSW_MDIO_BASE,
347         .cpsw_base              = AM335X_CPSW_BASE,
348         .mdio_div               = 0xff,
349         .channels               = 8,
350         .cpdma_reg_ofs          = 0x800,
351         .slaves                 = 1,
352         .slave_data             = cpsw_slaves,
353         .ale_reg_ofs            = 0xd00,
354         .ale_entries            = 1024,
355         .host_port_reg_ofs      = 0x108,
356         .hw_stats_reg_ofs       = 0x900,
357         .mac_control            = (1 << 5),
358         .control                = cpsw_control,
359         .host_port_num          = 0,
360         .version                = CPSW_CTRL_VERSION_2,
361 };
362
363 int board_eth_init(bd_t *bis)
364 {
365         uint8_t mac_addr[6];
366         uint32_t mac_hi, mac_lo;
367
368         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
369                 debug("<ethaddr> not set. Reading from E-fuse\n");
370                 /* try reading mac address from efuse */
371                 mac_lo = readl(&cdev->macid0l);
372                 mac_hi = readl(&cdev->macid0h);
373                 mac_addr[0] = mac_hi & 0xFF;
374                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
375                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
376                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
377                 mac_addr[4] = mac_lo & 0xFF;
378                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
379
380                 if (is_valid_ether_addr(mac_addr))
381                         eth_setenv_enetaddr("ethaddr", mac_addr);
382                 else
383                         return -1;
384         }
385
386         if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
387                 writel(MII_MODE_ENABLE, &cdev->miisel);
388                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
389                                 PHY_INTERFACE_MODE_MII;
390         } else {
391                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
392                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
393                                 PHY_INTERFACE_MODE_RGMII;
394         }
395
396         return cpsw_register(&cpsw_data);
397 }
398 #endif