board/technologic/ts4800/ts4800.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2015 Savoir-faire Linux Inc.
   4  *
   5  * Derived from MX51EVK code by
   6  *   Freescale Semiconductor, Inc.
   7  */
   8
   9 #include <common.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <net.h>
  13 #include <asm/global_data.h>
  14 #include <asm/io.h>
  15 #include <asm/gpio.h>
  16 #include <asm/arch/imx-regs.h>
  17 #include <asm/arch/iomux-mx51.h>
  18 #include <env.h>
  19 #include <linux/delay.h>
  20 #include <linux/errno.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/crm_regs.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/mach-imx/mx5_video.h>
  25 #include <mmc.h>
  26 #include <input.h>
  27 #include <fsl_esdhc_imx.h>
  28 #include <mc13892.h>
  29
  30 #include <malloc.h>
  31 #include <netdev.h>
  32 #include <phy.h>
  33 #include "ts4800.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #ifdef CONFIG_FSL_ESDHC_IMX
  38 struct fsl_esdhc_cfg esdhc_cfg[2] = {
  39         {MMC_SDHC1_BASE_ADDR},
  40         {MMC_SDHC2_BASE_ADDR},
  41 };
  42 #endif
  43
  44 int dram_init(void)
  45 {
  46         /* dram_init must store complete ramsize in gd->ram_size */
  47         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  48                                 PHYS_SDRAM_1_SIZE);
  49         return 0;
  50 }
  51
  52 u32 get_board_rev(void)
  53 {
  54         u32 rev = get_cpu_rev();
  55         if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
  56                 rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
  57         return rev;
  58 }
  59
  60 #define UART_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
  61
  62 static void setup_iomux_uart(void)
  63 {
  64         static const iomux_v3_cfg_t uart_pads[] = {
  65                 MX51_PAD_UART1_RXD__UART1_RXD,
  66                 MX51_PAD_UART1_TXD__UART1_TXD,
  67                 NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
  68                 NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
  69         };
  70
  71         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  72 }
  73
  74 static void setup_iomux_fec(void)
  75 {
  76         static const iomux_v3_cfg_t fec_pads[] = {
  77                 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO,
  78                                 PAD_CTL_HYS |
  79                                 PAD_CTL_PUS_22K_UP |
  80                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  81                 MX51_PAD_EIM_EB3__FEC_RDATA1,
  82                 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, PAD_CTL_HYS),
  83                 MX51_PAD_EIM_CS3__FEC_RDATA3,
  84                 MX51_PAD_NANDF_CS2__FEC_TX_ER,
  85                 MX51_PAD_EIM_CS5__FEC_CRS,
  86                 MX51_PAD_EIM_CS4__FEC_RX_ER,
  87                 /* PAD used on TS4800 */
  88                 MX51_PAD_DI2_PIN2__FEC_MDC,
  89                 MX51_PAD_DISP2_DAT14__FEC_RDAT0,
  90                 MX51_PAD_DISP2_DAT10__FEC_COL,
  91                 MX51_PAD_DISP2_DAT11__FEC_RXCLK,
  92                 MX51_PAD_DISP2_DAT15__FEC_TDAT0,
  93                 MX51_PAD_DISP2_DAT6__FEC_TDAT1,
  94                 MX51_PAD_DISP2_DAT7__FEC_TDAT2,
  95                 MX51_PAD_DISP2_DAT8__FEC_TDAT3,
  96                 MX51_PAD_DISP2_DAT9__FEC_TX_EN,
  97                 MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
  98                 MX51_PAD_DISP2_DAT12__FEC_RX_DV,
  99         };
 100
 101         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 102 }
 103
 104 #ifdef CONFIG_FSL_ESDHC_IMX
 105 int board_mmc_getcd(struct mmc *mmc)
 106 {
 107         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 108         int ret;
 109
 110         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
 111                                                 NO_PAD_CTRL));
 112         gpio_direction_input(IMX_GPIO_NR(1, 0));
 113         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
 114                                                 NO_PAD_CTRL));
 115         gpio_direction_input(IMX_GPIO_NR(1, 6));
 116
 117         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 118                 ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
 119         else
 120                 ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
 121
 122         return ret;
 123 }
 124
 125 int board_mmc_init(struct bd_info *bis)
 126 {
 127         static const iomux_v3_cfg_t sd1_pads[] = {
 128                 NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
 129                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 130                 NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
 131                         PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 132                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
 133                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 134                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
 135                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 136                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
 137                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 138                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
 139                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
 140                 NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
 141                 NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
 142         };
 143
 144         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 145
 146         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 147
 148         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 149 }
 150 #endif
 151
 152 int board_early_init_f(void)
 153 {
 154         setup_iomux_uart();
 155         setup_iomux_fec();
 156
 157         return 0;
 158 }
 159
 160 int board_init(void)
 161 {
 162         /* address of boot parameters */
 163         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 164
 165         return 0;
 166 }
 167
 168 /*
 169  * Read the MAC address from FEC's registers PALR PAUR.
 170  * User is supposed to configure these registers when MAC address is known
 171  * from another source (fuse), but on TS4800, MAC address is not fused and
 172  * the bootrom configure these registers on startup.
 173  */
 174 static int fec_get_mac_from_register(uint32_t base_addr)
 175 {
 176         unsigned char ethaddr[6];
 177         u32 reg_mac[2];
 178         int i;
 179
 180         reg_mac[0] = in_be32(base_addr + 0xE4);
 181         reg_mac[1] = in_be32(base_addr + 0xE8);
 182
 183         for(i = 0; i < 6; i++)
 184                 ethaddr[i] = (reg_mac[i / 4] >> ((i % 4) * 8)) & 0xFF;
 185
 186         if (is_valid_ethaddr(ethaddr)) {
 187                 eth_env_set_enetaddr("ethaddr", ethaddr);
 188                 return 0;
 189         }
 190
 191         return -1;
 192 }
 193
 194 #define TS4800_GPIO_FEC_PHY_RES         IMX_GPIO_NR(2, 14)
 195 int board_eth_init(struct bd_info *bd)
 196 {
 197         int dev_id = -1;
 198         int phy_id = 0xFF;
 199         uint32_t addr = IMX_FEC_BASE;
 200
 201         uint32_t base_mii;
 202         struct mii_dev *bus = NULL;
 203         struct phy_device *phydev = NULL;
 204         int ret;
 205
 206         /* reset FEC phy */
 207         imx_iomux_v3_setup_pad(MX51_PAD_EIM_A20__GPIO2_14);
 208         gpio_direction_output(TS4800_GPIO_FEC_PHY_RES, 0);
 209         mdelay(1);
 210         gpio_set_value(TS4800_GPIO_FEC_PHY_RES, 1);
 211         mdelay(1);
 212
 213         base_mii = addr;
 214         debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
 215         bus = fec_get_miibus(base_mii, dev_id);
 216         if (!bus)
 217                 return -ENOMEM;
 218
 219         phydev = phy_find_by_mask(bus, phy_id, PHY_INTERFACE_MODE_MII);
 220         if (!phydev) {
 221                 free(bus);
 222                 return -ENOMEM;
 223         }
 224
 225         if (fec_get_mac_from_register(addr))
 226                 printf("eth_init: failed to get MAC address\n");
 227
 228         ret = fec_probe(bd, dev_id, addr, bus, phydev);
 229         if (ret) {
 230                 free(phydev);
 231                 free(bus);
 232         }
 233
 234         return ret;
 235 }
 236
 237 /*
 238  * Do not overwrite the console
 239  * Use always serial for U-Boot console
 240  */
 241 int overwrite_console(void)
 242 {
 243         return 1;
 244 }
 245
 246 int checkboard(void)
 247 {
 248         puts("Board: TS4800\n");
 249
 250         return 0;
 251 }
 252
 253 void hw_watchdog_reset(void)
 254 {
 255         struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE);
 256         /* feed the watchdog for another 10s */
 257         writew(0x2, &wtd->feed);
 258 }
 259
 260 void hw_watchdog_init(void)
 261 {
 262         return;
 263 }