3 * Tapani Utriainen <linuxfae@technexion.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/mmc_host_def.h>
12 #include <asm/arch/mem.h>
13 #include <asm/arch/mux.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/arch/gpio.h>
17 #include <asm/mach-types.h>
20 #include <asm/ehci-omap.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 int tao3530_revision(void)
30 /* char *label argument is unused in gpio_request() */
31 ret = gpio_request(65, "");
33 puts("Error: GPIO 65 not available\n");
36 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4));
38 ret = gpio_request(1, "");
40 puts("Error: GPIO 1 not available\n");
43 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4));
45 ret = gpio_direction_input(65);
47 puts("Error: GPIO 65 not available for input\n");
51 ret = gpio_direction_input(1);
53 puts("Error: GPIO 1 not available for input\n");
57 ret = gpio_get_value(65) << 1 | gpio_get_value(1);
60 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M0));
63 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0));
70 #ifdef CONFIG_SPL_BUILD
72 * Routine: get_board_mem_timings
73 * Description: If we use SPL then there is no x-loader nor config header
74 * so we have to setup the DDR timings ourself on both banks.
76 void get_board_mem_timings(struct board_sdrc_timings *timings)
78 if (tao3530_revision() < 3) {
80 timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */
81 timings->ctrla = HYNIX_V_ACTIMA_165;
82 timings->ctrlb = HYNIX_V_ACTIMB_165;
85 timings->mcfg = MCFG(128 << 20, 13); /* RAS-width 13 */
86 timings->ctrla = MICRON_V_ACTIMA_165;
87 timings->ctrlb = MICRON_V_ACTIMB_165;
90 timings->mr = MICRON_V_MR_165;
91 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
97 * Description: Early hardware init.
101 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
102 /* board id for Linux */
103 gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530;
104 /* boot param addr */
105 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
111 * Routine: misc_init_r
112 * Description: Configure board specific parts
114 int misc_init_r(void)
116 struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
117 struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
119 twl4030_power_init();
120 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
122 /* Configure GPIOs to output */
124 writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
125 writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 |
126 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
129 writel(GPIO10 | GPIO8 | GPIO2 | GPIO1,
130 &gpio6_base->setdataout);
131 writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
132 GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
134 switch (tao3530_revision()) {
136 puts("TAO-3530 REV Reserve 1\n");
139 puts("TAO-3530 REV Reserve 2\n");
142 puts("TAO-3530 REV Cx\n");
145 puts("TAO-3530 REV Ax/Bx\n");
148 puts("Unknown board revision\n");
157 * Routine: set_muxconf_regs
158 * Description: Setting up the configuration Mux registers specific to the
159 * hardware. Many pins need to be moved from protect to primary
162 void set_muxconf_regs(void)
167 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
168 int board_mmc_init(bd_t *bis)
170 omap_mmc_init(0, 0, 0, -1, -1);
176 #if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
177 /* Call usb_stop() before starting the kernel */
178 void show_boot_progress(int val)
180 if (val == BOOTSTAGE_ID_RUN_OS)
184 static struct omap_usbhs_board_data usbhs_bdata = {
185 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
186 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
187 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
190 int ehci_hcd_init(int index, enum usb_init_type init,
191 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
193 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
196 int ehci_hcd_stop(int index)
198 return omap_ehci_hcd_stop();
200 #endif /* CONFIG_USB_EHCI */