board/technexion/pico-imx7d/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Technexion Ltd.
   4  *
   5  * Author: Richard Hu <richard.hu@technexion.com>
   6  */
   7
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch/crm_regs.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/arch-mx7/mx7-ddr.h>
  12 #include <asm/gpio.h>
  13 #include <spl.h>
  14
  15 #if defined(CONFIG_SPL_BUILD)
  16
  17 #ifdef CONFIG_SPL_OS_BOOT
  18 int spl_start_uboot(void)
  19 {
  20         return 0;
  21 }
  22 #endif
  23
  24 static struct ddrc ddrc_regs_val = {
  25         .mstr           = 0x01040001,
  26         .rfshtmg        = 0x00400046,
  27         .init1          = 0x00690000,
  28         .init0          = 0x00020083,
  29         .init3          = 0x09300004,
  30         .init4          = 0x04080000,
  31         .init5          = 0x00100004,
  32         .rankctl        = 0x0000033F,
  33         .dramtmg0       = 0x09081109,
  34         .dramtmg1       = 0x0007020d,
  35         .dramtmg2       = 0x03040407,
  36         .dramtmg3       = 0x00002006,
  37         .dramtmg4       = 0x04020205,
  38         .dramtmg5       = 0x03030202,
  39         .dramtmg8       = 0x00000803,
  40         .zqctl0         = 0x00800020,
  41         .dfitmg0        = 0x02098204,
  42         .dfitmg1        = 0x00030303,
  43         .dfiupd0        = 0x80400003,
  44         .dfiupd1        = 0x00100020,
  45         .dfiupd2        = 0x80100004,
  46         .addrmap4       = 0x00000F0F,
  47         .odtcfg         = 0x06000604,
  48         .odtmap         = 0x00000001,
  49         .rfshtmg        = 0x00400046,
  50         .dramtmg0       = 0x09081109,
  51         .addrmap0       = 0x0000001f,
  52         .addrmap1       = 0x00080808,
  53         .addrmap4       = 0x00000f0f,
  54         .addrmap5       = 0x07070707,
  55         .addrmap6       = 0x0f0f0707,
  56 };
  57
  58 static struct ddrc_mp ddrc_mp_val = {
  59         .pctrl_0        = 0x00000001,
  60 };
  61
  62 static struct ddr_phy ddr_phy_regs_val = {
  63         .phy_con0       = 0x17420f40,
  64         .phy_con1       = 0x10210100,
  65         .phy_con4       = 0x00060807,
  66         .mdll_con0      = 0x1010007e,
  67         .drvds_con0     = 0x00000d6e,
  68         .cmd_sdll_con0  = 0x00000010,
  69         .offset_lp_con0 = 0x0000000f,
  70         .offset_rd_con0 = 0x08080808,
  71         .offset_wr_con0 = 0x08080808,
  72 };
  73
  74 static struct mx7_calibration calib_param = {
  75         .num_val        = 5,
  76         .values         = {
  77                 0x0E407304,
  78                 0x0E447304,
  79                 0x0E447306,
  80                 0x0E447304,
  81                 0x0E447304,
  82         },
  83 };
  84
  85 static void gpr_init(void)
  86 {
  87         struct iomuxc_gpr_base_regs *gpr_regs =
  88                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  89         writel(0x4F400005, &gpr_regs->gpr[1]);
  90 }
  91
  92 static bool is_1g(void)
  93 {
  94         gpio_direction_input(IMX_GPIO_NR(1, 12));
  95         return !gpio_get_value(IMX_GPIO_NR(1, 12));
  96 }
  97
  98 static void ddr_init(void)
  99 {
 100         if (is_1g())
 101                 ddrc_regs_val.addrmap6  = 0x0f070707;
 102
 103         mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
 104                      &calib_param);
 105 }
 106
 107 void board_init_f(ulong dummy)
 108 {
 109         arch_cpu_init();
 110         gpr_init();
 111         board_early_init_f();
 112         timer_init();
 113         preloader_console_init();
 114         ddr_init();
 115         memset(__bss_start, 0, __bss_end - __bss_start);
 116         board_init_r(NULL, 0);
 117 }
 118
 119 void reset_cpu(ulong addr)
 120 {
 121 }
 122 #endif