board/technexion/pico-imx7d/pico-imx7d.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 NXP Semiconductors
   4  */
   5
   6 #include <init.h>
   7 #include <net.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/crm_regs.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/mx7-pins.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/global_data.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/io.h>
  17 #include <common.h>
  18 #include <miiphy.h>
  19 #include <power/pmic.h>
  20 #include <power/pfuze3000_pmic.h>
  21 #include "../../freescale/common/pfuze.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  26         PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  27
  28 int dram_init(void)
  29 {
  30         gd->ram_size = imx_ddr_size();
  31
  32         /* Subtract the defined OPTEE runtime firmware length */
  33 #ifdef CONFIG_OPTEE_TZDRAM_SIZE
  34                 gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
  35 #endif
  36
  37         return 0;
  38 }
  39
  40 #if CONFIG_IS_ENABLED(DM_PMIC)
  41 int power_init_board(void)
  42 {
  43         struct udevice *dev;
  44         int reg, rev_id;
  45         int ret;
  46
  47         ret = pmic_get("pfuze3000@8", &dev);
  48         if (ret == -ENODEV)
  49                 return 0;
  50         if (ret != 0)
  51                 return ret;
  52
  53         reg = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  54         rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  55         printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
  56
  57         /* disable Low Power Mode during standby mode */
  58         reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
  59         reg |= 0x1;
  60         pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
  61
  62         /* SW1A/1B mode set to APS/APS */
  63         reg = 0x8;
  64         pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
  65         pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
  66
  67         /* SW1A/1B standby voltage set to 1.025V */
  68         reg = 0xd;
  69         pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
  70         pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
  71
  72         /* decrease SW1B normal voltage to 0.975V */
  73         reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
  74         reg &= ~0x1f;
  75         reg |= PFUZE3000_SW1AB_SETP(975);
  76         pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
  77
  78         return 0;
  79 }
  80 #endif
  81
  82 static iomux_v3_cfg_t const wdog_pads[] = {
  83         MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  84 };
  85
  86 static iomux_v3_cfg_t const uart5_pads[] = {
  87         MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  88         MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  89 };
  90
  91 #ifdef CONFIG_FEC_MXC
  92 static int setup_fec(void)
  93 {
  94         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  95                 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  96
  97         /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
  98         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  99                         (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
 100                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
 101
 102         return set_clk_enet(ENET_125MHZ);
 103 }
 104
 105 int board_phy_config(struct phy_device *phydev)
 106 {
 107         unsigned short val;
 108
 109         /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
 110         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 111         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 112         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 113
 114         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 115         val &= 0xffe7;
 116         val |= 0x18;
 117         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 118
 119         /* introduce tx clock delay */
 120         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 121         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 122         val |= 0x0100;
 123         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 124
 125         if (phydev->drv->config)
 126                 phydev->drv->config(phydev);
 127
 128         return 0;
 129 }
 130 #endif
 131
 132 static void setup_iomux_uart(void)
 133 {
 134         imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
 135 }
 136
 137 int board_early_init_f(void)
 138 {
 139         setup_iomux_uart();
 140
 141         return 0;
 142 }
 143
 144 #ifdef CONFIG_VIDEO
 145 void setup_lcd(void)
 146 {
 147         gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness");
 148         gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable");
 149         /* Set Brightness to high */
 150         gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
 151         /* Set LCD enable to high */
 152         gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
 153 }
 154 #endif
 155
 156 int board_init(void)
 157 {
 158         /* address of boot parameters */
 159         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 160
 161 #ifdef CONFIG_VIDEO
 162         setup_lcd();
 163 #endif
 164 #ifdef CONFIG_FEC_MXC
 165         setup_fec();
 166 #endif
 167
 168         return 0;
 169 }
 170
 171 int board_late_init(void)
 172 {
 173         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 174
 175         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 176
 177         set_wdog_reset(wdog);
 178
 179         /*
 180          * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
 181          * since we use PMIC_PWRON to reset the board.
 182          */
 183         clrsetbits_le16(&wdog->wcr, 0, 0x10);
 184
 185         return 0;
 186 }
 187
 188 int checkboard(void)
 189 {
 190         puts("Board: i.MX7D PICOSOM\n");
 191
 192         return 0;
 193 }
 194
 195 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 196         MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 197 };
 198
 199 int board_ehci_hcd_init(int port)
 200 {
 201         switch (port) {
 202         case 0:
 203                 break;
 204         case 1:
 205                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 206                                                  ARRAY_SIZE(usb_otg2_pads));
 207                 break;
 208         default:
 209                 return -EINVAL;
 210         }
 211         return 0;
 212 }